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MC9S12HZ256
Data Sheet Covers MC9S12HZ128, MC9S12HZ64, MC9S12HN64 MC3S12HZ256, MC3S12HZ128, MC3S12HZ64, MC3S12HN64, MC3S12HZ32 & MC3S12HN32
HCS12 Microcontrollers
MC9S12HZ256V2 Rev. 2.05 04/2008
freescale.com
MC9S12HZ256 Data Sheet
MC9S12HZ256V2 Rev. 2.05 04/2008
This document contains information for all constituent modules, with the exception of the S12 CPU. For S12 CPU information please refer to the CPU S12 Reference Manual. To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ The following revision history table summarizes changes contained in this document.
Revision History
Date October 10, 2005 Revision Level 02.01 New Data Sheet Corrected Table 4-1 Port U and Port V descriptions Added 80QFP to PCB layout guidelines Added derivative differences to appendix D Updated ordering information on appendix E Added ROM to memory options Updated memory map figures and added tables for RAM mapping options Added ROM derivatives to appendix D Added ROM description to appendices (appendix E) Added MC3S12HZ64 mask set Updated Table A-5 Thermal Package Characteristics Updated Table A-17 PLL Characteristics Added MC3S12HZ64 Pinout. Figure 1-7 Corrected register map typo. Description
April 20, 2006
02.02
October 5, 2006
02.03
October 31, 2006
02.04
April 25, 2008
02.05
FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash(R) technology licensed from SST. (c) Freescale Semiconductor, Inc., 2006. All rights reserved. MC9S12HZ256 Data Sheet, Rev. 2.05 4 Freescale Semiconductor
Chapter 1 Chapter 2 Chapter 3 Chapter 4 Chapter 5 Chapter 6 Chapter 7 Chapter 8 Chapter 9 Chapter 10 Chapter 11 Chapter 12 Chapter 13 Chapter 14 Chapter 15 Chapter 16 Chapter 17 Chapter 18 Chapter 19 Chapter 20 Chapter 21 Chapter 22
MC9S12HZ256 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . 21 256 Kbyte Flash Module (FTS256K2V1) . . . . . . . . . . . . . . . . . . 57 2 Kbyte EEPROM Module (EETS2KV1). . . . . . . . . . . . . . . . . . . 95 Port Integration Module (PIM9HZ256V2) . . . . . . . . . . . . . . . . 115 Clocks and Reset Generator (CRGV4) . . . . . . . . . . . . . . . . . . 167 Oscillator (OSCV2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Analog-to-Digital Converter (ATD10B16CV4) . . . . . . . . . . . . 207 Liquid Crystal Display (LCD32F4BV1) . . . . . . . . . . . . . . . . . . 241 Motor Controller (MC10B8CV1). . . . . . . . . . . . . . . . . . . . . . . . 259 Stepper Stall Detector (SSDV1). . . . . . . . . . . . . . . . . . . . . . . . 291 Inter-Integrated Circuit (IICV2) . . . . . . . . . . . . . . . . . . . . . . . . 309 Freescale's Scalable Controller Area Network (MSCANV2) . 333 Serial Communication Interface (SCIV4) . . . . . . . . . . . . . . . . 387 Serial Peripheral Interface (SPIV3) . . . . . . . . . . . . . . . . . . . . . 419 Pulse-Width Modulator (PWM8B6CV1). . . . . . . . . . . . . . . . . . 441 Timer Module (TIM16B8CV1) . . . . . . . . . . . . . . . . . . . . . . . . . . 475 Dual Output Voltage Regulator (VREG3V3V2). . . . . . . . . . . . 501 Background Debug Module (BDMV4). . . . . . . . . . . . . . . . . . . 509 Debug Module (DBGV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535 Interrupt (INTV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567 Multiplexed External Bus Interface (MEBIV3) . . . . . . . . . . . . 575 Module Mapping Control (MMCV4) . . . . . . . . . . . . . . . . . . . . . 603
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Appendix A Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623 Appendix B PCB Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655 Appendix C Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658 Appendix D Derivative Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661 Appendix E ROM Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662 Appendix F Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666 Appendix G Detailed Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667
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Chapter 1 MC9S12HZ256 Device Overview
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.2 Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.3 Part ID Assignments and Mask Set Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.4 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.4.1 Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.4.2 Signal Properties Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 1.5 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 1.5.1 EXTAL, XTAL -- Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 1.5.2 RESET -- External Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 1.5.3 TEST -- Test Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 1.5.4 XFC -- PLL Loop Filter Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 1.5.5 BKGD / TAGHI / MODC -- Background Debug, Tag High, and Mode Pin . . . . . . . . . 38 1.5.6 Port Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 1.5.7 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 1.6 System Clock Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 1.7 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 1.7.1 Normal Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 1.7.2 Special Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 1.8 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 1.8.1 Securing the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 1.8.2 Operation of the Secured Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 1.8.3 Unsecuring the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 1.9 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 1.10 Resets and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 1.10.1 Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 1.10.2 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 1.10.3 Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Chapter 2 256 Kbyte Flash Module (FTS256K2V1)
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 2.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 2.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 2.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 2.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 7
2.2 2.3
2.4 2.5
2.6
2.7
2.8
External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 2.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 2.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 2.4.1 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 2.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 2.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 2.5.3 Background Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Flash Module Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 2.6.1 Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 2.6.2 Unsecuring the Flash Module in Special Single-Chip Mode using BDM . . . . . . . . . . . . 93 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 2.7.1 Flash Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 2.7.2 Reset While Flash Command Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 2.8.1 Description of Flash Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Chapter 3 2 Kbyte EEPROM Module (EETS2KV1)
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 3.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 3.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 3.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 3.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 3.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 3.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 3.4.1 Program and Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 3.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 3.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 3.5.3 Background Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
3.2 3.3
3.4 3.5
3.6 3.7
MC9S12HZ256 Data Sheet, Rev. 2.05 8 Freescale Semiconductor
Chapter 4 Port Integration Module (PIM9HZ256V2)
4.1 lntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 4.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 4.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 4.3.1 Port AD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 4.3.2 Port L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 4.3.3 Port M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 4.3.4 Port P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 4.3.5 Port S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 4.3.6 Port T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 4.3.7 Port U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 4.3.8 Port V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 4.4.1 I/O Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 4.4.2 Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 4.4.3 Data Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 4.4.4 Reduced Drive Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 4.4.5 Pull Device Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 4.4.6 Polarity Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 4.4.7 Pin Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 4.5.1 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 4.6.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 4.6.2 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 4.6.3 Operation in Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
4.2 4.3
4.4
4.5 4.6
Chapter 5 Clocks and Reset Generator (CRGV4)
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 5.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 5.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 5.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 5.2.1 VDDPLL, VSSPLL -- PLL Operating Voltage, PLL Ground . . . . . . . . . . . . . . . . . . . . . . 169 5.2.2 XFC -- PLL Loop Filter Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 5.2.3 RESET -- Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 5.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 5.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
5.2
5.3
5.4
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5.6
5.4.1 Phase Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 5.4.2 System Clocks Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 5.4.3 Clock Monitor (CM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 5.4.4 Clock Quality Checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 5.4.5 Computer Operating Properly Watchdog (COP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 5.4.6 Real-Time Interrupt (RTI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 5.4.7 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 5.4.8 Low-Power Operation in Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 5.4.9 Low-Power Operation in Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 5.4.10 Low-Power Operation in Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 5.5.1 Clock Monitor Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 5.5.2 Computer Operating Properly Watchdog (COP) Reset . . . . . . . . . . . . . . . . . . . . . . . . . 200 5.5.3 Power-On Reset, Low Voltage Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 5.6.1 Real-Time Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 5.6.2 PLL Lock Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 5.6.3 Self-Clock Mode Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Chapter 6 Oscillator (OSCV2)
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 6.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 6.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 6.2.1 VDDPLL and VSSPLL -- PLL Operating Voltage, PLL Ground . . . . . . . . . . . . . . . . . . . 204 6.2.2 EXTAL and XTAL -- Clock/Crystal Source Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 6.2.3 XCLKS -- Colpitts/Pierce Oscillator Selection Signal . . . . . . . . . . . . . . . . . . . . . . . . . 205 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 6.4.1 Amplitude Limitation Control (ALC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 6.4.2 Clock Monitor (CM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
6.2
6.3 6.4
6.5
Chapter 7 Analog-to-Digital Converter (ATD10B16CV4)
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 7.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 7.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 7.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 7.2.1 ANx (x = 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) -- Analog Input Channel x Pins 209 7.2.2 ETRIG3, ETRIG2, ETRIG1, ETRIG0 -- External Trigger Pins . . . . . . . . . . . . . . . . . 209
7.2
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7.3
7.4
7.5 7.6
7.2.3 VRH, VRL -- High Reference Voltage Pin, Low Reference Voltage Pin . . . . . . . . . . . . 209 7.2.4 VDDA, VSSA -- Analog Circuitry Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . 209 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 7.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 7.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 7.4.1 Analog Sub-block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 7.4.2 Digital Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 7.4.3 Operation in Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Chapter 8 Liquid Crystal Display (LCD32F4BV1)
8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 8.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 8.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 8.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 8.2.1 BP[3:0] -- Analog Backplane Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 8.2.2 FP[31:0] -- Analog Frontplane Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 8.2.3 VLCD -- LCD Supply Voltage Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 8.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 8.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 8.4.1 LCD Driver Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 8.4.2 Operation in Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 8.4.3 Operation in Pseudo Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 8.4.4 Operation in Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 8.4.5 LCD Waveform Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
8.2
8.3
8.4
8.5 8.6
Chapter 9 Motor Controller (MC10B8CV1)
9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 9.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 9.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 9.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 9.2.1 M0C0M/M0C0P/M0C1M/M0C1P -- PWM Output Pins for Motor 0 . . . . . . . . . . . . 262 9.2.2 M1C0M/M1C0P/M1C1M/M1C1P -- PWM Output Pins for Motor 1 . . . . . . . . . . . . 262 9.2.3 M2C0M/M2C0P/M2C1M/M2C1P -- PWM Output Pins for Motor 2 . . . . . . . . . . . . 262
9.2
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9.3
9.4
9.5 9.6 9.7
9.2.4 M3C0M/M3C0P/M3C1M/M3C1P -- PWM Output Pins for Motor 3 . . . . . . . . . . . . 263 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 9.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 9.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 9.4.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 9.4.2 PWM Duty Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 9.4.3 Motor Controller Counter Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 9.4.4 Output Switching Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 9.4.5 Operation in Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 9.4.6 Operation in Stop and Pseudo-Stop Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 9.6.1 Timer Counter Overflow Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 9.7.1 Code Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Chapter 10 Stepper Stall Detector (SSDV1)
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 10.1.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 10.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 10.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 10.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 10.2.1 COSxM/COSxP -- Cosine Coil Pins for Motor x . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 10.2.2 SINxM/SINxP -- Sine Coil Pins for Motor x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 10.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 10.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 10.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 10.4.1 Return to Zero Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 10.4.2 Full Step States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 10.4.3 Operation in Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 10.4.4 Stall Detection Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Chapter 11 Inter-Integrated Circuit (IICV2)
11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 11.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 11.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 11.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 11.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 11.2.1 IIC_SCL -- Serial Clock Line Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 11.2.2 IIC_SDA -- Serial Data Line Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
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11.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 11.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 11.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 11.4.1 I-Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 11.4.2 Operation in Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 11.4.3 Operation in Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 11.4.4 Operation in Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 11.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 11.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 11.7 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 11.7.1 IIC Programming Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 12.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 12.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 12.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 12.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 12.2.1 RXCAN -- CAN Receiver Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 12.2.2 TXCAN -- CAN Transmitter Output Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 12.2.3 CAN System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 12.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 12.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 12.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 12.3.3 Programmer's Model of Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 12.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 12.4.2 Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368 12.4.3 Identifier Acceptance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 12.4.4 Timer Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 12.4.5 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 12.4.6 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 12.4.7 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 12.4.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 12.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 12.5.1 MSCAN initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
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Chapter 13 Serial Communication Interface (SCIV4)
13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 13.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 13.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 13.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 13.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 13.2 External Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390 13.2.1 TXD -- SCI Transmit Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390 13.2.2 RXD -- SCI Receive Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390 13.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390 13.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390 13.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390 13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 13.4.1 Infrared Interface Submodule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401 13.4.2 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401 13.4.3 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403 13.4.4 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404 13.4.5 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407 13.4.6 Single-Wire Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415 13.4.7 Loop Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416 13.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416 13.5.1 Description of Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 13.5.2 Recovery from Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
Chapter 14 Serial Peripheral Interface (SPIV3)
14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419 14.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419 14.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419 14.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420 14.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420 14.2.1 MOSI -- Master Out/Slave In Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420 14.2.2 MISO -- Master In/Slave Out Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 14.2.3 SS -- Slave Select Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 14.2.4 SCK -- Serial Clock Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 14.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 14.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 14.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422 14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429 14.4.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430 14.4.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431 14.4.3 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432 14.4.4 SPI Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435
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14.4.5 Special Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436 14.4.6 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 14.4.7 Operation in Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438 14.4.8 Operation in Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438 14.4.9 Operation in Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438 14.5 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439 14.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439 14.6.1 MODF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439 14.6.2 SPIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439 14.6.3 SPTEF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
Chapter 15 Pulse-Width Modulator (PWM8B6CV1)
15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441 15.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441 15.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441 15.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442 15.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442 15.2.1 PWM5 -- Pulse Width Modulator Channel 5 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442 15.2.2 PWM4 -- Pulse Width Modulator Channel 4 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442 15.2.3 PWM3 -- Pulse Width Modulator Channel 3 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442 15.2.4 PWM2 -- Pulse Width Modulator Channel 2 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 15.2.5 PWM1 -- Pulse Width Modulator Channel 1 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 15.2.6 PWM0 -- Pulse Width Modulator Channel 0 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 15.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 15.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 15.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445 15.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463 15.4.1 PWM Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463 15.4.2 PWM Channel Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466 15.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473 15.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473
Chapter 16 Timer Module (TIM16B8CV1)
16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475 16.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475 16.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475 16.1.3 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476 16.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478 16.2.1 IOC7 -- Input Capture and Output Compare Channel 7 Pin . . . . . . . . . . . . . . . . . . . . 478 16.2.2 IOC6 -- Input Capture and Output Compare Channel 6 Pin . . . . . . . . . . . . . . . . . . . . 478 16.2.3 IOC5 -- Input Capture and Output Compare Channel 5 Pin . . . . . . . . . . . . . . . . . . . . 478 16.2.4 IOC4 -- Input Capture and Output Compare Channel 4 Pin . . . . . . . . . . . . . . . . . . . . 478
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16.3
16.4
16.5 16.6
16.2.5 IOC3 -- Input Capture and Output Compare Channel 3 Pin . . . . . . . . . . . . . . . . . . . . 478 16.2.6 IOC2 -- Input Capture and Output Compare Channel 2 Pin . . . . . . . . . . . . . . . . . . . . 479 16.2.7 IOC1 -- Input Capture and Output Compare Channel 1 Pin . . . . . . . . . . . . . . . . . . . . 479 16.2.8 IOC0 -- Input Capture and Output Compare Channel 0 Pin . . . . . . . . . . . . . . . . . . . . 479 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479 16.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479 16.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 16.4.1 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 16.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497 16.4.3 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497 16.4.4 Pulse Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497 16.4.5 Event Counter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498 16.4.6 Gated Time Accumulation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498 16.6.1 Channel [7:0] Interrupt (C[7:0]F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499 16.6.2 Pulse Accumulator Input Interrupt (PAOVI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499 16.6.3 Pulse Accumulator Overflow Interrupt (PAOVF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499 16.6.4 Timer Overflow Interrupt (TOF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499
Chapter 17 Dual Output Voltage Regulator (VREG3V3V2)
17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501 17.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501 17.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501 17.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502 17.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503 17.2.1 VDDR -- Regulator Power Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503 17.2.2 VDDA, VSSA -- Regulator Reference Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503 17.2.3 VDD, VSS -- Regulator Output1 (Core Logic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504 17.2.4 VDDPLL, VSSPLL -- Regulator Output2 (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504 17.2.5 VREGEN -- Optional Regulator Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504 17.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504 17.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504 17.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505 17.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505 17.4.1 REG -- Regulator Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505 17.4.2 Full-Performance Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506 17.4.3 Reduced-Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506 17.4.4 LVD -- Low-Voltage Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506 17.4.5 POR -- Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506 17.4.6 LVR -- Low-Voltage Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506 17.4.7 CTRL -- Regulator Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506 17.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507
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17.5.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507 17.5.2 Low-Voltage Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507 17.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507 17.6.1 LVI -- Low-Voltage Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507
Chapter 18 Background Debug Module (BDMV4)
18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509 18.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509 18.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 18.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 18.2.1 BKGD -- Background Interface Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 18.2.2 TAGHI -- High Byte Instruction Tagging Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 18.2.3 TAGLO -- Low Byte Instruction Tagging Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 18.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512 18.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512 18.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513 18.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518 18.4.1 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518 18.4.2 Enabling and Activating BDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518 18.4.3 BDM Hardware Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519 18.4.4 Standard BDM Firmware Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520 18.4.5 BDM Command Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521 18.4.6 BDM Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523 18.4.7 Serial Interface Hardware Handshake Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526 18.4.8 Hardware Handshake Abort Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528 18.4.9 SYNC -- Request Timed Reference Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531 18.4.10Instruction Tracing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531 18.4.11Instruction Tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532 18.4.12Serial Communication Time-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532 18.4.13Operation in Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533 18.4.14Operation in Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533
Chapter 19 Debug Module (DBGV1)
19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535 19.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535 19.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537 19.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537 19.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539 19.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540 19.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540 19.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540 19.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555
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19.4.1 DBG Operating in BKP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555 19.4.2 DBG Operating in DBG Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557 19.4.3 Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564 19.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565 19.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565
Chapter 20 Interrupt (INTV1)
20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567 20.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568 20.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568 20.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569 20.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569 20.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569 20.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569 20.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571 20.4.1 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571 20.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 20.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 20.6.1 Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 20.6.2 Highest Priority I-Bit Maskable Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 20.6.3 Interrupt Priority Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 20.7 Exception Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573
Chapter 21 Multiplexed External Bus Interface (MEBIV3)
21.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575 21.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575 21.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577 21.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577 21.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579 21.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580 21.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580 21.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596 21.4.1 Detecting Access Type from External Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596 21.4.2 Stretched Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597 21.4.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597 21.4.4 Internal Visibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602 21.4.5 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602
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Chapter 22 Module Mapping Control (MMCV4)
22.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603 22.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604 22.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604 22.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604 22.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604 22.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604 22.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606 22.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615 22.4.1 Bus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615 22.4.2 Address Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616 22.4.3 Memory Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617
Appendix A Electrical Characteristics
A.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623 A.1.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623 A.1.2 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623 A.1.3 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624 A.1.4 Current Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625 A.1.5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625 A.1.6 ESD Protection and Latch-up Immunity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626 A.1.7 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627 A.1.8 Power Dissipation and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628 A.1.9 I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629 A.1.10 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630 A.2 ATD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632 A.2.1 ATD Operating Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632 A.2.2 Factors influencing accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632 A.2.3 ATD accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634 A.3 NVM, Flash and EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636 A.3.1 NVM timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636 A.3.2 NVM Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638 A.4 Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639 A.4.1 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639 A.4.2 Chip Power-up and Voltage Drops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639 A.4.3 Output Loads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640 A.5 Reset, Oscillator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641 A.5.1 Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641 A.5.2 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643 A.5.3 Phase Locked Loop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644 A.6 MSCAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648 A.7 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 19
A.7.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648 A.7.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650 A.8 LCD_32F4B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651 A.9 External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651
Appendix B PCB Layout Guidelines Appendix C Package Information
C.1 112-Pin LQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659 C.2 80-Pin QFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660
Appendix D Derivative Differences Appendix E ROM Description
E.1 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662 E.1.1 ROM Options Register (ROPT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662 E.1.2 ROM Configuration Register (RCNFG). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663 E.1.3 Device SC Number Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664 E.1.4 Non-volatile Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664 ROM Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665 E.2.1 Security and Backdoor Key Access definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665 E.2.2 Unsecuring the MCU using the Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . 665
E.2
Appendix F Ordering Information Appendix G Detailed Register Map
MC9S12HZ256 Data Sheet, Rev. 2.05 20 Freescale Semiconductor
Chapter 1 MC9S12HZ256 Device Overview
1.1 Introduction
The MC9S12HZ256 microcontroller units (MCU) are 16-bit devices composed of standard on-chip peripherals including a 16-bit central processing unit (HCS12 CPU), up to 256K bytes of Flash EEPROM or ROM, up to 12K bytes of RAM, 2K bytes of EEPROM, two asynchronous serial communications interfaces (SCI), a serial peripheral interface (SPI), an IIC-bus interface (IIC), an 8-channel 16-bit timer (TIM), a 16-channel, 10-bit analog-to-digital converter (ATD), a six-channel pulse width modulator (PWM), and two CAN 2.0 A, B software compatible modules (MSCAN). In addition, they feature a 32x4 liquid crystal display (LCD) controller/driver, a pulse width modulator motor controller (MC) consisting of 16 high current outputs suited to drive up to four stepper motors, and four stepper stall detectors (SSD) to simultaneously calibrate the pointer position of each motor. System resource mapping, clock generation, interrupt control, and external bus interfacing are managed by the HCS12 Core. The MC9S12HZ256 have full 16-bit data paths throughout. The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirements. In addition to the I/O ports available in each module, 8 general-purpose I/O pins are available with interrupt and wake-up capability from stop or wait mode. For information regarding the HCS12 CPU instruction set, please see the HCS12 CPU Reference Manual, Freescale document order number S12CPUV2.
1.1.1
*
Features
HCS12 core - 16-bit HCS12 CPU Upward compatible with M68HC11 instruction set Interrupt stacking and programmer's model identical to M68HC11 16-bit ALU Instruction queue Enhanced indexed addressing - MEBI (multiplexed external bus interface) - MMC (module mapping control) - INT (interrupt control) - DBG (debugger and breakpoints) - BDM (background debug mode)
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 21
Chapter 1 MC9S12HZ256 Device Overview
*
* *
*
*
*
*
*
*
Memory - 256K, 128K, 64K, 32K Flash EEPROM or ROM - 2K, 1K byte EEPROM - 12K, 6K, 4K, 2K byte RAM CRG (low current oscillator, PLL, reset, clocks, COP watchdog, real time interrupt, clock monitor) Analog-to-digital converter - 16 channels, 10-bit resolution - External conversion trigger capability Two 1-Mbps, CAN 2.0 A, B software compatible modules - Five receive and three transmit buffers - Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit - Four separate interrupt channels for Rx, Tx, error and wake-up - Low-pass filter wake-up function - Loop-back for self test operation Timer - 16-bit main counter with 7-bit prescaler - 8 programmable input capture or output compare channels - Two 8-bit or one 16-bit pulse accumulators 6 PWM channels - Programmable period and duty cycle - 8-bit 6-channel or 16-bit 3-channel - Separate control for each pulse width and duty cycle - Center-aligned or left-aligned outputs - Programmable clock select logic with a wide range of frequencies - Fast emergency shutdown input Serial interfaces - Two asynchronous serial communications interfaces (SCI) - Synchronous serial peripheral interface (SPI) - Inter-integrated circuit interface (IIC) Liquid crystal display (LCD) driver with variable input voltage - Configurable for up to 32 frontplanes and 4 backplanes or general-purpose input or output - 5 modes of operation allow for different display sizes to meet application requirements - Unused frontplane and backplane pins can be used as general-purpose I/O PWM motor controller (MC) with 16 high current drivers - Each PWM channel switchable between two drivers in an H-bridge configuration - Left, right and center aligned outputs - Support for sine and cosine drive - Dithering - Output slew rate control
MC9S12HZ256 Data Sheet, Rev. 2.05
22
Freescale Semiconductor
Chapter 1 MC9S12HZ256 Device Overview
*
*
* *
Four stepper stall detectors (SSD) - Full step control during return to zero - Voltage detector and integrator / sigma delta converter circuit - 16-bit accumulator register - 16-bit modulus down counter 112-pin LQFP and 80-pin QFP packages - 85 I/O lines with 5-V input and drive capability - 5-V A/D converter inputs - 8 key wake up interrupts with digital filtering and programmable rising/falling edge trigger Operation at 50 MHz equivalent to 25-MHz bus speed Development support - Single-wire background debugTM mode (BDM) - Debugger and on-chip hardware breakpoints
1.1.2
Modes of Operation
User modes * Normal and emulation operating modes - Normal single-chip mode - Normal expanded wide mode - Normal expanded narrow mode - Emulation expanded wide mode - Emulation expanded narrow mode * Special operating mode - Special single-chip mode with active background debug mode Low-power modes * Stop mode * Pseudo stop mode * Wait mode
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 23
Chapter 1 MC9S12HZ256 Device Overview
1.1.3
Block Diagram
VDDR VDD1 VSS1,2
Voltage Regulator 256K, 128K, 64K, 32K Bytes Flash or ROM 2K Bytes EEPROM 12K, 6K, 4K, 2K Bytes RAM
AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15
Analog to VSSA VRH Digital Converter VRL
VDDA
VDDA VSSA VRH VRL KWAD0 KWAD1 KWAD2 KWAD3 KWAD4 KWAD5 KWAD6 KWAD7 PW0 PAD0 PAD1 PAD2 PAD3 PAD4 PAD5 PAD6 PAD7 PP0 PP1 PP2 PP3 PP4 PP5 PM2 PM3 PM4 PM5 PS0 PS1
BKGD XFC VDDPLL VSSPLL EXTAL XTAL RESET TEST PE0 PE1 PE4 PE5 PE6 VLCD XADDR14 XADDR15 XADDR16 XADDR17 DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 PK0 PK1 PK2 PK3 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PL0 PL1 PL2 PL3 PL4 PL5 PL6 PL7 PE2 PE3 PE7 PK7 PT0 PT1 PT2 PT3 PT4 PT5 PT6 PT7
Single-Wire Background Debug Module Clock and Reset Generation Module
S12 CPU Periodic Interrupt COP Watchdog Clock Monitor
AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 TXD1
DDRAD DDRP DDRM
RXD1
Breakpoints
IIC CAN0 CAN1 SCI0
SDA SCL
PW4 PW5 RXCAN0 TXCAN0 RXCAN1 TXCAN1 RXD0 TXD0
XIRQ IRQ ECLK MODA MODB VLCD BP0 BP1 BP2 BP3 FP0 FP1 FP2 FP3 FP4 FP5 FP6 FP7 FP8 FP9 FP10 FP11 FP12 FP13 FP14 FP15 FP16 FP17 FP18 FP19 FP28 FP29 FP30 FP31 FP20 FP21 FP22 FP23 FP24 FP25 FP26 FP27 IOC4 IOC5 IOC6 IOC7
DDRE
PTE
System Integration Module
PIX0 PIX1 PIX2 PIX3 ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15
PPAGE
DDRK
PTK
DDRS PTS
PTM
PTP
PLL
SCI1
PW1 Pulse PW2 Width Modulator PW3
PTAD
SPI Multiplexed Address/Data Bus DDRB
MISO MOSI SCK SS
PS4 PS5 PS6 PS7 PU0 PU1 PU2 PU3 PU4 PU5 PU6 PU7 VDDM1,2,3 VSSM1,2,3 PV0 PV1 PV2 PV3 PV4 PV5 PV6 PV7
PTB
LCD Driver
SSD0
SSD1
DDRA
M0COSM M0COSP M0SINM M0SINP M1COSM M1COSP M1SINM M1SINP
PWM0 PWM1 PWM2 PWM3
M0C0M M0C0P M0C1M M0C1P M1C0M M1C0P M1C1M M1C1P
DDRU DDRV
PTA
MOTOR0,1, 2 3 Supply
M2COSM M2COSP M2SINM M2SINP M3COSM M3COSP M3SINM M3SINP
PWM4 PWM5 PWM6 PWM7
SSD2
DDRL
Multiplexed Multiplexed Wide Narrow Bus Bus
SSD3
M2C0M M2C0P M2C1M M2C1P M3C0M M3C0P M3C1M M3C1P
PTL
DDRE
R/W LSTRB/TAGLO NOACC/XCLKS ECS/ROMCTL IOC0 IOC1 IOC2 IOC3
PTE
DDRT
PTT
DDRK
PTK
Input Capture and Output Compare Timer
Figure 1-1. MC9S12HZ256 Block Diagram
MC9S12HZ256 Data Sheet, Rev. 2.05 24 Freescale Semiconductor
PTV
PTU
Chapter 1 MC9S12HZ256 Device Overview
1.2
Device Memory Map
Table 1-1 shows the device memory map for the MC9S12HZ256 out of reset.
Table 1-1. Device Register Map Overview
Address Offset 0x0000-0x0017 0x0018-0x0019 0x001A-0x001B 0x001C-0x001F 0x0020-0x0027 0x0028-0x002F 0x0030-0x0033 0x0034-0x003F 0x0040-0x006F 0x0070-0x007F 0x0080-0x00AF 0x00B0-0x00BF 0x00C0-0x00C7 0x00C8-0x00CF 0x00D0-0x00D7 0x00D8-0x00DF 0x00E0-0x00FF 0x0100-0x010F 0x0110-0x011B 0x011C-0x011F 0x0120-0x0137 0x0140-0x017F 0x0180-0x01BF 0x01C0-0x01FF 0x0200-0x027F 0x0280-0x0287 0x0288-0x028F 0x0290-0x0297 0x0298-0x029F 0x02A0-0x02A7 0x02A8-0x03FF Module HCS12 Core (Ports A, B, E, Modes, Inits, Test) Reserved Device ID register (PARTID) HCS12 Core (MEMSIZ, IRQ, HPRIO) Reserved HCS12 Core (Background Debug Mode) HCS12 Core (PPAGE, Port K) Clock and Reset Generator (PLL, RTI, COP) Standard Timer Module 16-bit 8 channels (TIM) Reserved Analog-to-Digital Converter 10-bit 16 channels (ATD) Reserved Inter Integrated Circuit (IIC) Serial Communications Interface 0 (SCI0) Serial Communications Interface 1 (SCI1) Serial Peripheral Interface (SPI) Pulse Width Modulator 8-bit 6 channels (PWM) Flash control registers EEPROM control registers Reserved Liquid Crystal Display Driver 32x4 (LCD) Scalable Controller Area Network 0 (MSCAN0) Scalable Controller Area Network 1 (MSCAN1) Motor Control Module (MC) Port Integration Module (PIM) Reserved Stepper Stall Detector 0 (SSD0) Stepper Stall Detector 1 (SSD1) Stepper Stall Detector 2 (SSD2) Stepper Stall Detector 3 (SSD3) Reserved Size (Bytes) 24 2 2 4 8 8 4 12 48 16 48 16 8 8 8 8 32 16 12 4 24 64 64 64 128 8 8 8 8 8 344
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 25
Chapter 1 MC9S12HZ256 Device Overview
Figure 1-2 shows the device memory map for the MC9(3)S12HZ256 out of reset.
0x0000 0x0000 0x0400 0x0800 0x1000 0x07FF 0x1000 0x03FF 0x0000 1K Register Space Mappable to any 2K Boundary 2K Bytes EEPROM^ 1K overlapped by register space Mappable to any 2K Boundary 12K Bytes RAM See table below for mapping options
0x4000
0x3FFF 0x4000 0.5K, 1K, 2K or 4K Protected Sector
0x7FFF 0x8000 0x8000 EXT 0xBFFF 0xC000 0xC000
16K Fixed Flash or ROM
16K Page Window Sixteen * 16K Flash or ROM Pages
16K Fixed Flash or ROM
0xFFFF 0xFF00 0xFF00 0xFFFF VECTORS NORMAL SINGLE CHIP VECTORS EXPANDED* VECTORS SPECIAL SINGLE CHIP 0xFFFF
2K, 4K, 8K or 16K Protected Boot Sector BDM (If Active)
* Assuming that a `0' was driven onto port K7 during reset to normal expanded mode ^ EEPROM is not available in ROM device
Figure 1-2. MC9(3)S12HZ256 Memory Map
Table 1-2. MC9(3)S12HZ256 RAM mapping options
INITRM 0x00 0x39 0x40 0x79 0x80 0xB9 0xC0 0xF9 RAM location 0x0000 - 0x2FFF 0x1000 - 0x3FFF 0x4000 - 0x6FFF 0x5000 - 0x7FFF 0x8000 - 0xAFFF 0x9000 - 0xBFFF 0xC000 - 0xEFFF 0xD000 - 0xFFFF
MC9S12HZ256 Data Sheet, Rev. 2.05 26 Freescale Semiconductor
Chapter 1 MC9S12HZ256 Device Overview
Figure 1-3 shows the device memory map for the MC9(3)S12HZ128 out of reset.
0x0000 0x0000 0x0400 0x0800 0x2800 0x07FF 0x2800 0x03FF 0x0000 1K Register Space Mappable to any 2K Boundary 2K Bytes EEPROM^ 1K overlapped by register space Mappable to any 2K Boundary 6K Bytes RAM See table below for mapping options
0x4000
0x3FFF 0x4000 0.5K, 1K, 2K or 4K Protected Sector
0x7FFF 0x8000 0x8000 EXT 0xBFFF 0xC000 0xC000
16K Fixed Flash or ROM
16K Page Window Eight * 16K Flash or ROM Pages
16K Fixed Flash or ROM
0xFFFF 0xFF00 0xFF00 0xFFFF VECTORS NORMAL SINGLE CHIP VECTORS EXPANDED* VECTORS SPECIAL SINGLE CHIP 0xFFFF
2K, 4K, 8K or 16K Protected Boot Sector BDM (If Active)
* Assuming that a `0' was driven onto port K7 during reset to normal expanded mode ^ EEPROM is not available in ROM device
Figure 1-3. MC9(3)S12HZ128 Memory Map
Table 1-3. MC9(3)S12HZ128 RAM mapping options
INITRM1 0x00 0x39 0x40 0x79 0x80 0xB9 0xC0 0xF9
1
RAM location 0x0000 - 0x17FF 0x2800 - 0x3FFF 0x4000 - 0x57FF 0x6800 - 0x7FFF 0x8000 - 0x97FF 0xA800 - 0xBFFF 0xC000 - 0xD7FF 0xE800 - 0xFFFF
Reserved location
(no Flash/ROM/EEPROM access)
0x1800 - 0x2FFF 0x1000 - 0x27FF 0x5800 - 0x6FFF 0x5000 - 0x67FF 0x9800 - 0xAFFF 0x9000 - 0xA7FF 0xD800 - 0xEFFF 0xD000 - 0xE7FF
User must initialize RAM13 bit to the same value as RAMHAL bit
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 27
Chapter 1 MC9S12HZ256 Device Overview
Figure 1-4 shows the device memory map for the MC9(3)S12HZ64 and MC9(3)S12HN64 out of reset.
0x0000 0x0000 0x0400 0x0800 0x3000 0x07FF 0x3000 0x03FF 0x0000 1K Register Space Mappable to any 2K Boundary 1K Bytes EEPROM^ 1K overlapped by register space Mappable to any 2K Boundary (1K mapped twice in 2K space) 4K Bytes RAM See table below for mapping options
0x4000
0x3FFF 0x4000 0.5K, 1K, 2K or 4K Protected Sector
0x7FFF 0x8000 0x8000
16K Fixed Flash or ROM
16K Page Window Four * 16K Flash or ROM Pages
0xBFFF 0xC000 0xC000 16K Fixed Flash or ROM
0xFFFF 0xFF00 0xFF00 0xFFFF VECTORS NORMAL SINGLE CHIP VECTORS SPECIAL SINGLE CHIP 0xFFFF
2K, 4K, 8K or 16K Protected Boot Sector BDM (If Active)
^ EEPROM is not available in ROM devices
Figure 1-4. MC9(3)S12HZ64 and M9S12(3)HN64 Memory Map
Table 1-4. MC9(3)S12HZ64 and M9S12(3)HN64 RAM mapping options
INITRM1 0x00 0x39 0x40 0x79 0x80 0xB9 0xC0 0xF9
1
RAM location 0x0000 - 0x0FFF 0x3000 - 0x3FFF 0x4000 - 0x4FFF 0x7000 - 0x7FFF 0x8000 - 0x8FFF 0xB000 - 0xBFFF 0xC000 - 0xCFFF 0xF000 - 0xFFFF
Reserved location
(no Flash/ROM/EEPROM access)
0x1000 - 0x2FFF 0x1000 - 0x2FFF 0x5000 - 0x6FFF 0x5000 - 0x6FFF 0x9000 - 0xAFFF 0x9000 - 0xAFFF 0xD000 - 0xEFFF 0xD000 - 0xEFFF
User must initialize RAM13 and RAM12 bits to the same value as RAMHAL bit
MC9S12HZ256 Data Sheet, Rev. 2.05 28 Freescale Semiconductor
Chapter 1 MC9S12HZ256 Device Overview
Figure 1-5 shows the device memory map for the MC3S12HZ32 and MC93S12HN32 out of reset.
0x0000 0x0000 0x0400 0x0800 0x3800 0x3800 2K Bytes RAM See table below for mapping options 0x03FF 1K Register Space Mappable to any 2K Boundary
0x4000
0x3FFF 0x4000 0.5K, 1K, 2K or 4K Protected Sector
0x7FFF 0x8000 0x8000
16K Fixed ROM
16K Page Window Two * 16K ROM Pages
0xBFFF 0xC000 0xC000 16K Fixed ROM
0xFFFF 0xFF00 0xFF00 0xFFFF VECTORS NORMAL SINGLE CHIP VECTORS SPECIAL SINGLE CHIP 0xFFFF
2K, 4K, 8K or 16K Protected Boot Sector BDM (If Active)
Figure 1-5. MC3S12HZ32 and MC3S12HN32 Memory Map
Table 1-5. MC3S12HZ32 and MC3S12HN32 RAM mapping options
INITRM1 0x00 0x39 0x40 0x79 0x80 0xB9 0xC0 0xF9
1
RAM location 0x0000 - 0x07FF 0x3800 - 0x3FFF 0x4000 - 0x47FF 0x7800 - 0x7FFF 0x8000 - 0x87FF 0xB800 - 0xBFFF 0xC000 - 0xC7FF 0xF800 - 0xFFFF
Reserved location
(no ROM access)
0x0800 - 0x2FFF 0x1000 - 0x37FF 0x4800 - 0x6FFF 0x5000 - 0x77FF 0x8800 - 0xAFFF 0x9000 - 0xB7FF 0xC800 - 0xEFFF 0xD000 - 0xF7FF
User must initialize RAM13, RAM12 and RAM11 bits to the same value as RAMHAL bit
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 29
Chapter 1 MC9S12HZ256 Device Overview
1.3
Part ID Assignments and Mask Set Numbers
The part ID is located in two 8-bit registers PARTIDH and PARTIDL at addresses 0x001A and 0X001B, respectively. The rado-only value is a unique part ID for each revision of the chip. Table 1-6 shows the assigned part ID and Mask Set numbers.
Table 1-6. Assigned Part ID and Mask Set Numbers
Part Names MC9S12HZ256 MC9S12HZ128 MC9S12HZ64 MC9S12HN64 MC3S12HZ256 MC3S12HZ128 MC3S12HZ64 MC3S12HN64 MC3S12HZ32 MC3S12HN32 Mask Set 2L16Y/3L16Y Part ID 1
0x1402/0x1403
1M36C
0x1501
1 The coding is as follows: Bit 15-12: Major family identifier Bit 11-8: Minor family identifier Bit 7-4: Major mask set revision including fab transfers Bit 3-0: Minor non-full mask set revision
The device memory sizes are located in two 8-bit registers MEMSIZ0 and MEMZI1 (addresses 0x001C and 0x001D after reset). Table 1-7 shows the read-only values of these registers. Refer to the HCS12 MMC block description chapter for further details.
Table 1-7. Memory Size Registers
Part Names MC9S12HZ256 MC9S12HZ128 MC9S12HZ64 MC9S12HN64 MC3S12HZ256 MC3S12HZ128 MC3S12HZ64 MC3S12HN64 MC3S12HZ32 MC3S12HN32 MEMSIZ0 0x15 MEMSIZ1 0x81
0x01
0x80
MC9S12HZ256 Data Sheet, Rev. 2.05 30 Freescale Semiconductor
Chapter 1 MC9S12HZ256 Device Overview
1.4
Signal Description
This section describes signals that connect off-chip. It includes a pinout diagram, a table of signal properties, and detailed discussion of signals. It is built from the signal description sections of the block description chapters of the individual IP blocks on the device.
1.4.1
Device Pinout
The MC9S12HZ256 are available in a 112-pin quad flat pack (LQFP) and a 80-pin quad flat pack (QFP). Most pins perform two or more functions, as described in 1.5, "Detailed Signal Descriptions". Figure 1-6, Figure 1-7 and Figure 1-8 show the pin assignments.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 31
Chapter 1 MC9S12HZ256 Device Overview
112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85
PT7/IOC7 PT6/IOC6 PT5/IOC5 PT4/IOC4 PT3/IOC3/FP27 PT2/IOC2/FP26 PT1/IOC1/FP25 PT0/IOC0/FP24 VSSX1 VDDX1 PK7/ECS/ROMCTL/FP23 PE7/NOACC/XCLKS/FP22 PE3/LSTRB/TAGLO/FP21 PE2/R/W/FP20 PL3/AN11/FP19 PL2/AN10/FP18 PL1/AN9/FP17 PL0/AN8/FP16 PA7/ADDR15/DATA15/FP15 PA6/ADDR14/DATA14/FP14 PA5/ADDR13/DATA13/FP13 PA4/ADDR12/DATA12/FP12 PA3/ADDR11/DATA11/FP11 PA2/ADDR10/DATA10/FP10 PA1/ADDR9/DATA9/FP9 PA0/ADDR8/DATA8/FP8 PB7/ADDR7/DATA7/FP7 PB6/ADDR6/DATA6/FP6
FP28/AN12/PL4 FP29/AN13/PL5 FP30/AN14/PL6 FP31/AN15/PL7 VDDM1 VSSM1 M0C0M/M0COSM/PU0 M0C0P/M0COSP/PU1 M0C1M/M0SINM/PU2 M0C1P/M0SINP/PU3 M1C0M/M1COSM/PU4 M1C0P/M1COSP/PU5 M1C1M/M1SINM/PU6 M1C1P/M1SINP/PU7 VDDM2 VSSM2 M2C0M/M2COSM/PV0 M2C0P/M2COSP/PV1 M2C1M/M2SINM/PV2 M2C1P/M2SINP/PV3 M3C0M/M3COSM/PV4 M3C0P/M3COSP/PV5 M3C1M/M3SINM/PV6 M3C1P/M3SINP/PV7 VDDM3 VSSM3 SCL/PWM5/PP5 SDA/PWM4/PP4
PWM3/PP3 RXD1/PWM2/PP2 TXD1/PWM0/PP0 PWM1/PP1 RXD0/PS0 TXD0/PS1 VSS2 VDDR VDDX2 VSSX2
Figure 1-6. 112-Pin LQFP for MC9S12HZ256, MC9S12HZ128, MC3S12HZ256 and MC3S12HZ128
MC9S12HZ256 Data Sheet, Rev. 2.05 32 Freescale Semiconductor
MODC/TAGHI/BKGD
RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST RXCAN0/PM2 TXCAN0/PM3 RXCAN1/PM4 TXCAN1/PM5 MODA/IPIP0/PE5 MISO/PS4 MOSI/PS5 SCK/PS6 SS/PS7 IRQ/PE1
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
MC9S12HZ256, MC9S12HZ128, MC3S12HZ256, MC3S12HZ128 112 LQFP
84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57
PB5/ADDR5/DATA5/FP5 PB4/ADDR4/DATA4/FP4 PB3/ADDR3/DATA3/FP3 PB2/ADDR2/DATA2/FP2 PB1/ADDR1/DATA1/FP1 PB0/ADDR0/DATA0/FP0 PK0/XADDR14/BP0 PK1/XADDR15/BP1 PK2/XADDR16/BP2 PK3/XADDR17/BP3 VLCD VSS1 VDD1 PAD7/KWAD7/AN7 PAD6/KWAD6/AN6 PAD5/KWAD5/AN5 PAD4/KWAD4/AN4 PAD3/KWAD3/AN3 PAD2/KWAD2/AN2 PAD1/KWAD1/AN1 PAD0/KWAD0/AN0 VDDA VRH VRL VSSA PE0/XIRQ PE4/ECLK PE6/IPIPE1/MODB
Chapter 1 MC9S12HZ256 Device Overview
112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85
PT7/IOC7 PT6/IOC6 PT5/IOC5 PT4/IOC4 PT3/IOC3/FP27 PT2/IOC2/FP26 PT1/IOC1/FP25 PT0/IOC0/FP24 VSSX1 VDDX1 PK7/FP23 PE7/XCLKS/FP22 PE3/FP21 PE2/FP20 PL3/FP19 PL2/FP18 PL1/FP17 PL0/FP16 PA7/FP15 PA6/FP14 PA5/FP13 PA4/FP12 PA3/FP11 PA2/FP10 PA1/FP9 PA0/FP8 PB7/FP7 PB6/FP6
NC NC NC NC VDDM1 VSSM1 M0C0M/M0COSM/PU0 M0C0P/M0COSP/PU1 M0C1M/M0SINM/PU2 M0C1P/M0SINP/PU3 M1C0M/M1COSM/PU4 M1C0P/M1COSP/PU5 M1C1M/M1SINM/PU6 M1C1P/M1SINP/PU7 VDDM2 VSSM2 M2C0M/M0COSM/PV0 M2C0P/M0COSP/PV1 M2C1M/M0SINM/PV2 M2C1P/M0SINP/PV3 M3C0M/M1COSM/PV4 M3C0P/M1COSP/PV5 M3C1M/M1SINM/PV6 M3C1P/M1SINP/PV7 VDDM3 VSSM3 PWM5/PP5 PWM4/PP4
PWM3/PP3 NC NC PWM1/PP1 RXD0/PS0 TXD0/PS1 VSS2 VDDR VDDX2 VSSX2
Figure 1-7. 112-Pin LQFP for MC9S12HZ(N)64 and MC3S12HZ(N)64
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 33
RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST RXCAN0/PM2 TXCAN0/PM3 NC NC NC MISO/PS4 MOSI/PS5 SCK/PS6 NC NC
MODC/BKGD
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
MC9S12HZ64, MC9S12HN64, MC3S12HZ64, MC3S12HN64 112 LQFP
Signals shown in BOLD are not available in the 80 QFP package
84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57
PB5/FP5 PB4/FP4 NC NC NC NC PK0/BP0 PK1/BP1 PK2/BP2 PK3/BP3 VLCD VSS1 VDD1 PAD7/KWAD7/AN7 PAD6/KWAD6/AN6 PAD5/KWAD5/AN5 PAD4/KWAD4/AN4 PAD3/KWAD3/AN3 PAD2/KWAD2/AN2 PAD1/KWAD1/AN1 PAD0/KWAD0/AN0 VDDA/VRH NC NC VSSA/VRL PE0/XIRQ PE4/ECLK NC
Chapter 1 MC9S12HZ256 Device Overview
M0C0M/M0COSM/PU0 M0C0P/M0COSP/PU1 M0C1M/M0SINM/PU2 M0C1P/M0SINP/PU3 M1C0M/M1COSM/PU4 M1C0P/M1COSP/PU5 M1C1M/M1SINM/PU6 M1C1P/M1SINP/PU7 VDDM2 VSSM2 M2C0M/M0COSM/PV0 M2C0P/M0COSP/PV1 M2C1M/M0SINM/PV2 M2C1P/M0SINP/PV3 M3C0M/M1COSM/PV4 M3C0P/M1COSP/PV5 M3C1M/M1SINM/PV6 M3C1P/M1SINP/PV7 PWM5/PP5 PWM4/PP4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
PT3/IOC3/FP27 PT2/IOC2/FP26 PT1/IOC1/FP25 PT0/IOC0/FP24 VSSX1 VDDX1 PK7/FP23 PE7/XCLKS/FP22 PE3/FP21 PE2/FP20 PA7/FP15 PA6/FP14 PA5/FP13 PA4/FP12 PA3/FP11 PA2/FP10 PA1/FP9 PA0/FP8 PB7/FP7 PB6/FP6
MC9S12HZ64, MC9S12HN64, MC3S12HZ64, MC3S12HN64, MC3S12HZ32, MC3S12HN32 80 QFP
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
PB5/FP5 PB4/FP4 PK0/BP0 PK1/BP1 PK2/BP2 PK3/BP3 VLCD VSS1 VDD1 PAD6/KWAD6/AN6 PAD5/KWAD5/AN5 PAD4/KWAD4/AN4 PAD3/KWAD3/AN3 PAD2/KWAD2/AN2 PAD1/KWAD1/AN1 PAD0/KWAD0/AN0 VDDA/VRH VSSA/VRL PE0/XIRQ PE4/ECLK
PWM3/PP3 PWM1/PP1 RXD0/PS0 TXD0/PS1 VSS2 VDDR VDDX2 VSSX2
Figure 1-8. 80-Pin QFP for MC9S12HZ(N)64, MC3S12HZ(N)64 and MC3S12HZ(N)32
MC9S12HZ256 Data Sheet, Rev. 2.05 34 Freescale Semiconductor
RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST RXCAN0/PM2 TXCAN0/PM3 PS4 PS6
MODC/BKGD
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Chapter 1 MC9S12HZ256 Device Overview
1.4.2
Signal Properties Summary
Table 1-8. Signal Properties
Table 1-8 summarizes all pin functions.
Pin Name Function 1 EXTAL XTAL RESET TEST XFC BKGD PAD[7:0] PA[7:0] PB[7:0] PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PK7 PK[3:0] PL[7:4] PL[3:0]
Pin Name Function 2 -- -- -- -- -- TAGHI AN[7:0] FP[15:8] FP[7:0] FP22 IPIPE1 IPIPE0 ECLK FP21 FP20 IRQ XIRQ FP23 BP[3:0] FP[31:28] FP[19:16]
Pin Name Function 3 -- -- -- -- -- MODC KWAD[7:0] ADDR[15:8]/ DATA[15:8] ADDR[7:0]/ DATA[7:0] XCLKS MODB MODA -- LSTRB R/W -- -- ECS XADDR[17:14] AN[15:12] AN[11:8]
Pin Name Function 4 -- -- -- -- -- -- -- -- -- NOACC -- -- -- TAGLO -- -- -- ROMCTL -- -- --
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Internal Pull Up Resistor Description CTRL Reset State NA NA None NA NA Up External reset pin Test input - must be tied to VSS in all applications PLL loop Filter Background debug, tag high, mode pin Oscillator pins
VDDPLL VDDPLL VDDX2 VDDX2 VDDPLL VDDX2 VDDA VDDX1 VDDX1 VDDX1 VDDX2 VDDX2 VDDX2 VDDX1 VDDX1 VDDX2 VDDX2 VDDX1 VDDX1 VDDA VDDX1
NA NA None NA NA Always Up PERAD/ PPSAD PUCR PUCR PUCR
Disabled Port AD I/O, Analog inputs (ATD), interrupts Down Down Down Port A I/O, multiplexed address/data Port B I/O, multiplexed address/data Port E I/O, access, clock select, LCD driver Port E I/O, pipe status, mode input Port E I/O, pipe status, mode input Port E I/O, bus clock output Port E I/O, LCD driver, byte strobe, tag low Port E I/O, R/W in expanded modes Port E input, maskable interrupt Port E input, non-maskable interrupt Port K I/O, emulation chip select, ROM on enable Port K I/O, LCD driver, extended addresses Port L I/O, LCD drivers, analog inputs (ATD) Port L I/O, LCD drivers, analog inputs (ATD)
While RESET pin is low: Down While RESET pin is low: Down PUCR PUCR PUCR PUCR Down Down Down
Up Up Down Down Down Down
PUCR PUCR PUCR PERL/ PPSL PERL/ PPSL
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 35
Chapter 1 MC9S12HZ256 Device Overview
Table 1-8. Signal Properties (continued)
Pin Name Function 1 PM5 PM4 PM3 PM2 PP5 PP4 PP3 PP2 PP1 PP0 PS7 PS6 PS5 PS4 PS1 PS0 PT[7:4] PT[3:0] PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 PV7 PV6 PV5 PV4 PV3 PV2 PV1 PV0 Pin Name Function 2 TXCAN1 RXCAN1 TXCAN0 RXCAN0 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 SS SCK MOSI MISO TXD0 RXD0 IOC[7:4] IOC[3:0] M1C1P M1C1M M1C0P M1C0M M0C1P M0C1M M0C0P M0C0M M3C1P M3C1M M3C0P M3C0M M2C1P M2C1M M2C0P M2C0M Pin Name Function 3 -- -- -- -- SCL SDA -- RXD1 -- TXD1 -- -- -- -- -- -- -- FP[27:24] M1SINP M1SINM M1COSP M1COSM M0SINP M0SINM M0COSP M0COSM M3SINP M3SINM M3COSP M3COSM M2SINP M2SINM M2COSP M2COSM Pin Name Function 4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- M1SINP M1SINM M1COSP M1COSM M0SINP M0SINM M0COSP M0COSM Internal Pull Up Resistor Description CTRL VDDX2 VDDX2 VDDX2 VDDX2 VDDX2 VDDX2 VDDX2 VDDX2 VDDX2 VDDX2 VDDX2 VDDX2 VDDX2 VDDX2 VDDX2 VDDX2 VDDX1 VDDX1 VDDM1,2,3 VDDM1,2,3 VDDM1,2,3 VDDM1,2,3 VDDM1,2,3 VDDM1,2,3 VDDM1,2,3 VDDM1,2,3 VDDM1,2,3 VDDM1,2,3 VDDM1,2,3 VDDM1,2,3 VDDM1,2,3 VDDM1,2,3 VDDM1,2,3 VDDM1,2,3 Port V I/O, motor 2 coil nodes of MC or SSD2 PERV/ PPSV Disabled Port V I/O, motor 3 coil nodes of MC or SSD3 Port U I/O, motor 0 coil nodes of MC or SSD0 PERT/ PPST PERU/ PPSU Down PERS/ PPSS PERP/ PPSP PERM/ PPSM Reset State Disabled Port M I/O, TX of CAN1 Port M I/O, RX of CAN1 Port M I/O, TX of CAN0 Port M I/O, RX of CAN0 Disabled Port P I/O, PWM channel, SCL of IIC Port P I/O, PWM channel, SDA of IIC Port P I/O, PWM channel Port P I/O, PWM channel, RXD of SCI1 Port P I/O, PWM channel Port P I/O, PWM channel, TXD of SCI1 Disabled Port S I/O, SS of SPI Port S I/O, SCK of SPI Port S I/O, MOSI of SPI Port S I/O, MISO of SPI Port S I/O, TXD of SCI0 Port S I/O, RXD of SCI0 Port T I/O, Timer channels Port T I/O, Timer channels, LCD driver Disabled Port U I/O, motor1 coil nodes of MC or SSD1
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MC9S12HZ256 Data Sheet, Rev. 2.05 36 Freescale Semiconductor
Chapter 1 MC9S12HZ256 Device Overview
Table 1-9. Power and Ground
Mnemonic VLCD VDD1 VSS1 VSS2 VDDR VSSR VDDX1 VDDX2 VSSX1 VSSX2 VDDA VSSA VRH VRL VDDPLL VSSPLL VDDM1,2,3 VSSM1,2,3 Nominal Voltage 5.0 V 2.5 V 0V 5.0 V 0V 5.0 V 0V 5.0 V 0V 5.0 V 0V 2.5 V 0V 5.0 V 0V Operating voltage and ground for the analog-to-digital converter and the reference for the internal voltage regulator, allows the supply voltage to the A/D to be bypassed independently. Reference voltage high for the ATD converter. Reference voltage low for the ATD converter. Provides operating voltage and ground for the phased-locked Loop. This allows the supply voltage to the PLL to be bypassed independently. Internal power and ground generated by internal regulator. Provides operating voltage and ground for motor 0, 1, 2 and 3. External power and ground, supply to pin drivers. Voltage reference pin for the LCD driver. Internal power and ground generated by internal regulator. These also allow an external source to supply the core VDD/VSS voltages and bypass the internal voltage regulator. External power and ground, supply to pin drivers and internal voltage regulator. Description
NOTE All VSS pins must be connected together in the application. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. Bypass requirements depend on MCU pin load.
1.5
1.5.1
Detailed Signal Descriptions
EXTAL, XTAL -- Oscillator Pins
EXTAL and XTAL are the crystal driver and external clock pins. On reset all the device clocks are derived from the EXTAL input frequency. XTAL is the crystal output.
1.5.2
RESET -- External Reset Pin
An active low bidirectional control signal, it acts as an input to initialize the MCU to a known start-up state, and an output when an internal MCU function causes a reset.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 37
Chapter 1 MC9S12HZ256 Device Overview
1.5.3
TEST -- Test Pin
NOTE The TEST pin must be tied to VSS in all applications.
This pin is reserved for test.
1.5.4
XFC -- PLL Loop Filter Pin
Dedicated pin used to create the PLL loop filter. Please ask your Freescale representative for the interactive application note to compute PLL loop filter elements. Any current leakage on this pin must be avoided.
XFC R MCU CS VDDPLL VDDPLL
CP
Figure 1-9. PLL Loop Filter Connections
1.5.5
BKGD / TAGHI / MODC -- Background Debug, Tag High, and Mode Pin
The BKGD/TAGHI/MODC pin is used as a pseudo-open-drain pin for the background debug communication. In MCU expanded modes of operation when instruction tagging is on, an input low on this pin during the falling edge of E-clock tags the high half of the instruction word being read into the instruction queue. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODC bit at the rising edge of RESET.
1.5.6
1.5.6.1
Port Pins
PAD[7:0] / AN[7:0] / KWAD[7:0] -- Port AD I/O Pins [7:0]
PAD7-PAD0 are general-purpose input or output pins and analog inputs for the analog-to-digital converter. They can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode.
1.5.6.2
PA[7:0] / FP[15:8] / ADDR[15:8] / DATA[15:8] -- Port A I/O Pins
PA7-PA0 are general-purpose input or output pins. They can be configured as frontplane segment driver outputs FP15-FP8 of the LCD. In MCU expanded modes of operation, these pins are used for the multiplexed external address and data bus.
MC9S12HZ256 Data Sheet, Rev. 2.05 38 Freescale Semiconductor
Chapter 1 MC9S12HZ256 Device Overview
1.5.6.3
PB[7:0] / FP[7:0] / ADDR[7:0] / DATA[7:0] -- Port B I/O Pins
PB7-PB0 are general-purpose input or output pins. They can be configured as frontplane segment driver outputs FP7-FP0 of the LCD. In MCU expanded modes of operation, these pins are used for the multiplexed external address and data bus.
1.5.6.4
PE7 / FP22 / XCLKS / NOACC -- Port E I/O Pin 7
PE7 is a general-purpose input or output pin. It can be configured as frontplane segment driver output FP22 of the LCD module. The XCLKS is an input signal which controls whether a crystal in combination with the internal Colpitts (low power) oscillator is used or whether Pierce oscillator/external clock circuitry is used. The state of this pin is latched at the rising edge of RESET. If the input is a logic high the EXTAL pin is configured for an external clock drive or a Pierce Oscillator. If the input is a logic low a Colpitts oscillator circuit is configured on EXTAL and XTAL. Because this pin is an input with a pull-down device during reset, if the pin remains floating, the default configuration is a Colpitts oscillator circuit on EXTAL and XTAL.
EXTAL CDC* MCU C1 Crystal or ceramic resonator
XTAL C2 VSSPLL
* Due to the nature of a translated ground Colpitts oscillator a DC voltage bias is applied to the crystal. Please contact the crystal manufacturer for crystal DC. Figure 1-10. Colpitts Oscillator Connections (PE7 = 0)
EXTAL
C1
MCU RS* RB
Crystal or ceramic resonator
XTAL
C2
VSSPLL
* Rs can be zero (shorted) when use with higher frequency crystals. Refer to manufacturer's data. Figure 1-11. Pierce Oscillator Connections (PE7 = 1)
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 39
Chapter 1 MC9S12HZ256 Device Overview
1.5.6.5
PE6 / MODB / IPIPE1 -- Port E I/O Pin 6
PE6 is a general-purpose input or output pin. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODB bit at the rising edge of RESET. This pin is shared with the instruction queue tracking signal IPIPE1. This pin is an input with a pull-down device which is only active when RESET is low.
1.5.6.6
PE5 / MODA / IPIPE0 -- Port E I/O Pin 5
PE5 is a general-purpose input or output pin. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODA bit at the rising edge of RESET. This pin is shared with the instruction queue tracking signal IPIPE0. This pin is an input with a pull-down device which is only active when RESET is low.
1.5.6.7
PE4 / ECLK -- Port E I/O Pin 4
PE4 is a general-purpose input or output pin. It can be configured to drive the internal bus clock ECLK. ECLK can be used as a timing reference.
1.5.6.8
PE3 / FP21 / LSTRB / TAGLO -- Port E I/O Pin 3
PE3 is a general-purpose input or output pin. It can be configured as frontplane segment driver output FP21 of the LCD module. In MCU expanded modes of operation, LSTRB is used for the low-byte strobe function to indicate the type of bus access and when instruction tagging is on, TAGLO is used to tag the low half of the instruction word being read into the instruction queue.
1.5.6.9
PE2 / FP20 / R/W -- Port E I/O Pin 2
PE2 is a general-purpose input or output pin. It can be configured as frontplane segment driver output FP20 of the LCD module. In MCU expanded modes of operations, this pin performs the read/write output signal for the external bus. It indicates the direction of data on the external bus.
1.5.6.10
PE1 / IRQ -- Port E Input Pin 1
PE1 is a general-purpose input pin and also the maskable interrupt request input that provides a means of applying asynchronous interrupt requests. If IRQ is enabled, this pin can wake up the MCU from stop or wait mode.
1.5.6.11
PE0 / XIRQ -- Port E Input Pin 0
PE0 is a general-purpose input pin and also the non-maskable interrupt request input that provides a means of applying asynchronous interrupt requests. This can wake up the MCU from stop or wait mode.
MC9S12HZ256 Data Sheet, Rev. 2.05 40 Freescale Semiconductor
Chapter 1 MC9S12HZ256 Device Overview
1.5.6.12
PK7 / FP23 / ECS / ROMCTL -- Port K I/O Pin 7
PK7 is a general-purpose input or output pin. It can be configured as frontplane segment driver output FP23 of the LCD module. During MCU expanded modes of operation, this pin is used as the emulation chip select output (ECS). During MCU expanded modes of operation, this pin is used to enable the Flash EEPROM memory in the memory map (ROMCTL). At the rising edge of RESET, the state of this pin is latched to the ROMON bit. For all other modes the reset state of the ROMON bit is as follows: Special single: ROMCTL = 1 Normal single: ROMCTL = 1 Emulation expanded wide: ROMCTL = 0 Emulation expanded narrow: ROMCTL = 0 Special test: ROMCTL = 0 Peripheral test: ROMCTL = 1
1.5.6.13
PK[3:0] / BP[3:0] / XADDR[17:14] -- Port K I/O Pins [3:0]
PK3-PK0 are general-purpose input or output pins. They can be configured as backplane segment driver outputs BP3-BP0 of the LCD module. In MCU expanded modes of operation, these pins provide the expanded address XADDR[17:14] for the external bus.
1.5.6.14
PL[7:4] / FP[31:28] / AN[15:12] -- Port L I/O Pins [7:4]
PL7-PL4 are general-purpose input or output pins. They can be configured as frontplane segment driver outputs FP31-FP28 of the LCD module or analog inputs for the analog-to-digital converter.
1.5.6.15
PL[3:0] / FP[19:16] / AN[11:8] -- Port L I/O Pins [3:0]
PL3-PL0 are general-purpose input or output pins. They can be configured as frontplane segment driver outputs FP19-FP16 of the LCD module or analog inputs for the analog-to-digital converter.
1.5.6.16
PM5 / TXCAN1 -- Port M I/O Pin 5
PM5 is a general-purpose input or output pin. It can be configured as the transmit pin TXCAN1 of the scalable controller area network controller 1 (CAN1)
1.5.6.17
PM4 / RXCAN1 -- Port M I/O Pin 4
PM4 is a general-purpose input or output pin. It can be configured as the receive pin RXCAN1 of the scalable controller area network controller 1 (CAN1)
1.5.6.18
PM3 / TXCAN0 -- Port M I/O Pin 3
PM3 is a general-purpose input or output pin. It can be configured as the transmit pin TXCAN0 of the scalable controller area network controller 0 (CAN0)
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1.5.6.19
PM2 / RXCAN0 -- Port M I/O Pin 2
PM2 is a general-purpose input or output pin. It can be configured as the receive pin RXCAN0 of the scalable controller area network controller 0 (CAN0)
1.5.6.20
PP5 / PWM5 -- Port P I/O Pin 5
PP5 is a general-purpose input or output pin. It can be configured as pulse width modulator (PWM) channel output PWM5 or the serial clock pin SCL of the inter-IC bus interface (IIC).
1.5.6.21
PP4 / PWM4 -- Port P I/O Pin 4
PP4 is a general-purpose input or output pin. It can be configured as pulse width modulator (PWM) channel output PWM4 or the serial data pin SDA of the inter-IC bus interface (IIC).
1.5.6.22
PP3 / PWM3 -- Port P I/O Pin 3
PP3 is a general-purpose input or output pin. It can be configured as pulse width modulator (PWM) channel output PWM3.
1.5.6.23
PP2 / PWM2 -- Port P I/O Pin 2
PP2 is a general-purpose input or output pin. It can be configured as pulse width modulator (PWM) channel output PWM2 or the receive pin RXD1 of the serial communication interface 1 (SCI1).
1.5.6.24
PP1 / PWM1 -- Port P I/O Pin 1
PP1 is a general-purpose input or output pin. It can be configured as pulse width modulator (PWM) channel output PWM1.
1.5.6.25
PP0 / PWM0 -- Port P I/O Pin 0
PP0 is a general-purpose input or output pin. It can be configured as pulse width modulator (PWM) channel output PWM0 or the transmit pin TXD1 of the serial communication interface 1 (SCI1).
1.5.6.26
PS7 / SS -- Port S I/O Pin 7
PS7 is a general-purpose input or output pin. It can be configured as slave select pin SS of the serial peripheral interface (SPI).
1.5.6.27
PS6 / SCK -- Port S I/O Pin 6
PS6 is a general-purpose input or output pin. It can be configured as serial clock pin SCK of the serial peripheral interface (SPI).
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1.5.6.28
PS5 / MOSI -- Port S I/O Pin 5
PS5 is a general-purpose input or output pin. It can be configured as the master output (during master mode) or slave input (during slave mode) pin MOSI of the serial peripheral interface (SPI).
1.5.6.29
PS4 / MISO -- Port S I/O Pin 4
PS4 is a general-purpose input or output pin. It can be configured as master input (during master mode) or slave output (during slave mode) pin MISO for the serial peripheral interface (SPI).
1.5.6.30
PS1 / TXD0 -- Port S I/O Pin 1
PS1 is a general-purpose input or output pin. It can be configured as transmit pin TXD0 of the serial communication interface 0 (SCI0).
1.5.6.31
PS0 / RXD0 -- Port S I/O Pin 0
PS0 is a general-purpose input or output pin. It can be configured as receive pin RXD0 of the serial communication interface 0 (SCI0).
1.5.6.32
PT[7:4] / IOC[7:4] -- Port T I/O Pins [7:4]
PT7-PT4 are general-purpose input or output pins. They can be configured as input capture or output compare pins IOC7-IOC4 of the timer (TIM).
1.5.6.33
PT[3:0] / IOC[3:0] / FP[27:24] -- Port T I/O Pins [3:0]
PT3-PT0 are general-purpose input or output pins. They can be configured as input capture or output compare pins IOC3-IOC0 of the timer (TIM). They can be configured as frontplane segment driver outputs FP27-FP24 of the LCD module.
1.5.6.34
PU[7:4] / M1C1(SIN)P, M1C1(SIN)M, M1C0(COS)P, M1C0(COS)M -- Port U I/O Pins [7:4]
PU7-PU4 are general-purpose input or output pins. They can be configured as high current PWM output pins which can be used for motor drive or to measure the back EMF to calibrate the pointer reset position. These pins interface to the coils of motor 1.
1.5.6.35
PU[3:0] / M0C1(SIN)P, M0C1(SIN)M, M0C0(COS)P, M0C0(COS)M -- Port U I/O Pins [3:0]
PU3-PU0 are general-purpose input or output pins. They can be configured as high current PWM output pins which can be used for motor drive or to measure the back EMF to calibrate the pointer reset position. These pins interface to the coils of motor 0.
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1.5.6.36
PV[7:4] / M3C1(SIN)P, M3C1(SIN)M, M3C0(COS)P, M3C0(COS)M -- Port V I/O Pins [7:4]
PV7-PV4 are general-purpose input or output pins. They can be configured as high current PWM output pins which can be used for motor drive or to measure the back EMF to calibrate the pointer reset position. These pins interface to the coils of motor 3.
1.5.6.37
PV[3:0] / M2C1(SIN)P, M2C1(SIN)M, M2C0(COS)P, M2C0(COS)M -- Port V I/O Pins [3:0]
PV3-PV0 are general-purpose input or output pins. They can be configured as high current PWM output pins which can be used for motor drive or to measure the back EMF to calibrate the pointer reset position. These pins interface to the coils of motor 2.
1.5.7
Power Supply Pins
NOTE All VSS pins must be connected together in the application (See Appendix B, "PCB Layout Guidelines"). Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. Bypass requirements depend on how heavily the MCU pins are loaded (Table B-1).
MC9S12HZ256 power and ground pins are described below.
1.5.7.1
VDDR -- External Power Pin
VDDR is the power supply pin for the internal voltage regulator.
1.5.7.2
VDDX1, VDDX2, VSSX1, VSSX2 -- External Power and Ground Pins
VDDX1, VDDX2, VSSX1 and VSSX2 are the power supply and ground pins for input/output drivers.VDDX1 and VDDX2 as well as VSSX1 and VSSX2 are not internally connected.
1.5.7.3
VDD1, VSS1, VSS2 -- Internal Logic Power Pins
VDD1, VSS1 and VSS2 are the internal logic power and ground pins and related to the voltage regulator output. These pins serve as connection points for filter capacitors. VSS1 and VSS2 are internally connected. NOTE No load allowed except for bypass capacitors.
1.5.7.4
VDDA, VSSA -- Power Supply Pins for ATD and VREG
VDDA, VSSA are the power supply and ground pins for the voltage regulator and the analog-to-digital converter.
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1.5.7.5
VDDM1, VDDM2, VDDM3 -- Power Supply Pins for Motor 0 to 3
VDDM1, VDDM2 and VDDM3 are the supply pins for the ports U and V. VDDM1, VDDM2 and VDDM3 are internally connected.
1.5.7.6
VSSM1, VSSM2, VSSM3 -- Ground Pins for Motor 0 to 3
VSSM1, VSSM2 and VSSM3 are the ground pins for the ports U and V. VSSM1, VSSM2 and VSSM3 are internally connected.
1.5.7.7
VLCD -- Power Supply Reference Pin for LCD driver
VLCD is the voltage reference pin for the LCD driver. Adjusting the voltage on this pin will change the display contrast.
1.5.7.8
VRH, VRL -- ATD Reference Voltage Input Pins
VRH and VRL are the voltage reference pins for the analog-to-digital converter.
1.5.7.9
VDDPLL, VSSPLL -- Power Supply Pins for PLL
VDDPLL and VSSPLL are the PLL supply pins and serve as connection points for external loop filter components. NOTE No load allowed except for bypass capacitors.
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1.6
System Clock Description
The clock and reset generator (CRG) provides the internal clock signals for the core and all peripheral modules. Figure 1-12 shows the clock connections from the CRG to all modules. Consult the CRG block description chapter for details on clock generation.
HCS12 CORE
BDM MEBI CPU MMC DBG
core clock
INT
Flash RAM EEPROM EXTAL TIM ATD CRG bus clock oscillator clock XTAL PWM SCI0, SCI1 SPI CAN0, CAN1 IIC MC LCD PIM SSD1, SSD2, SSD3, SSD4
Figure 1-12. Clock Connections
MC9S12HZ256 Data Sheet, Rev. 2.05 46 Freescale Semiconductor
Chapter 1 MC9S12HZ256 Device Overview
1.7
Modes of Operation
Eight possible modes determine the operating configuration of the MC9S12HZ256. Each mode has an associated default memory map and external bus configuration. Three low power modes exist for the device. The operating mode out of reset is determined by the states of the MODC, MODB, and MODA pins during reset (Table 1-10). The MODC, MODB, and MODA bits in the MODE register show the current operating mode and provide limited mode switching during operation. The states of the MODC, MODB, and MODA pins are latched into these bits on the rising edge of the reset signal.
Table 1-10. Mode Selection
MODC 0 0 X 0 1 1 1 MODB 0 0 1 1 0 0 1 MODA 0 1 0 1 0 1 1 Mode Description Special Single Chip, BDM allowed and ACTIVE. BDM is allowed in all other modes but a serial command is required to make BDM active. Emulation Expanded Narrow, BDM allowed Reserved for factory test Emulation Expanded Wide, BDM allowed Normal Single Chip, BDM allowed Normal Expanded Narrow, BDM allowed Normal Expanded Wide, BDM allowed
There are two basic types of operating modes: 1. Normal modes: Some registers and bits are protected against accidental changes. 2. Special modes: Allow greater access to protected control registers and bits for special purposes such as testing. A system development and debug feature, background debug mode (BDM), is available in all modes. In special single-chip mode, BDM is active immediately after reset. Some aspects of port E are not mode dependent. Bit 1 of port E is a general-purpose input or the IRQ interrupt input. IRQ can be enabled by bits in the CPU's condition codes register but it is inhibited at reset so this pin is initially configured as a simple input with a pull-up. Bit 0 of port E is a general-purpose input or the XIRQ interrupt input. XIRQ can be enabled by bits in the CPU's condition codes register but it is inhibited at reset so this pin is initially configured as a simple input with a pull-up. The ESTR bit in the EBICTL register is set to one by reset in any user mode. This assures that the reset vector can be fetched even if it is located in an external slow memory device. The PE6/MODB/IPIPE1 and PE5/MODA/IPIPE0 pins act as pull-down select inputs during reset and high-impedance select inputs after reset. The following paragraphs discuss the default bus setup and describe which aspects of the bus can be changed after reset on a per mode basis.
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1.7.1
Normal Operating Modes
These modes provide three operating configurations. Background debug is available in all three modes, but must first be enabled for some operations by means of a BDM background command, then activated.
1.7.1.1
Normal Single-Chip Mode
There is no external expansion bus in this mode. All pins of ports A, B, E and K are general-purpose I/O pins initially configured with internal pull-downs enabled, except port E bits 1 and 0 which are available as general-purpose input only pins with internal pull-ups enabled. The pins associated with port E bits 6, 5, 3, and 2 cannot be configured for their alternate functions IPIPE1, IPIPE0, LSTRB, and R/W while the MCU is in single chip modes. In single chip modes, the associated control bits PIPOE, LSTRE, and RDWE are reset to zero. Writing the opposite state into them in single chip mode does not change the operation of the associated port E pins. In normal single chip mode, the MODE register is writable one time. This allows a user program to change the bus mode to narrow or wide expanded mode and/or turn on visibility of internal accesses. Port E, bit 4 can be configured for a free-running E clock output by clearing NECLK=0. Typically the only use for an E clock output while the MCU is in single chip modes would be to get a constant speed clock for use in the external application system.
1.7.1.2
Normal Expanded Wide Mode
All pins of ports A, B, E and K are general-purpose I/O pins initially configured with internal pull-downs enabled, except port E bits 1 and 0 which are available as general-purpose input only pins with internal pull-ups enabled. In expanded wide modes, ports A and B are configured as a 16-bit multiplexed address and data bus and port E bit 4 is configured as the E clock output signal. These signals allow external memory and peripheral devices to be interfaced to the MCU. Port E pins other than PE4/ECLK are configured as general-purpose I/O pins. Control bits PIPOE, NECLK, LSTRE, and RDWE in the PEAR register can be used to configure port E pins to act as bus control outputs instead of general-purpose I/O pins. It is possible to enable the pipe status signals on port E bits 6 and 5 by setting the PIPOE bit in PEAR, but it would be unusual to do so in this mode. Development systems where pipe status signals are monitored would typically use the special variation of this mode. The port E bit 2 pin can be reconfigured as the R/W bus control signal by writing "1" to the RDWE bit in PEAR. If the expanded system includes external devices that can be written, such as RAM, the RDWE bit would need to be set before any attempt to write to an external location. If there are no writable resources in the external system, PE2 can remain a general-purpose I/O pin. The port E bit 3 pin can be reconfigured as the LSTRB bus control signal by writing "1" to the LSTRE bit in PEAR. The default condition of this pin is a general-purpose input because the LSTRB function is not needed in all expanded wide applications.
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The port E bit 4 pin is initially configured as ECLK output with stretch. The E clock output function depends upon the settings of the NECLK bit in the PEAR register, the IVIS bit in the MODE register and the ESTR bit in the EBICTL register. The E clock is available for use in external select decode logic or as a constant speed clock for use in the external application system.
1.7.1.3
Normal Expanded Narrow Mode
This mode is used for lower cost production systems that use 8-bit wide external EPROMs or RAMs. Such systems take extra bus cycles to access 16-bit locations but this may be preferred over the extra cost of additional external memory devices. Ports A and B are configured as a 16-bit address bus and port A is multiplexed with data. Internal visibility is not available in this mode because the internal cycles would need to be split into two 8-bit cycles. Because the PEAR register can only be written one time in this mode, use care to set all bits to the desired states during the single allowed write. The PE3/LSTRB pin is always a general-purpose I/O pin in normal expanded narrow mode. Although it is possible to write the LSTRE bit in PEAR to "1" in this mode, the state of LSTRE is overridden and port E bit 3 cannot be reconfigured as the LSTRB output. It is possible to enable the pipe status signals on port E bits 6 and 5 by setting the PIPOE bit in PEAR, but it would be unusual to do so in this mode. LSTRB would also be needed to fully understand system activity. Development systems where pipe status signals are monitored would typically use special expanded wide mode or occasionally special expanded narrow mode. The PE4/ECLK pin is initially configured as ECLK output with stretch. The E clock output function depends upon the settings of the NECLK bit in the PEAR register, the IVIS bit in the MODE register and the ESTR bit in the EBICTL register. In normal expanded narrow mode, the E clock is available for use in external select decode logic or as a constant speed clock for use in the external application system. The PE2/R/W pin is initially configured as a general-purpose input with a pull-up but this pin can be reconfigured as the R/W bus control signal by writing "1" to the RDWE bit in PEAR. If the expanded narrow system includes external devices that can be written such as RAM, the RDWE bit would need to be set before any attempt to write to an external location. If there are no writable resources in the external system, PE2 can remain a general-purpose I/O pin.
1.7.1.4
Internal Visibility
Internal visibility is available when the MCU is operating in expanded wide modes or special narrow mode. It is not available in single-chip, peripheral or normal expanded narrow modes. Internal visibility is enabled by setting the IVIS bit in the MODE register. If an internal access is made while E, R/W, and LSTRB are configured as bus control outputs and internal visibility is off (IVIS = 0), E will remain low for the cycle, R/W will remain high, and address, data and the LSTRB pins will remain at their previous state. When internal visibility is enabled (IVIS = 1), certain internal cycles will be blocked from going external. During cycles when the BDM is selected, R/W will remain high, data will maintain its previous state, and address and LSTRB pins will be updated with the internal value. During CPU no access cycles when the
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BDM is not driving, R/W will remain high, and address, data and the LSTRB pins will remain at their previous state.
1.7.1.5
Emulation Expanded Wide Mode
In expanded wide modes, ports A and B are configured as a 16-bit multiplexed address and data bus and port E provides bus control and status signals. These signals allow external memory and peripheral devices to be interfaced to the MCU. These signals can also be used by a logic analyzer to monitor the progress of application programs. The bus control related pins in port E (PE7/NOACC, PE6/MODB/IPIPE1, PE5/MODA/IPIPE0, PE4/ECLK, PE3/LSTRB/TAGLO, and PE2/R/W) are all configured to serve their bus control output functions rather than general-purpose I/O. Notice that writes to the bus control enable bits in the PEAR register in special mode are restricted.
1.7.1.6
Emulation Expanded Narrow Mode
Expanded narrow modes are intended to allow connection of single 8-bit external memory devices for lower cost systems that do not need the performance of a full 16-bit external data bus. Accesses to internal resources that have been mapped external (i.e., PORTA, PORTB, DDRA, DDRB, PORTE, DDRE, PEAR, PUCR, RDRIV) will be accessed with a 16-bit data bus on ports A and B. Accesses of 16-bit external words to addresses which are normally mapped external will be broken into two separate 8-bit accesses using port A as an 8-bit data bus. Internal operations continue to use full 16-bit data paths. They are only visible externally as 16-bit information if IVIS = 1. Ports A and B are configured as multiplexed address and data output ports. During external accesses, address A15, data D15 and D7 are associated with PA7, address A0 is associated with PB0 and data D8 and D0 are associated with PA0. During internal visible accesses and accesses to internal resources that have been mapped external, address A15 and data D15 is associated with PA7 and address A0 and data D0 is associated with PB0. The bus control related pins in port E (PE7/NOACC, PE6/MODB/IPIPE1, PE5/MODA/IPIPE0, PE4/ECLK, PE3/LSTRB/TAGLO, and PE2/R/W) are all configured to serve their bus control output functions rather than general-purpose I/O. Notice that writes to the bus control enable bits in the PEAR register in special mode are restricted.
1.7.2
1.7.2.1
Special Operating Modes
Special Single-Chip Mode
When the MCU is reset in this mode, the background debug mode is enabled and active. The MCU does not fetch the reset vector and execute application code as it would in other modes. Instead the active background mode is in control of CPU execution and BDM firmware is waiting for additional serial commands through the BKGD pin. When a serial command instructs the MCU to return to normal execution, the system will be configured as described below unless the reset states of internal control registers have been changed through background commands after the MCU was reset. There is no external expansion bus after reset in this mode. Ports A and B are initially simple bidirectional I/O pins that are configured as high-impedance inputs with internal pull-downs enabled; however, writing
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to the mode select bits in the MODE register (which is allowed in special modes) can change this after reset. All of the port E pins (except PE4/ECLK) are initially configured as general-purpose high-impedance inputs with pull-downs enabled. PE4/ECLK is configured as the E clock output in this mode. The pins associated with port E bits 6, 5, 3, and 2 cannot be configured for their alternate functions IPIPE1, IPIPE0, LSTRB, and R/W while the MCU is in single chip modes. In single chip modes, the associated control bits PIPOE, LSTRE and RDWE are reset to zero. Writing the opposite value into these bits in single chip mode does not change the operation of the associated port E pins. Port E, bit 4 can be configured for a free-running E clock output by clearing NECLK = 0. Typically the only use for an E clock output while the MCU is in single chip modes would be to get a constant speed clock for use in the external application system.
1.8
Security
The device will make available a security feature preventing the unauthorized read and write of the memory contents. This feature allows: * Protection of the contents of FLASH * Protection of the contents of EEPROM * Operation in single-chip mode * Operation from external memory with internal FLASH and EEPROM disabled The user must be reminded that part of the security must lie with the user's code. An extreme example would be user's code that dumps the contents of the internal program. This code would defeat the purpose of security. At the same time the user may also wish to put a back door in the user's program. An example of this is the user downloads a key through the SCI which allows access to a programming routine that updates parameters stored in EEPROM.
1.8.1
Securing the Microcontroller
After the user has programmed the FLASH and EEPROM (if desired), the part can be secured by programming the security bits located in the FLASH module. These non-volatile bits will keep the part secured through resetting the part and through powering down the part. The security byte resides in a portion of the Flash array. Check the Flash block description chapter for more details on the security configuration.
1.8.2
1.8.2.1
Operation of the Secured Microcontroller
Normal Single Chip Mode
This will be the most common usage of the secured part. Everything will appear the same as if the part was not secured with the exception of BDM operation. The BDM operation will be blocked.
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1.8.2.2
Executing from External Memory
The user may wish to execute from external space with a secured microcontroller. This is accomplished by resetting directly into expanded mode. The internal FLASH and EEPROM will be disabled. BDM operations will be blocked.
1.8.3
Unsecuring the Microcontroller
In order to unsecure the microcontroller, the internal FLASH and EEPROM must be erased. This can be done through an external program in expanded mode. After the user has erased the FLASH and EEPROM, the part can be reset into special single chip mode. This invokes a program that verifies the erasure of the internal FLASH and EEPROM. After this program completes, the user can erase and program the FLASH security bits to the unsecured state. This is generally done through the BDM, but the user could also change to expanded mode (by writing the mode bits through the BDM) and jumping to an external program (again through BDM commands). Note that if the part goes through a reset before the security bits are reprogrammed to the unsecure state, the part will be secured again.
1.9
Low Power Modes
Consult the respective block description chapter for information on the module behavior in stop, pseudo stop, and wait mode.
1.10
Resets and Interrupts
Consult the Exception Processing section of the CPU12 Reference Manual for information on resets and interrupts. Both local masking and CCR masking are included as listed in Table 1-11. System resets can be generated through external control of the RESET pin, through the clock and reset generator module CRG or through the low voltage reset (LVR) generator of the voltage regulator module. Refer to the CRG and VREG block description chapters for detailed information on reset generation.
1.10.1
Vectors
Table 1-11. Interrupt Vector Locations
Table 1-11 lists interrupt sources and vectors in default order of priority.
Vector Address 0xFFFE, 0xFFFF
Interrupt Source External Reset, Power On Reset or Low Voltage Reset (see CRG Flags Register to determine reset source) Clock Monitor fail reset COP failure reset Unimplemented instruction trap SWI XIRQ
CCR Mask None
Local Enable None
HPRIO Value to Elevate --
0xFFFC, 0xFFFD 0xFFFA, 0xFFFB 0xFFF8, 0xFFF9 0xFFF6, 0xFFF7 0xFFF4, 0xFFF5
None None None None X-Bit
COPCTL (CME, FCME) COP rate select None None None
-- -- -- -- --
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Chapter 1 MC9S12HZ256 Device Overview
Table 1-11. Interrupt Vector Locations (continued)
Vector Address 0xFFF2, 0xFFF3 0xFFF0, 0xFFF1 0xFFEE, 0xFFEF 0xFFEC, 0xFFED 0xFFEA, 0xFFEB 0xFFE8, 0xFFE9 0xFFE6, 0xFFE7 0xFFE4, 0xFFE5 0xFFE2, 0xFFE3 0xFFE0, 0xFFE1 0xFFDE, 0xFFDF 0xFFDC, 0xFFDD 0xFFDA, 0xFFDB 0xFFD8, 0xFFD9 0xFFD6, 0xFFD7 0xFFD4, 0xFFD5 0xFFD2, 0xFFD3 0xFFD0, 0xFFD1 0xFFCE, 0xFFCF 0xFFCC, 0xFFCD 0xFFCA, 0xFFCB 0xFFC8, 0xFFC9 0xFFC6, 0xFFC7 0xFFC4, 0xFFC5 0xFFC2, 0xFFC3 0xFFC0, 0xFFC1 0xFFBE, 0xFFBF 0xFFBC, 0xFFBD 0xFFBA, 0xFFBB 0xFFB8, 0xFFB9 0xFFB6, 0xFFB7 0xFFB4, 0xFFB5 0xFFB2, 0xFFB3 0xFFB0, 0xFFB1 0xFFAE, 0xFFAF 0xFFAC, 0xFFAD 0xFFAA, 0xFFAB Interrupt Source IRQ Real Time Interrupt Timer channel 0 Timer channel 1 Timer channel 2 Timer channel 3 Timer channel 4 Timer channel 5 Timer channel 6 Timer channel 7 Timer overflow Pulse accumulator A overflow Pulse accumulator input edge SPI SCI0 SCI1 ATD Reserved Reserved Reserved Reserved Port AD CRG PLL lock CRG Self Clock Mode Reserved IIC Bus Reserved Reserved EEPROM FLASH CAN0 wake-up CAN0 errors CAN0 receive CAN0 transmit CAN1 wake-up CAN1 errors CAN1 receive CCR Mask I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit Local Enable INTCR (IRQEN) RTICTL (RTIE) TIE (C0I) TIE (C1I) TIE (C2I) TIE (C3I) TIE (C4I) TIE (C5I) TIE (C6I) TIE (C7I) TSCR2 (TOI) PACTL (PAOVI) PACTL (PAI) SPCR1 (SPIE) SC0CR2 (TIE, TCIE, RIE, ILIE) SC1CR2 (TIE, TCIE, RIE, ILIE) ATDCTL2 (ASCIE) Reserved Reserved Reserved Reserved PTADIF (PTADIE) CRGINT (LOCKIE) CRGINT (SCMIE) Reserved IBCR (IBIE) Reserved Reserved EECTL (CCIE, CBEIE) FCTL (CCIE, CBEIE) CAN0RIER (WUPIE) CAN0RIER (CSCIE, OVRIE) CAN0RIER (RXFIE) CAN0TIER (TXEIE[2:0]) CAN1RIER (WUPIE) CAN1RIER (CSCIE, OVRIE) CAN1RIER (RXFIE) HPRIO Value to Elevate 0xF2 0xF0 0xEE 0xEC 0xEA 0xE8 0xE6 0xE4 0xE2 0xE0 0xDE 0xDC 0xDA 0xD8 0xD6 0xD4 0xD2 0xD0 0xCE 0xCC 0xCA 0xC8 0xC6 0xC4 0xC2 0xC0 0xBE 0xBC 0xBA 0xB8 0xB6 0xB4 0xB2 0xB0 0xAE 0xAC 0xAA
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 53
Chapter 1 MC9S12HZ256 Device Overview
Table 1-11. Interrupt Vector Locations (continued)
Vector Address 0xFFA8, 0xFFA9 0xFFA6, 0xFFA7 0xFFA4, 0xFFA5 0xFFA2, 0xFFA3 0xFFA0, 0xFFA1 0xFF9E, 0xFF9F 0xFF9C, 0xFF9D 0xFF9A, 0xFF9B 0xFF98, 0xFF99 0xFF96, 0xFF97 0xFF94, 0xFF95 0xFF92, 0xFF93 0xFF90, 0xFF91 0xFF8E, 0xFF8F 0xFF8C, 0xFF8D 0xFF8A, 0xFF8B 0xFF80-0xFF89 Interrupt Source CAN1 transmit Reserved Reserved Reserved SSD0 SSD1 SSD2 SSD3 Reserved Motor Control Timer Overflow Reserved Reserved Reserved Reserved PWM Emergency Shutdown VREG Low Voltage Interrupt Reserved CCR Mask I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit Local Enable CAN1TIER (TXEIE[2:0]) Reserved Reserved Reserved MDC0CTL (MCZIE, AOVIE) MDC1CTL (MCZIE, AOVIE) MDC2CTL (MCZIE, AOVIE) MDC3CTL (MCZIE, AOVIE) Reserved MCCTL1 (MCOCIE) Reserved Reserved Reserved Reserved PWMSDN(PWMIE) VREGCTRL (LVIE) Reserved HPRIO Value to Elevate 0xA8 0xA6 0xA4 0xA2 0xA0 0x9E 0x9C 0x9A 0x98 0x96 0x94 0x92 0x90 0x8E 0x8C 0x8A 0x80-0x88
MC9S12HZ256 Data Sheet, Rev. 2.05 54 Freescale Semiconductor
Chapter 1 MC9S12HZ256 Device Overview
1.10.2
Resets
Resets are a subset of the interrupts featured in Table 1-12. The different sources capable of generating a system reset are summarized in Table 1-12.
Table 1-12. Reset Summary
Reset Power-on Reset External Reset Low Voltage Reset Clock Monitor Reset COP Watchdog Reset Priority 1 1 1 2 3 Source CRG Module RESET pin VREG Module CRG Module CRG Module Vector 0xFFFE, 0xFFFF 0xFFFE, 0xFFFF 0xFFFE, 0xFFFF 0xFFFC, 0xFFFD 0xFFFA, 0xFFFB
1.10.3
Effects of Reset
When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the respective module block description chapters for register reset states. MC mode dependent pin configuration of port A, B and E out of reset. Refer to the PIM block description chapter for reset configurations of all peripheral module ports. Refer to Table 1-1 for locations of the memories depending on the operating mode after reset. The RAM array is not automatically initialized out of reset.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 55
Chapter 1 MC9S12HZ256 Device Overview
MC9S12HZ256 Data Sheet, Rev. 2.05 56 Freescale Semiconductor
Chapter 2 256 Kbyte Flash Module (FTS256K2V1)
2.1 Introduction
This document describes the FTS256K2 module that includes a 256 Kbyte Flash (nonvolatile) memory. The Flash memory may be read as either bytes, aligned words, or misaligned words. Read access time is one bus cycle for bytes and aligned words, and two bus cycles for misaligned words. The Flash memory is ideal for program and data storage for single-supply applications allowing for field reprogramming without requiring external voltage sources for program or erase. Program and erase functions are controlled by a command driven interface. The Flash module supports both block erase and sector erase. An erased bit reads 1 and a programmed bit reads 0. The high voltage required to program and erase the Flash memory is generated internally. It is not possible to read from a Flash block while it is being erased or programmed. CAUTION A Flash word must be in the erased state before being programmed. Cumulative programming of bits within a Flash word is not allowed.
2.1.1
Glossary
Banked Register -- A memory-mapped register operating on one Flash block which shares the same register address as the equivalent registers for the other Flash blocks. The active register bank is selected by the BKSEL bit in the FCNFG register. Command Write Sequence -- A three-step MCU instruction sequence to execute built-in algorithms (including program and erase) on the Flash memory. Common Register -- A memory-mapped register which operates on all Flash blocks.
2.1.2
* * * * * * *
Features
256 Kbytes of Flash memory comprised of two 128 Kbyte blocks with each block divided into 128 sectors of 1024 bytes Automated program and erase algorithm Interrupts on Flash command completion, command buffer empty Fast sector erase and word program operation 2-stage command pipeline for faster multi-word program times Sector erase abort feature for critical interrupt response Flexible protection scheme to prevent accidental program or erase
MC9S12HZ256 Data Sheet, Rev. 2.05
Freescale Semiconductor
57
Chapter 2 256 Kbyte Flash Module (FTS256K2V1)
* * *
Single power supply for all Flash operations including program and erase Security feature to prevent unauthorized access to the Flash memory Code integrity check using built-in data compression
2.1.3
Modes of Operation
Program, erase, erase verify, and data compress operations (please refer to Section 2.4.1 for details).
2.1.4
Block Diagram
A block diagram of the Flash module is shown in Figure 2-1.
MC9S12HZ256 Data Sheet, Rev. 2.05 58 Freescale Semiconductor
Chapter 2 256 Kbyte Flash Module (FTS256K2V1)
FTS256K2
Command Interface
Common Registers Banked Registers Command Interrupt Request Command Pipelines Flash Block 0-1
comm2 addr2 data2 comm1 addr1 data1
Flash Block 0 64K * 16 Bits
sector 0 sector 1 sector 127
Flash Block 1 64K * 16 Bits
sector 0 sector 1 sector 127
Protection
Security
Oscillator Clock
Clock Divider FCLK
Figure 2-1. FTS256K2 Block Diagram
2.2
External Signal Description
The Flash module contains no signals that connect off-chip.
2.3
Memory Map and Register Definition
This subsection describes the memory map and registers for the Flash module.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 59
Chapter 2 256 Kbyte Flash Module (FTS256K2V1)
2.3.1
Module Memory Map
The Flash memory map is shown in Figure 2-2. The HCS12 architecture places the Flash memory addresses between 0x4000 and 0xFFFF which corresponds to three 16-Kbyte pages. The content of the HCS12 core PPAGE register is used to map the logical middle page ranging from address 0x8000 to 0xBFFF to any physical 16 Kbyte page in the Flash memory. By placing 0x3E or 0x3F in the HCS12 Core PPAGE register, the associated 16 Kbyte pages appear twice in the MCU memory map. The FPROT register, described in Section 2.3.2.5, "Flash Protection Register (FPROT)", can be set to globally protect a Flash block. However, three separate memory regions, one growing upward from the first address in the next-to-last page in the Flash block (called the lower region), one growing downward from the last address in the last page in the Flash block (called the higher region), and the remaining addresses in the Flash block, can be activated for protection. The Flash locations of these protectable regions are shown in Table 2-2. The higher address region of Flash block 0 is mainly targeted to hold the boot loader code because it covers the vector space. The lower address region of any Flash block can be used for EEPROM emulation in an MCU without an EEPROM module because it can remain unprotected while the remaining addresses are protected from program or erase. Security information that allows the MCU to restrict access to the Flash module is stored in the Flash configuration field found in Flash block 0, described in Table 2-1.
Table 2-1. Flash Configuration Field
Unpaged Flash Address 0xFF00 - 0xFF07 Paged Flash Address (PPAGE 0x3F) 0xBF00 - 0xBF07 Size (Bytes) 8
Description
Backdoor Comparison Key Refer to Section 2.6.1, "Unsecuring the MCU using Backdoor Key Access" Reserved Block 1 Flash Protection Byte Refer to Section 2.3.2.7, "Flash Status Register (FSTAT)" Block 0 Flash Protection Byte Refer toSection 2.3.2.7, "Flash Status Register (FSTAT)" Flash Nonvolatile Byte Refer to Section 2.3.2.9, "Flash Control Register (FCTL)" Flash Security Byte Refer to Section 2.3.2.2, "Flash Security Register (FSEC)"
0xFF08 - 0xFF0B 0xFF0C 0xFF0D 0xFF0E 0xFF0F
0xBF08 - 0xBF0B 0xBF0C 0xBF0D 0xBF0E 0xBF0F
4 1 1 1 1
MC9S12HZ256 Data Sheet, Rev. 2.05 60 Freescale Semiconductor
Chapter 2 256 Kbyte Flash Module (FTS256K2V1)
(16 bytes) MODULE BASE + 0x0000 Flash Registers MODULE BASE + 0x000F FLASH_START = 0x4000 0x4400 0x4800 0x5000 Flash Protected Low Sectors 1, 2, 4, 8 Kbytes
0x6000
0x3E
0x8000
Flash Blocks
16K PAGED MEMORY
0x38
0x39
0x3A
0x3B 0x3C
0x3D
0x3E
0x3F
Block 0
0xC000 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37
Block 1
0xE000
0x3F
Flash Protected High Sectors 2, 4, 8, 16 Kbytes
0xF000 0xF800 FLASH_END = 0xFFFF
0xFF00 - 0xFF0F, Flash Configuration Field
Note: 0x30-0x3F correspond to the PPAGE register content
Figure 2-2. Flash Memory Map
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 61
Chapter 2 256 Kbyte Flash Module (FTS256K2V1)
Table 2-2. Detailed Flash Memory Map
MCU Address Range 0x4000-0x7FFF PPAGE Unpaged (0x3E) Protectable Lower Range 0x4000-0x43FF 0x4000-0x47FF 0x4000-0x4FFF 0x4000-0x5FFF 0x8000-0xBFFF 0x30 0x31 0x32 0x33 0x34 0x35 0x36 N.A. N.A. N.A. N.A. N.A. N.A. 0x8000-0x83FF 0x8000-0x87FF 0x8000-0x8FFF 0x8000-0x9FFF 0x37 N.A. 0xB800-0xBFFF 0xB000-0xBFFF 0xA000-0xBFFF 0x8000-0xBFFF 0x8000-0xBFFF 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E N.A. N.A. N.A. N.A. N.A. N.A. 0x8000-0x83FF 0x8000-0x87FF 0x8000-0x8FFF 0x8000-0x9FFF 0x3F N.A. 0xB800-0xBFFF 0xB000-0xBFFF 0xA000-0xBFFF 0x8000-0xBFFF 0xC000-0xFFFF Unpaged (0x3F) N.A. 0xF800-0xFFFF 0xF000-0xFFFF 0xE000-0xFFFF 0xC000-0xFFFF
1
Protectable Higher Range N.A.
Flash Block 0
Block Relative Address1 0x018000-0x01BFFF
N.A. N.A. N.A. N.A. N.A. N.A. N.A.
1
0x000000-0x003FFF 0x004000-0x007FFF 0x008000-0x00BFFF 0x00C000-0x00FFFF 0x010000-0x013FFF 0x014000-0x017FFF 0x018000-0x01BFFF
0x01C000-0x01FFFF
N.A. N.A. N.A. N.A. N.A. N.A. N.A.
0
0x000000-0x003FFF 0x004000-0x007FFF 0x008000-0x00BFFF 0x00C000-0x00FFFF 0x010000-0x013FFF 0x014000-0x017FFF 0x018000-0x01BFFF
0x01C000-0x01FFFF
0
0x01C000-0x01FFFF
Block relative address for each 128 Kbyte Flash block consists of 17 address bits.
MC9S12HZ256 Data Sheet, Rev. 2.05 62 Freescale Semiconductor
Chapter 2 256 Kbyte Flash Module (FTS256K2V1)
The Flash module also contains a set of 16 control and status registers located in address space module base + 0x0000 to module base + 0x000F. In order to accommodate more than one Flash block with a minimum register address space, a set of registers located from module base + 0x0004 to module base + 0x000B are repeated in all banks. The active register bank is selected by the BKSEL bits in the unbanked Flash configuration register (FCNFG). A summary of these registers is given in Table 2-3 while their accessibility in normal and special modes is detailed in Section 2.3.2, "Register Descriptions".
Table 2-3. Flash Register Map
Module Base + 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C 0x000D 0x000E 0x000F
1
Register Name Flash Clock Divider Register (FCLKDIV) Flash Security Register (FSEC) Flash Test Mode Register (FTSTMOD)1
Normal Mode Access R/W R R R/W R/W R/W R/W R R R R R R R R R
Flash Configuration Register (FCNFG) Flash Protection Register (FPROT) Flash Status Register (FSTAT) Flash Command Register (FCMD) Flash Control Register (FCTL) Flash High Address Register (FADDRHI)1 Flash Low Address Register (FADDRLO)1 Flash High Data Register (FDATAHI) Flash Low Data Register (FDATALO) RESERVED11 RESERVED21 RESERVED31 RESERVED41
Intended for factory test purposes only.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 63
Chapter 2 256 Kbyte Flash Module (FTS256K2V1)
2.3.2
Register Descriptions
Bit 7 R W FDIVLD PRDIV8 FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0 6 5 4 3 2 1 Bit 0
Register Name FCLKDIV
FSEC
R W
KEYEN
RNV5
RNV4
RNV3
RNV2
SEC
FTSTMOD
R W
0
0
0 WRALL
0
0
0
0
FCNFG
R CBEIE W CCIE KEYACC
0
0
0
0 BKSEL
FPROT
R FPOPEN W
RNV6 FPHDIS FPHS FPLDIS FPLS
FSTAT
R CBEIF W
CCIF PVIOL ACCERR
0
BLANK
0
0
FCMD
R W
0 CMDB
FCTL
R W
NV7
NV6
NV5
NV4
NV3
NV2
NV1
NV0
FADDRHI
R W
FADDRHI
FADDRLO
R W
FADDRLO
FDATAHI
R W
FDATAHI
FDATALO
R W
FDATALO
RESERVED1
R W
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-3. FTS256K2 Register Summary
MC9S12HZ256 Data Sheet, Rev. 2.05 64 Freescale Semiconductor
Chapter 2 256 Kbyte Flash Module (FTS256K2V1)
Register Name RESERVED2 R W RESERVED3 R W RESERVED4 R W
Bit 7 0
6 0
5 0
4 0
3 0
2 0
1 0
Bit 0 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-3. FTS256K2 Register Summary (continued)
2.3.2.1
Flash Clock Divider Register (FCLKDIV)
The unbanked FCLKDIV register is used to control timed events in program and erase algorithms.
7 R W Reset 0 0 0 0 0 0 0 0 FDIVLD PRDIV8 FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0 6 5 4 3 2 1 0
= Unimplemented or Reserved
Figure 2-4. Flash Clock Divider Register (FCLKDIV)
All bits in the FCLKDIV register are readable, bits 6-0 are write once and bit 7 is not writable.
Table 2-4. FCLKDIV Field Descriptions
Field 7 FDIVLD 6 PRDIV8 5-0 FDIV[5:0] Description Clock Divider Loaded. 0 Register has not been written. 1 Register has been written to since the last reset. Enable Prescalar by 8. 0 The oscillator clock is directly fed into the clock divider. 1 The oscillator clock is divided by 8 before feeding into the clock divider. Clock Divider Bits -- The combination of PRDIV8 and FDIV[5:0] must divide the oscillator clock down to a frequency of 150 kHz-200 kHz. The maximum divide ratio is 512. Please refer to Section 2.4.1.1, "Writing the FCLKDIV Register" for more information.
2.3.2.2
Flash Security Register (FSEC)
The unbanked FSEC register holds all bits associated with the security of the MCU and Flash module.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 65
Chapter 2 256 Kbyte Flash Module (FTS256K2V1)
7 R W Reset F KEYEN
6
5 RNV5
4 RNV4
3 RNV3
2 RNV2
1 SEC
0
F
F
F
F
F
F
F
= Unimplemented or Reserved
Figure 2-5. Flash Security Register (FSEC)
All bits in the FSEC register are readable but are not writable. The FSEC register is loaded from the Flash Configuration Field at address $FF0F during the reset sequence, indicated by F in Figure 2-5.
Table 2-5. FSEC Field Descriptions
Field Description
1-0 Backdoor Key Security Enable Bits --The KEYEN[1:0] bits define the enabling of backdoor key access to the KEYEN[1:0] Flash module as shown in Table 2-6. 5-2 RNV[5:2] 1-0 SEC[1:0] Reserved Nonvolatile Bits -- The RNV[5:2] bits must remain in the erased 1 state for future enhancements. Flash Security Bits -- The SEC[1:0] bits define the security state of the MCU as shown in Table 2-7. If the Flash module is unsecured using backdoor key access, the SEC bits are forced to 10.
Table 2-6. Flash KEYEN States
KEYEN[1:0] 00 011 10 11
1
Status of Backdoor Key Access DISABLED DISABLED ENABLED DISABLED
Preferred KEYEN state to disable Backdoor Key Access.
Table 2-7. Flash Security States
SEC[1:0] 00 01
1
Status of Security SECURED SECURED UNSECURED SECURED
10 11
1
Preferred SEC state to set MCU to secured state.
The security function in the Flash module is described in Section 2.6, "Flash Module Security".
MC9S12HZ256 Data Sheet, Rev. 2.05 66 Freescale Semiconductor
Chapter 2 256 Kbyte Flash Module (FTS256K2V1)
2.3.2.3
Flash Test Mode Register (FTSTMOD)
The unbanked FTSTMOD register is used to control Flash test features.
7 R W Reset 0 0 0 0 0 0 0 0 0 6 0 5 0 WRALL 4 3 0 2 0 1 0 0 0
= Unimplemented or Reserved
Figure 2-6. Flash Test Mode Register (FTSTMOD)
All bits read 0 and are not writable in normal mode. The WRALL bit is writable only in special mode to simplify mass erase and erase verify operations. When writing to the FTSTMOD register in special mode, all unimplemented/reserved bits must be written to 0.
Table 2-8. FTSTMOD Field Descriptions
Field 4 WRALL Description Write to All Register Banks -- If the WRALL bit is set, all banked registers sharing the same register address will be written simultaneously during a register write. 0 Write only to the bank selected via BKSEL. 1 Write to all register banks.
2.3.2.4
Flash Configuration Register (FCNFG)
The unbanked FCNFG register enables the Flash interrupts and gates the security backdoor writes.
7 R CBEIE W Reset 0 0 0 0 0 0 0 0 CCIE KEYACC 6 5 4 0 3 0 2 0 1 0 BKSEL 0
= Unimplemented or Reserved
Figure 2-7. Flash Configuration Register (FCNFG)
CBEIE, CCIE, KEYACC and BKSEL bits are readable and writable while all remaining bits read 0 and are not writable. KEYACC is only writable if KEYEN (see Section 2.3.2.2) is set to the enabled state.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 67
Chapter 2 256 Kbyte Flash Module (FTS256K2V1)
Table 2-9. FCNFG Field Descriptions
Field 7 CBEIE Description Command Buffer Empty Interrupt Enable -- The CBEIE bit enables an interrupt in case of an empty command buffer in the Flash module. 0 Command buffer empty interrupt disabled. 1 An interrupt will be requested whenever the CBEIF flag (see Section 2.3.2.7, "Flash Status Register (FSTAT)") is set. Command Complete Interrupt Enable -- The CCIE bit enables an interrupt in case all commands have been completed in the Flash module. 0 Command complete interrupt disabled. 1 An interrupt will be requested whenever the CCIF flag (see Section 2.3.2.7, "Flash Status Register (FSTAT)") is set. Enable Security Key Writing 0 Flash writes are interpreted as the start of a command write sequence. 1 Writes to Flash array are interpreted as keys to open the backdoor. Reads of the Flash array return invalid data. Block Select -- The BKSEL bit indicates which register bank is active. 0 Select register bank associated with Flash block 0. 1 Select register bank associated with Flash block 1.
6 CCIE
5 KEYACC
0 BKSEL
2.3.2.5
Flash Protection Register (FPROT)
The banked FPROT register defines which Flash sectors are protected against program or erase operations.
7 R FPOPEN W Reset F F F F F F F F 6 RNV6 FPHDIS FPHS FPLDIS FPLS 5 4 3 2 1 0
= Unimplemented or Reserved
Figure 2-8. Flash Protection Register (FPROT)
All bits in the FPROT register are readable and writable with restrictions except for RNV[6] which is only readable (see Section 2.3.2.6, "Flash Protection Restrictions"). During reset, the banked FPROT registers are loaded from the Flash Configuration Field at the address shown in Table 2-10. To change the Flash protection that will be loaded during the reset sequence, the upper sector of the Flash memory must be unprotected, then the Flash Protect/Security byte located as described in Table 2-1 must be reprogrammed.
Table 2-10. Reset Loading of FPROT
Flash Address 0xFF0D 0xFF0C Protection Byte for Flash Block 0 Flash Block 1
MC9S12HZ256 Data Sheet, Rev. 2.05 68 Freescale Semiconductor
Chapter 2 256 Kbyte Flash Module (FTS256K2V1)
Trying to alter data in any of the protected areas in the Flash block will result in a protection violation error and the PVIOL flag will be set in the FSTAT register. A mass erase of the Flash block is not possible if any of the contained Flash sectors are protected.
Table 2-11. FPROT Field Descriptions
Field 7 FPOPEN Description Protection Function Bit -- The FPOPEN bit determines the protection function for program or erase as shown in Table 2-12. 0 FPHDIS and FPLDIS bits define unprotected address ranges as specified by the corresponding FPHS[1:0] and FPLS[1:0] bits. For an MCU without an EEPROM module, the FPOPEN clear state allows the main part of the Flash block to be protected while a small address range can remain unprotected for EEPROM emulation. 1 FPHDIS and FPLDIS bits enable protection for the address range specified by the corresponding FPHS[1:0] and FPLS[1:0] bits. Reserved Nonvolatile Bit -- The RNV[6] bit must remain in the erased state 1 for future enhancements. Flash Protection Higher Address Range Disable -- The FPHDIS bit determines whether there is a protected/unprotected area in the higher address space of the Flash block. 0 Protection/Unprotection enabled 1 Protection/Unprotection disabled Flash Protection Higher Address Size -- The FPHS[1:0] bits determine the size of the protected/unprotected area as shown in Table 2-13. The FPHS[1:0] bits can only be written to while the FPHDIS bit is set. Flash Protection Lower address range Disable -- The FPLDIS bit determines whether there is a protected/unprotected area in the lower address space of the Flash block. 0 Protection/Unprotection enabled 1 Protection/Unprotection disabled Flash Protection Lower Address Size -- The FPLS[1:0] bits determine the size of the protected/unprotected area as shown in Table 2-14. The FPLS[1:0] bits can only be written to while the FPLDIS bit is set.
6 RNV[6] 5 FPHDIS
4:3 FPHS[1:0] 2 FPLDIS
1:0 FPLS[1:0]
Table 2-12. Flash Protection Function
FPOPEN 1 1 1 1 0 0 0 0
1
FPHDIS 1 1 0 0 1 1 0 0
FPLDIS 1 0 1 0 1 0 1 0 No Protection
Function1
Protected Low Range Protected High Range Protected High and Low Ranges Full Block Protected Unprotected Low Range Unprotected High Range Unprotected High and Low Ranges
For range sizes, refer to Table 2-13 and Table 2-14.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 69
Chapter 2 256 Kbyte Flash Module (FTS256K2V1)
Table 2-13. Flash Protection Higher Address Range
FPHS[1:0] 00 01 10 11 Unpaged Address Range 0xF800-0xFFFF 0xF000-0xFFFF 0xE000-0xFFFF 0xC000-0xFFFF Paged Address Range 0x0037/0x003F: 0xC800-0xCFFF 0x0037/0x003F: 0xC000-0xCFFF 0x0037/0x003F: 0xB000-0xCFFF 0x0037/0x003F: 0x8000-0xCFFF Protected Size 2 Kbytes 4 Kbytes 8 Kbytes 16 Kbytes
Table 2-14. Flash Protection Lower Address Range
FPLS[1:0] 00 01 10 11 Unpaged Address Range 0x4000-0x43FF 0x4000-0x47FF 0x4000-0x4FFF 0x4000-0x5FFF Paged Address Range 0x0036/0x003E: 0x8000-0x83FF 0x0036/0x003E: 0x8000-0x87FF 0x0036/0x003E: 0x8000-0x8FFF 0x0036/0x003E: 0x8000-0x9FFF Protected Size 1 Kbyte 2 Kbytes 4 Kbytes 8 Kbytes
All possible Flash protection scenarios are illustrated in Figure 2-9. Although the protection scheme is loaded from the Flash array after reset, it can be changed by the user. This protection scheme can be used by applications requiring re-programming in single-chip mode while providing as much protection as possible if re-programming is not required.
MC9S12HZ256 Data Sheet, Rev. 2.05 70 Freescale Semiconductor
Chapter 2 256 Kbyte Flash Module (FTS256K2V1)
FPHDIS = 1 FPLDIS = 1 Scenario 7
FPHDIS = 1 FPLDIS = 0 6
FPHDIS = 0 FPLDIS = 1 5
FPHDIS = 0 FPLDIS = 0 4
PPAGE 0x0030-0x0035 0x0038-0x003D
PPAGE 0x0036-0x0037 0x003E-0x003F
Scenario
3
2
1
0
PPAGE 0x0030-0x0035 0x0038-0x003D
FPHS[1:0] FPHS[1:0] FPLS[1:0] FPOPEN = 0
71
PPAGE 0x0036-0x0037 0x003E-0x003F
Unprotected region Protected region not defined by FPLS, FPHS
Protected region with size defined by FPLS Protected region with size defined by FPHS
Figure 2-9. Flash Protection Scenarios
2.3.2.6
Flash Protection Restrictions
The general guideline is that Flash protection can only be added and not removed. Table 2-15 specifies all valid transitions between Flash protection scenarios. Any attempt to write an invalid scenario to the FPROT register will be ignored and the FPROT register will remain unchanged. The contents of the
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor
FPLS[1:0]
FPOPEN = 1
Chapter 2 256 Kbyte Flash Module (FTS256K2V1)
FPROT register reflect the active protection scenario. See the FPHS and FPLS descriptions for additional restrictions.
Table 2-15. Flash Protection Scenario Transitions
From Protection Scenario 0 1 2 3 4 5 6 7
1
To Protection Scenario1 0 X 1 X X X 2 X 3 X X X X X X X X X X X X X X X X X X X X X X 4 5 6 7
Allowed transitions marked with X.
2.3.2.7
Flash Status Register (FSTAT)
The banked FSTAT register defines the operational status of the module.
7 R CBEIF W Reset 1 1 0 0 0 0 0 0 6 CCIF PVIOL ACCERR 5 4 3 0 2 BLANK 1 0 0 0
= Unimplemented or Reserved
Figure 2-10. Flash Status Register (FSTAT - Normal Mode)
7 R CBEIF W Reset 1 1 0 0 0 0 0 0 6 CCIF PVIOL ACCERR 5 4 3 0 2 BLANK FAIL 1 0 0
= Unimplemented or Reserved
Figure 2-11. Flash Status Register (FSTAT - Special Mode)
CBEIF, PVIOL, and ACCERR are readable and writable, CCIF and BLANK are readable and not writable, remaining bits read 0and are not writable in normal mode. FAIL is readable and writable in special mode. FAIL must be clear when starting a command write sequence.
MC9S12HZ256 Data Sheet, Rev. 2.05 72 Freescale Semiconductor
Chapter 2 256 Kbyte Flash Module (FTS256K2V1)
Table 2-16. FSTAT Field Descriptions
Field 7 CBEIF Description Command Buffer Empty Interrupt Flag -- The CBEIF flag indicates that the address, data and command buffers are empty so that a new command write sequence can be started. The CBEIF flag is cleared by writing a 1 to CBEIF. Writing a 0 to the CBEIF flag has no effect on CBEIF. Writing a 0 to CBEIF after writing an aligned word to the Flash address space but before CBEIF is cleared will abort a command write sequence and cause the ACCERR flag to be set. Writing a 0 to CBEIF outside of a command write sequence will not set the ACCERR flag. The CBEIF flag is used together with the CBEIE bit in the FCNFG register to generate an interrupt request (see Figure 2-29). 0 Buffers are full. 1 Buffers are ready to accept a new command. Command Complete Interrupt Flag -- The CCIF flag indicates that there are no more commands pending. The CCIF flag is cleared when CBEIF is clear and sets automatically upon completion of all active and pending commands. The CCIF flag does not set when an active commands completes and a pending command is fetched from the command buffer. Writing to the CCIF flag has no effect on CCIF. The CCIF flag is used together with the CCIE bit in the FCNFG register to generate an interrupt request (see Figure 2-29). 0 Command in progress. 1 All commands are completed. Protection Violation Flag -- The PVIOL flag indicates an attempt was made to program or erase an address in a protected area of the Flash block during a command write sequence. The PVIOL flag is cleared by writing a 1 to PVIOL. Writing a 0 to the PVIOL flag has no effect on PVIOL. While PVIOL is set, it is not possible to launch a command or start a command write sequence. 0 No failure. 1 A protection violation has occurred. Access Error Flag -- The ACCERR flag indicates an illegal access to the Flash array caused by either a violation of the command write sequence, issuing an illegal command (illegal combination of the CMDBx bits in the FCMD register), launching the sector erase abort command terminating a sector erase operation early or the execution of a CPU STOP instruction while a command is executing (CCIF = 0). The ACCERR flag is cleared by writing a 1 to ACCERR. Writing a 0 to the ACCERR flag has no effect on ACCERR. While ACCERR is set in any of the banked FTSAT registers, it is not possible to launch a command or start a command write sequence in any of the Flash blocks. If ACCERR is set by an erase verify operation or a data compress operation, any buffered command will not launch. 0 No access error detected. 1 Access error has occurred. Erase Verify Operation Status Flag -- When the CCIF flag is set after completion of an erase verify command, the BLANK flag indicates the result of the erase verify operation. The BLANK flag is cleared by the Flash module when CBEIF is cleared as part of a new valid command write sequence. Writing to the BLANK flag has no effect on BLANK. 0 Flash block verified as not erased. 1 Flash block verified as erased. Flag Indicating a Failed Flash Operation -- The FAIL flag will set if the erase verify operation fails (selected Flash block verified as not erased). The FAIL flag is cleared by writing a 1 to FAIL. Writing a 0 to the FAIL flag has no effect on FAIL. 0 Flash operation completed without error. 1 Flash operation failed.
6 CCIF
5 PVIOL
4 ACCERR
2 BLANK
1 FAIL
2.3.2.8
Flash Command Register (FCMD)
The banked FCMD register is the Flash command register.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 73
Chapter 2 256 Kbyte Flash Module (FTS256K2V1)
7 R W Reset 0 0
6
5
4
3 CMDB
2
1
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-12. Flash Command Register (FCMD - NVM User Mode)
All CMDB bits are readable and writable during a command write sequence while bit 7 reads 0 and is not writable.
Table 2-17. FCMD Field Descriptions
Field 6-0 CMDB[6:0] Description Flash Command -- Valid Flash commands are shown in Table 2-18. Writing any command other than those listed in Table 2-18 sets the ACCERR flag in the FSTAT register.
Table 2-18. Valid Flash Command List
CMDB[6:0] 0x05 0x06 0x20 0x40 0x41 0x47 NVM Command Erase Verify Data Compress Word Program Sector Erase Mass Erase Sector Erase Abort
2.3.2.9
Flash Control Register (FCTL)
The banked FCTL register is the Flash control register.
7 R W Reset F F F F F F F F = Unimplemented or Reserved NV7 6 NV6 5 NV5 4 NV4 3 NV3 2 NV2 1 NV1 0 NV0
Figure 2-13. Flash Control Register (FCTL)
All bits in the FCTL register are readable but are not writable. The FCTL register is loaded from the Flash Configuration Field byte at $FF0E during the reset sequence, indicated by F in Figure 2-13.
Table 2-19. FCTL Field Descriptions
Field 7-0 NV[7:0] Description Nonvolatile Bits -- The NV[7:0] bits are available as nonvolatile bits. Refer to the Device User Guide for proper use of the NV bits.
MC9S12HZ256 Data Sheet, Rev. 2.05 74 Freescale Semiconductor
Chapter 2 256 Kbyte Flash Module (FTS256K2V1)
2.3.2.10
Flash Address Registers (FADDR)
The banked FADDRHI and FADDRLO registers are the Flash address registers.
7 R W Reset 0 0 0 0 0 0 0 0 6 5 4 FADDRHI 3 2 1 0
= Unimplemented or Reserved
Figure 2-14. Flash Address High Register (FADDRHI)
7 R W Reset 0 0 0 0 0 0 0 0 6 5 4 FADDRLO 3 2 1 0
= Unimplemented or Reserved
Figure 2-15. Flash Address Low Register (FADDRLO)
All FADDRHI and FADDRLO bits are readable but are not writable. After an array write as part of a command write sequence, the FADDR registers will contain the mapped MCU address written.
2.3.2.11
Flash Data Registers (FDATA)
The banked FDATAHI and FDATALO registers are the Flash data registers.
7 R W Reset 0 0 0 0 0 0 0 0 6 5 4 FDATAHI 3 2 1 0
= Unimplemented or Reserved
Figure 2-16. Flash Data High Register (FDATAHI)
7 R W Reset 0 0 0 0 0 0 0 0 6 5 4 FDATALO 3 2 1 0
= Unimplemented or Reserved
Figure 2-17. Flash Data Low Register (FDATALO)
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 75
Chapter 2 256 Kbyte Flash Module (FTS256K2V1)
All FDATAHI and FDATALO bits are readable but are not writable. After an array write as part of a command write sequence, the FDATA registers will contain the data written. At the completion of a data compress operation, the resulting 16-bit signature is stored in the FDATA registers. The data compression signature is readable in the FDATA registers until a new command write sequence is started.
2.3.2.12
RESERVED1
This register is reserved for factory testing and is not accessible.
7 R W Reset 0 0 0 0 0 0 0 0 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
= Unimplemented or Reserved
Figure 2-18. RESERVED1
All bits read 0 and are not writable.
2.3.2.13
RESERVED2
This register is reserved for factory testing and is not accessible.
7 R W Reset 0 0 0 0 0 0 0 0 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
= Unimplemented or Reserved
Figure 2-19. RESERVED2
All bits read 0 and are not writable.
2.3.2.14
RESERVED3
This register is reserved for factory testing and is not accessible.
7 R W Reset 0 0 0 0 0 0 0 0 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
= Unimplemented or Reserved
Figure 2-20. RESERVED3
All bits read 0 and are not writable.
MC9S12HZ256 Data Sheet, Rev. 2.05 76 Freescale Semiconductor
Chapter 2 256 Kbyte Flash Module (FTS256K2V1)
2.3.2.15
RESERVED4
This register is reserved for factory testing and is not accessible.
7 R W Reset 0 0 0 0 0 0 0 0 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
= Unimplemented or Reserved
Figure 2-21. RESERVED4
All bits read 0 and are not writable.
2.4
2.4.1
Functional Description
Flash Command Operations
Write and read operations are both used for the program, erase, erase verify, and data compress algorithms described in this subsection. The program and erase algorithms are time controlled by a state machine whose timebase, FCLK, is derived from the oscillator clock via a programmable divider. The command register as well as the associated address and data registers operate as a buffer and a register (2-stage FIFO) so that a second command along with the necessary data and address can be stored to the buffer while the first command remains in progress. This pipelined operation allows a time optimization when programming more than one word on a specific row in the Flash block as the high voltage generation can be kept active in between two programming commands. The pipelined operation also allows a simplification of command launching. Buffer empty as well as command completion are signalled by flags in the Flash status register with interrupts generated, if enabled. The next paragraphs describe: 1. How to write the FCLKDIV register. 2. Command write sequences used to program, erase, and verify the Flash memory. 3. Valid Flash commands. 4. Effects resulting from illegal Flash command write sequences or aborting Flash operations.
2.4.1.1
Writing the FCLKDIV Register
Prior to issuing any program, erase, erase verify, or data compress command, it is first necessary to write the FCLKDIV register to divide the oscillator clock down to within the 150 kHz to 200 kHz range. Because the program and erase timings are also a function of the bus clock, the FCLKDIV determination must take this information into account. If we define: * FCLK as the clock of the Flash timing control block, * Tbus as the period of the bus clock, and
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 77
Chapter 2 256 Kbyte Flash Module (FTS256K2V1)
*
INT(x) as taking the integer part of x (e.g. INT(4.323)=4).
Then, FCLKDIV register bits PRDIV8 and FDIV[5:0] are to be set as described in Figure 2-22. For example, if the oscillator clock frequency is 950 kHz and the bus clock frequency is 10 MHz, FCLKDIV bits FDIV[5:0] must be set to 4 (000100) and bit PRDIV8 set to 0. The resulting FCLK frequency is then 190 kHz. As a result, the Flash program and erase algorithm timings are increased over the optimum target by: ( 200 - 190 ) 200 x 100 = 5% CAUTION Program and erase command execution time will increase proportionally with the period of FCLK. Because of the impact of clock synchronization on the accuracy of the functional timings, programming or erasing the Flash memory cannot be performed if the bus clock runs at less than 1 MHz. Programming or erasing the Flash memory with FCLK < 150 kHz must be avoided. Setting FCLKDIV to a value such that FCLK < 150 kHz can destroy the Flash memory due to overstress. Setting FCLKDIV to a value such that (1/FCLK + Tbus) < 5s can result in incomplete programming or erasure of the Flash memory cells. If the FCLKDIV register is written, the FDIVLD bit is set automatically. If the FDIVLD bit is 0, the FCLKDIV register has not been written since the last reset. Flash commands will not be executed if the FCLKDIV register has not been written to.
MC9S12HZ256 Data Sheet, Rev. 2.05 78 Freescale Semiconductor
Chapter 2 256 Kbyte Flash Module (FTS256K2V1)
START
Tbus < 1s? YES PRDIV8=0 (reset)
NO
ALL COMMANDS IMPOSSIBLE
OSCILLATOR CLOCK > 12.8 MHZ? YES PRDIV8=1 PRDCLK=oscillator_clock/8
NO
PRDCLK=oscillator_clock
PRDCLK[MHz]*(5+Tbus[s]) an integer? YES
NO
FDIV[5:0]=INT(PRDCLK[MHz]*(5+Tbus[s]))
FDIV[5:0]=PRDCLK[MHz]*(5+Tbus[s])-1
TRY TO DECREASE Tbus
FCLK=(PRDCLK)/(1+FDIV[5:0])
1/FCLK[MHz] + Tbus[s] > 5 AND FCLK > 0.15 MHz ? NO
YES END
YES
FDIV[5:0] > 4?
NO ALL COMMANDS IMPOSSIBLE
Figure 2-22. Determination Procedure for PRDIV8 and FDIV Bits
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 79
Chapter 2 256 Kbyte Flash Module (FTS256K2V1)
2.4.1.2
Command Write Sequence
The Flash command controller is used to supervise the command write sequence to execute program, erase, erase verify, and data compress algorithms. Before starting a command write sequence, the ACCERR and PVIOL flags in the FSTAT register must be clear (see Section 2.3.2.7, "Flash Status Register (FSTAT)") and the CBEIF flag must be tested to determine the state of the address, data, and command buffers. If the CBEIF flag is set, indicating the buffers are empty, a new command write sequence can be started. If the CBEIF flag is clear, indicating the buffers are not available, a new command write sequence will overwrite the contents of the address, data, and command buffers. A command write sequence consists of three steps which must be strictly adhered to with writes to the Flash module not permitted between the steps. However, Flash register and array reads are allowed during a command write sequence. A command write sequence consists of the following steps: 1. Write an aligned data word to a valid Flash array address. The address and data will be stored in the address and data buffers, respectively. If the CBEIF flag is clear when the Flash array write occurs, the contents of the address and data buffers will be overwritten and the CBEIF flag will be set. 2. Write a valid command to the FCMD register. a) For the erase verify command (see Section 2.4.1.3.1, "Erase Verify Command"), the contents of the data buffer are ignored and all address bits in the address buffer are ignored. b) For the data compress command (see Section 2.4.1.3.2, "Data Compress Command"), the contents of the data buffer represents the number of consecutive words to read for data compression and the contents of the address buffer represents the starting address. c) For the program command (see Section 2.4.1.3.3, "Program Command"), the contents of the data buffer will be programmed to the address specified in the address buffer with all address bits valid. d) For the sector erase command (see Section 2.4.1.3.4, "Sector Erase Command"), the contents of the data buffer are ignored and address bits [9:0] contained in the address buffer are ignored. e) For the mass erase command (see Section 2.4.1.3.5, "Mass Erase Command"), the contents of the data buffer and address buffer are ignored. f) For the sector erase abort command (see Section 2.4.1.3.6, "Sector Erase Abort Command"), the contents of the data buffer and address buffer are ignored. 3. Clear the CBEIF flag by writing a 1 to CBEIF to launch the command. When the CBEIF flag is cleared, the CCIF flag is cleared on the same bus cycle by internal hardware indicating that the command was successfully launched. For all command write sequences except data compress and sector erase abort, the CBEIF flag will set four bus cycles after the CCIF flag is cleared indicating that the address, data, and command buffers are ready for a new command write sequence to begin. For data compress and sector erase abort operations, the CBEIF flag will remain clear until the operation completes. A command write sequence can be aborted prior to clearing the CBEIF flag by writing a 0 to the CBEIF flag and will result in the ACCERR flag being set.
MC9S12HZ256 Data Sheet, Rev. 2.05 80 Freescale Semiconductor
Chapter 2 256 Kbyte Flash Module (FTS256K2V1)
Except for the sector erase abort command, a buffered command will wait for the active operation to be completed before being launched. The sector erase abort command is launched when the CBEIF flag is cleared as part of a sector erase abort command write sequence. After a command is launched, the completion of the command operation is indicated by the setting of the CCIF flag. The CCIF flag only sets when all active and buffered commands have been completed.
2.4.1.3
Valid Flash Commands
Table 2-20 summarizes the valid Flash commands along with the effects of the commands on the Flash block.
Table 2-20. Valid Flash Command Description
FCMDB 0x05 0x06 0x20 0x40 0x41 NVM Command Erase Verify Function on Flash Memory Verify all memory bytes in the Flash block are erased. If the Flash block is erased, the BLANK flag in the FSTAT register will set upon command completion.
Data Compress data from a selected portion of the Flash block. The resulting signature is stored in Compress the FDATA register. Program Sector Erase Mass Erase Sector Erase Abort Program a word (two bytes) in the Flash block. Erase all memory bytes in a sector of the Flash block. Erase all memory bytes in the Flash block. A mass erase of the full Flash block is only possible when FPLDIS, FPHDIS, and FPOPEN bits in the FPROT register are set prior to launching the command. Abort the sector erase operation. The sector erase operation will terminate according to a set procedure. The Flash sector must not be considered erased if the ACCERR flag is set upon command completion.
0x47
CAUTION A Flash word must be in the erased state before being programmed. Cumulative programming of bits within a Flash word is not allowed.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 81
Chapter 2 256 Kbyte Flash Module (FTS256K2V1)
2.4.1.3.1
Erase Verify Command
The erase verify operation is used to confirm that a Flash block is erased. After launching the erase verify command, the CCIF flag in the FSTAT register will set after the operation has completed unless a second command has been buffered. The number of bus cycles required to execute the erase verify operation is equal to the number of addresses in the Flash block plus 12 bus cycles as measured from the time the CBEIF flag is cleared until the CCIF flag is set. The result of the erase verify operation is reflected in the state of the BLANK flag in the FSTAT register. If the BLANK flag is set in the FSTAT register, the Flash memory is erased.
Read: Register FCLKDIV Clock Register Loaded Check
Bit FDIVLD set? yes
no
Write: Register FCLKDIV
1.
Write: Flash Block Address and Dummy Data Write: Register FCMD Erase Verify Command 0x05 Write: Register FSTAT Clear bit CBEIF 0x80 Read: Register FSTAT Bit ACCERR Set? no NOTE: command write sequence aborted by writing 0x00 to FSTAT register. NOTE: command write sequence aborted by writing 0x00 to FSTAT register.
2.
3.
Access Error Check
yes
Write: Register FSTAT Clear bit ACCERR 0x10
Bit Polling for Command Completion Check
Bit CCIF Set? yes Bit BLANK Set? yes
no
Read: Register FSTAT
no
Flash Block Not Erased; Mass Erase Flash Block
EXIT
Figure 2-23. Example Erase Verify Command Flow
MC9S12HZ256 Data Sheet, Rev. 2.05 82 Freescale Semiconductor
Chapter 2 256 Kbyte Flash Module (FTS256K2V1)
2.4.1.3.2
Data Compress Command
The data compress command is used to check Flash code integrity by compressing data from a selected portion of the Flash block into a signature analyzer. The starting address for the data compress operation is defined by the address written during the command write sequence. The number of consecutive word addresses compressed is defined by the data written during the command write sequence. If the data value written is 0x0000, 64K addresses or 128 Kbytes will be compressed. After launching the data compress command, the CCIF flag in the FSTAT register will set after the data compress operation has completed. The number of bus cycles required to execute the data compress operation is equal to two times the number of addresses read plus 20 bus cycles as measured from the time the CBEIF flag is cleared until the CCIF flag is set. After the CCIF flag is set, the signature generated by the data compress operation is available in the FDATA register. The signature in the FDATA register can be compared to the expected signature to determine the integrity of the selected data stored in the Flash block. If the last address of the Flash block is reached during the data compress operation, data compression will continue with the starting address of the Flash block. NOTE Since the FDATA register (or data buffer) is written to as part of the data compress operation, a command write sequence is not allowed to be buffered behind a data compress command write sequence. The CBEIF flag will not set after launching the data compress command to indicate that a command must not be buffered behind it. If an attempt is made to start a new command write sequence with a data compress operation active, the ACCERR flag in the FSTAT register will be set. A new command write sequence must only be started after reading the signature stored in the FDATA register. In order to take corrective action, it is recommended that the data compress command be executed on a Flash sector or subset of a Flash sector. If the data compress operation on a Flash sector returns an invalid signature, the Flash sector must be erased using the sector erase command and then reprogrammed using the program command. The data compress command can be used to verify that a sector or sequential set of sectors are erased.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 83
Chapter 2 256 Kbyte Flash Module (FTS256K2V1)
Read: Register FCLKDIV Clock Register Loaded Check
Bit FDIVLD set? yes
no
Write: Register FCLKDIV
1.
Write: Flash address to start compression and number of word addresses to compress Write: Register FCMD Data Compress Command 0x06 Write: Register FSTAT Clear bit CBEIF 0x80 Read: Register FSTAT Bit ACCERR Set? no NOTE: command write sequence aborted by writing 0x00 to FSTAT register. NOTE: command write sequence aborted by writing 0x00 to FSTAT register.
2.
3.
Access Error Check
yes
Write: Register FSTAT Clear bit ACCERR 0x10
Bit Polling for Command Completion Check yes
Bit CCIF Set?
no
Read: Register FSTAT
Read: Register FDATA Data Compress Signature
Signature Compared to Known Value
Signature Valid? yes EXIT
no
Erase and Reprogram Flash Region Compressed
Figure 2-24. Example Data Compress Command Flow
MC9S12HZ256 Data Sheet, Rev. 2.05 84 Freescale Semiconductor
Chapter 2 256 Kbyte Flash Module (FTS256K2V1)
2.4.1.3.3
Program Command
The program command is used to program a previously erased word in the Flash memory using an embedded algorithm. If the word to be programmed is in a protected area of the Flash block, the PVIOL flag in the FSTAT register will set and the program command will not launch. After the program command has successfully launched, the CCIF flag in the FSTAT register will set after the program operation has completed unless a second command has been buffered. A summary of the launching of a program operation is shown in Figure 2-25.
Read: Register FCLKDIV Clock Register Loaded Check
Bit FDIVLD set? yes
no
Write: Register FCLKDIV
1.
Write: Flash Address and Program Data Write: Register FCMD Program Command 0x20 Write: Register FSTAT Clear bit CBEIF 0x80 Read: Register FSTAT Bit PVIOL Set? no yes NOTE: command write sequence aborted by writing 0x00 to FSTAT register. NOTE: command write sequence aborted by writing 0x00 to FSTAT register.
2.
3.
Protection Violation Check
Write: Register FSTAT Clear bit PVIOL 0x20
Access Error Check
Bit ACCERR Set? no
yes
Write: Register FSTAT Clear bit ACCERR 0x10 yes
Address, Data, Command Buffer Empty Check
Bit CBEIF Set? no
yes
Next Write? no
Bit Polling for Command Completion Check
Bit CCIF Set? yes EXIT
no
Read: Register FSTAT
Figure 2-25. Example Program Command Flow
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 85
Chapter 2 256 Kbyte Flash Module (FTS256K2V1)
2.4.1.3.4
Sector Erase Command
The sector erase command is used to erase the addressed sector in the Flash memory using an embedded algorithm. If the Flash sector to be erased is in a protected area of the Flash block, the PVIOL flag in the FSTAT register will set and the sector erase command will not launch. After the sector erase command has successfully launched, the CCIF flag in the FSTAT register will set after the sector erase operation has completed unless a second command has been buffered.
Read: Register FCLKDIV Clock Register Loaded Check
Bit FDIVLD set? yes
no
Write: Register FCLKDIV
1.
Write: Flash Sector Address and Dummy Data Write: Register FCMD Sector Erase Command 0x40 Write: Register FSTAT Clear bit CBEIF 0x80 Read: Register FSTAT Bit PVIOL Set? no yes NOTE: command write sequence aborted by writing 0x00 to FSTAT register. NOTE: command write sequence aborted by writing 0x00 to FSTAT register.
2.
3.
Protection Violation Check
Write: Register FSTAT Clear bit PVIOL 0x20
Access Error Check
Bit ACCERR Set? no
yes
Write: Register FSTAT Clear bit ACCERR 0x10 yes
Address, Data, Command Buffer Empty Check
Bit CBEIF Set? no
yes
Next Write? no
Bit Polling for Command Completion Check
Bit CCIF Set? yes EXIT
no
Read: Register FSTAT
Figure 2-26. Example Sector Erase Command Flow
MC9S12HZ256 Data Sheet, Rev. 2.05 86 Freescale Semiconductor
Chapter 2 256 Kbyte Flash Module (FTS256K2V1)
2.4.1.3.5
Mass Erase Command
The mass erase command is used to erase a Flash memory block using an embedded algorithm. If the Flash block to be erased contains any protected area, the PVIOL flag in the FSTAT register will set and the mass erase command will not launch. After the mass erase command has successfully launched, the CCIF flag in the FSTAT register will set after the mass erase operation has completed unless a second command has been buffered.
Read: Register FCLKDIV Clock Register Loaded Check
Bit FDIVLD set? yes
no
Write: Register FCLKDIV
1.
Write: Flash Block Address and Dummy Data Write: Register FCMD Mass Erase Command 0x41 Write: Register FSTAT Clear bit CBEIF 0x80 Read: Register FSTAT Bit PVIOL Set? no Bit ACCERR Set? no yes yes NOTE: command write sequence aborted by writing 0x00 to FSTAT register. NOTE: command write sequence aborted by writing 0x00 to FSTAT register.
2.
3.
Protection Violation Check
Write: Register FSTAT Clear bit PVIOL 0x20
Access Error Check
Write: Register FSTAT Clear bit ACCERR 0x10 yes
Address, Data, Command Buffer Empty Check
Bit CBEIF Set? no
yes
Next Write? no
Bit Polling for Command Completion Check
Bit CCIF Set? yes EXIT
no
Read: Register FSTAT
Figure 2-27. Example Mass Erase Command Flow
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 87
Chapter 2 256 Kbyte Flash Module (FTS256K2V1)
2.4.1.3.6
Sector Erase Abort Command
The sector erase abort command is used to terminate the sector erase operation so that other sectors in the Flash block are available for read and program operations without waiting for the sector erase operation to complete. If the sector erase abort command is launched resulting in the early termination of an active sector erase operation, the ACCERR flag will set after the operation completes as indicated by the CCIF flag being set. The ACCERR flag sets to inform the user that the sector may not be fully erased and a new sector erase command must be launched before programming any location in that specific sector. If the sector erase abort command is launched but the active sector erase operation completes normally, the ACCERR flag will not set upon completion of the operation as indicated by the CCIF flag being set. Therefore, if the ACCERR flag is not set after the sector erase abort command has completed, the sector being erased when the abort command was launched is fully erased. The maximum number of cycles required to abort a sector erase operation is equal to four FCLK periods (see Section 2.4.1.1, "Writing the FCLKDIV Register") plus five bus cycles as measured from the time the CBEIF flag is cleared until the CCIF flag is set. NOTE Since the ACCERR bit in the FSTAT register may be set at the completion of the sector erase abort operation, a command write sequence is not allowed to be buffered behind a sector erase abort command write sequence. The CBEIF flag will not set after launching the sector erase abort command to indicate that a command must not be buffered behind it. If an attempt is made to start a new command write sequence with a sector erase abort operation active, the ACCERR flag in the FSTAT register will be set. A new command write sequence may be started after clearing the ACCERR flag, if set. NOTE The sector erase abort command must be used sparingly because a sector erase operation that is aborted counts as a complete program/erase cycle.
MC9S12HZ256 Data Sheet, Rev. 2.05 88 Freescale Semiconductor
Chapter 2 256 Kbyte Flash Module (FTS256K2V1)
Execute Sector Erase Command Flow
Bit Polling for Command Completion Check
Bit CCIF Set? yes EXIT 1.
no
Erase Abort Needed? yes
no
Read: Register FSTAT
Write: Dummy Flash Address and Dummy Data Write: Register FCMD Sector Erase Abort Cmd 0x47 Write: Register FSTAT Clear bit CBEIF 0x80 Read: Register FSTAT
NOTE: command write sequence aborted by writing 0x00 to 2. FSTAT register. NOTE: command write sequence aborted by writing 0x00 to 3. FSTAT register.
Bit Polling for Command Completion Check
Bit CCIF Set? yes
no
Read: Register FSTAT
Access Error Check
Bit ACCERR Set? no
yes
Write: Register FSTAT Clear bit ACCERR 0x10
EXIT Sector Erase Completed
EXIT Sector Erase Aborted
Figure 2-28. Example Sector Erase Abort Command Flow
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 89
Chapter 2 256 Kbyte Flash Module (FTS256K2V1)
2.4.1.4
Illegal Flash Operations
The ACCERR flag will be set during the command write sequence if any of the following illegal steps are performed, causing the command write sequence to immediately abort: 1. Writing to a Flash address before initializing the FCLKDIV register. 2. Writing to a Flash address in the range 0x8000-0xBFFF when the PPAGE register does not select a 16 Kbyte page in the Flash block selected by the BKSEL bit in the FCNFG register. 3. Writing to a Flash address in the range 0x4000-0x7FFF or 0xC000-0xFFFF with the BKSEL bit in the FCNFG register not selecting Flash block 0. 4. Writing a byte or misaligned word to a valid Flash address. 5. Starting a command write sequence while a data compress operation is active. 6. Starting a command write sequence while a sector erase abort operation is active. 7. Writing a second word to a Flash address in the same command write sequence. 8. Writing to any Flash register other than FCMD after writing a word to a Flash address. 9. Writing a second command to the FCMD register in the same command write sequence. 10. Writing an invalid command to the FCMD register. 11. When security is enabled, writing a command other than mass erase to the FCMD register when the write originates from a non-secure memory location or from the Background Debug Mode. 12. Writing to any Flash register other than FSTAT (to clear CBEIF) after writing to the FCMD register. 13. Writing a 0 to the CBEIF flag in the FSTAT register to abort a command write sequence. The ACCERR flag will not be set if any Flash register is read during a valid command write sequence. The ACCERR flag will also be set if any of the following events occur: 1. Launching the sector erase abort command while a sector erase operation is active which results in the early termination of the sector erase operation (see Section 2.4.1.3.6, "Sector Erase Abort Command") 2. The MCU enters stop mode and a program or erase operation is in progress. The operation is aborted immediately and any pending command is purged (see Section 2.5.2, "Stop Mode"). If the Flash memory is read during execution of an algorithm (i.e., CCIF flag in the FSTAT register is low), the read operation will return invalid data and the ACCERR flag will not be set. If the ACCERR flag is set in the FSTAT register, the user must clear the ACCERR flag before starting another command write sequence (see Section 2.3.2.7, "Flash Status Register (FSTAT)"). The PVIOL flag will be set after the command is written to the FCMD register during a command write sequence if any of the following illegal operations are attempted, causing the command write sequence to immediately abort: 1. Writing the program command if the address written in the command write sequence was in a protected area of the Flash memory. 2. Writing the sector erase command if the address written in the command write sequence was in a protected area of the Flash memory. 3. Writing the mass erase command while any Flash protection is enabled.
MC9S12HZ256 Data Sheet, Rev. 2.05 90 Freescale Semiconductor
Chapter 2 256 Kbyte Flash Module (FTS256K2V1)
If the PVIOL flag is set in the FSTAT register, the user must clear the PVIOL flag before starting another command write sequence (see Section 2.3.2.7, "Flash Status Register (FSTAT)").
2.5
2.5.1
Operating Modes
Wait Mode
If a command is active (CCIF = 0) when the MCU enters wait mode, the active command and any buffered command will be completed. The Flash module can recover the MCU from wait mode if the CBEIF and CCIF interrupts are enabled (Section 2.8, "Interrupts").
2.5.2
Stop Mode
If a command is active (CCIF = 0) when the MCU enters stop mode, the operation will be aborted and, if the operation is program or erase, the Flash array data being programmed or erased may be corrupted and the CCIF and ACCERR flags will be set. If active, the high voltage circuitry to the Flash memory will immediately be switched off when entering stop mode. Upon exit from stop mode, the CBEIF flag is set and any buffered command will not be launched. The ACCERR flag must be cleared before starting a command write sequence (see Section 2.4.1.2, "Command Write Sequence"). NOTE As active commands are immediately aborted when the MCU enters stop mode, it is strongly recommended that the user does not use the STOP instruction during program or erase operations.
2.5.3
Background Debug Mode
In background debug mode (BDM), the FPROT register is writable. If the MCU is unsecured, then all Flash commands listed in Table 2-20 can be executed.
2.6
Flash Module Security
The Flash module provides the necessary security information to the MCU. After each reset, the Flash module determines the security state of the MCU as defined in Section 2.3.2.2, "Flash Security Register (FSEC)". The contents of the Flash security byte at 0xFF0F in the Flash configuration field must be changed directly by programming 0xFF0F when the MCU is unsecured and the higher address sector is unprotected. If the Flash security byte remains in a secured state, any reset will cause the MCU to initialize to a secure operating mode.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 91
Chapter 2 256 Kbyte Flash Module (FTS256K2V1)
2.6.1
Unsecuring the MCU using Backdoor Key Access
The MCU may be unsecured by using the backdoor key access feature which requires knowledge of the contents of the backdoor keys (four 16-bit words programmed at addresses 0xFF00-0xFF07). If the KEYEN[1:0] bits are in the enabled state (see Section 2.3.2.2, "Flash Security Register (FSEC)") and the KEYACC bit is set, a write to a backdoor key address in the Flash memory triggers a comparison between the written data and the backdoor key data stored in the Flash memory. If all four words of data are written to the correct addresses in the correct order and the data matches the backdoor keys stored in the Flash memory, the MCU will be unsecured. The data must be written to the backdoor keys sequentially starting with 0xFF00-0xFF01 and ending with 0xFF06-0xFF07. 0x0000 and 0xFFFF are not permitted as backdoor keys. While the KEYACC bit is set, reads of the Flash memory will return invalid data. The user code stored in the Flash memory must have a method of receiving the backdoor key from an external stimulus. This external stimulus would typically be through one of the on-chip serial ports. If the KEYEN[1:0] bits are in the enabled state (see Section 2.3.2.2, "Flash Security Register (FSEC)"), the MCU can be unsecured by the backdoor access sequence described below: 1. Set the KEYACC bit in the Flash configuration register (FCNFG). 2. Write the correct four 16-bit words to Flash addresses 0xFF00-0xFF07 sequentially starting with 0xFF00. 3. Clear the KEYACC bit. 4. If all four 16-bit words match the backdoor keys stored in Flash addresses 0xFF00-0xFF07, the MCU is unsecured and the SEC[1:0] bits in the FSEC register are forced to the unsecure state of 1:0. The backdoor key access sequence is monitored by an internal security state machine. An illegal operation during the backdoor key access sequence will cause the security state machine to lock, leaving the MCU in the secured state. A reset of the MCU will cause the security state machine to exit the lock state and allow a new backdoor key access sequence to be attempted. The following operations during the backdoor key access sequence will lock the security state machine: 1. If any of the four 16-bit words does not match the backdoor keys programmed in the Flash array. 2. If the four 16-bit words are written in the wrong sequence. 3. If more than four 16-bit words are written. 4. If any of the four 16-bit words written are 0x0000 or 0xFFFF. 5. If the KEYACC bit does not remain set while the four 16-bit words are written. 6. If any two of the four 16-bit words are written on successive MCU clock cycles. After the backdoor keys have been correctly matched, the MCU will be unsecured. After the MCU is unsecured, the Flash security byte can be programmed to the unsecure state, if desired. In the unsecure state, the user has full control of the contents of the backdoor keys by programming addresses 0xFF00-0xFF07 in the Flash configuration field. The security as defined in the Flash security byte (0xFF0F) is not changed by using the backdoor key access sequence to unsecure. The backdoor keys stored in addresses 0xFF00-0xFF07 are unaffected by the backdoor key access sequence. After the next reset of the MCU, the security state of the Flash module
MC9S12HZ256 Data Sheet, Rev. 2.05 92 Freescale Semiconductor
Chapter 2 256 Kbyte Flash Module (FTS256K2V1)
is determined by the Flash security byte (0xFF0F). The backdoor key access sequence has no effect on the program and erase protections defined in the Flash protection register. It is not possible to unsecure the MCU in special single-chip mode by using the backdoor key access sequence via the background debug mode (BDM).
2.6.2
Unsecuring the Flash Module in Special Single-Chip Mode using BDM
The MCU can be unsecured in special single-chip mode by erasing the Flash module by the following method : * Reset the MCU into special single-chip mode, delay while the erase test is performed by the BDM secure ROM, send BDM commands to disable protection in the Flash module, and execute a mass erase command write sequence to erase the Flash memory. After the CCIF flag sets to indicate that the mass operation has completed, reset the MCU into special single-chip mode. The BDM secure ROM will verify that the Flash memory is erased and will assert the UNSEC bit in the BDM status register. This BDM action will cause the MCU to override the Flash security state and the MCU will be unsecured. All BDM commands will be enabled and the Flash security byte may be programmed to the unsecure state by the following method: * Send BDM commands to execute a word program sequence to program the Flash security byte to the unsecured state and reset the MCU.
2.7
2.7.1
Resets
Flash Reset Sequence
On each reset, the Flash module executes a reset sequence to hold CPU activity while loading the following registers from the Flash memory according to Table 2-1: * FPROT -- Flash Protection Register (see Section 2.3.2.5). * FCTL -- Flash Control Register (see Section 2.3.2.9). * FSEC -- Flash Security Register (see Section 2.3.2.2).
2.7.2
Reset While Flash Command Active
If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The state of the word being programmed or the sector / block being erased is not guaranteed.
2.8
Interrupts
The Flash module can generate an interrupt when all Flash command operations have completed, when the Flash address, data, and command buffers are empty.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 93
Chapter 2 256 Kbyte Flash Module (FTS256K2V1)
Table 2-21. Flash Interrupt Sources
Interrupt Source Flash address, data and command buffers empty All Flash commands completed Interrupt Flag Local Enable Global (CCR) Mask I Bit I Bit
CBEIF (FSTAT register) CBEIE (FCNFG register) CCIF (FSTAT register) CCIE (FCNFG register)
NOTE Vector addresses and their relative interrupt priority are determined at the MCU level.
2.8.1
Description of Flash Interrupt Operation
The logic used for generating interrupts is shown in Figure 2-29. The Flash module uses the CBEIF and CCIF flags in combination with the CBIE and CCIE enable bits to generate the Flash command interrupt request.
Block 0 CBEIF Block 0 Select Block 1 CBEIF Block 1 Select CBEIE Flash Command Interrupt Request Block 0 CCIF Block 0 Select Block 1 CCIF Block 1 Select CCIE
Figure 2-29. Flash Interrupt Implementation
For a detailed description of the register bits, refer to Section 2.3.2.4, "Flash Configuration Register (FCNFG)" and Section 2.3.2.7, "Flash Status Register (FSTAT)".
MC9S12HZ256 Data Sheet, Rev. 2.05 94 Freescale Semiconductor
Chapter 3 2 Kbyte EEPROM Module (EETS2KV1)
3.1 Introduction
This document describes the EETS2K module which is a 2 Kbyte EEPROM (nonvolatile) memory. The EETS2K block uses a small sector Flash memory to emulate EEPROM functionality. It is an array of electrically erasable and programmable, nonvolatile memory. The EEPROM memory is organized as 1024 rows of 2 bytes (1 word). The EEPROM memory's erase sector size is 2 rows or 2 words (4 bytes). The EEPROM memory may be read as either bytes, aligned words, or misaligned words. Read access time is one bus cycle for byte and aligned word, and two bus cycles for misaligned words. Program and erase functions are controlled by a command driven interface. Both sector erase and mass erase of the entire EEPROM memory are supported. An erased bit reads 1 and a programmed bit reads 0. The high voltage required to program and erase is generated internally by on-chip charge pumps. It is not possible to read from the EEPROM memory while it is being erased or programmed. The EEPROM memory is ideal for data storage for single-supply applications allowing for field reprogramming without requiring external programming voltage sources. CAUTION An EEPROM word must be in the erased state before being programmed. Cumulative programming of bits within a word is not allowed.
3.1.1
Glossary
Command Write Sequence -- A three-step MCU instruction sequence to program, erase, or erase verify the EEPROM.
3.1.2
* * * * * * * *
Features
2 Kbytes of EEPROM memory Minimum erase sector of 4 bytes Automated program and erase algorithms Interrupts on EEPROM command completion and command buffer empty Fast sector erase and word program operation 2-stage command pipeline Flexible protection scheme for protection against accidental program or erase Single power supply program and erase
MC9S12HZ256 Data Sheet, Rev. 2.05
Freescale Semiconductor
95
Chapter 3 2 Kbyte EEPROM Module (EETS2KV1)
3.1.3
Modes of Operation
Program and erase operation (please refer to Section 3.4.1 for details).
3.1.4
Block Diagram
Figure 3-1 shows a block diagram of the EETS2K module.
EETS2K
Command Interface
Registers
EEPROM Array 1024 * 16 Bits
row0 row1
Command Pipeline
comm2 addr2 data2 comm1 addr1 data1
row1023
Command Complete Interrupt
Command Buffer Empty Interrupt Oscillator Clock
Clock Divider
EECLK
Figure 3-1. EETS2K Block Diagram
3.2
External Signal Description
The EETS2K module contains no signals that connect off chip.
3.3
Memory Map and Register Definition
This section describes the EETS2K memory map and registers.
3.3.1
Module Memory Map
Figure 3-2 shows the EETS2K memory map. Location of the EEPROM array in the MCU memory map is defined in the Device Overview chapter and is reflected in the INITEE register contents defined in the INT block description chapter. Shown within the EEPROM array are: a protection/reserved field and user-defined EEPROM protected sectors. The 16-byte protection/reserved field is located in the EEPROM array from address 0x07F0 to 0x07FF. A description of this protection/reserved field is given in Table 3-1.
MC9S12HZ256 Data Sheet, Rev. 2.05 96 Freescale Semiconductor
Chapter 3 2 Kbyte EEPROM Module (EETS2KV1)
Table 3-1. EEPROM Protection/Reserved Field
Address Offset 0x07F0 - 0x07FC 0x07FD 0x07FE - 0x07FF Size (Bytes) 13 1 2 Description Reserved EEPROM protection byte Reserved
The EEPROM module has hardware interlocks which protect data from accidental corruption. A protected sector is located at the higher address end of the EEPROM array, just below address 0x07FF. The protected sector in the EEPROM array can be sized from 64 bytes to 512 bytes. In addition, the EPOPEN bit in the EPROT register, described in Section 3.3.2.5, "EEPROM Protection Register (EPROT)", can be set to globally protect the entire EEPROM array. Chip security is defined at the MCU level.
(12 BYTES) MODULE BASE + 0x0000 EEPROM Registers MODULE BASE + 0x000B EEPROM BASE + 0x0000
1536 BYTES EEPROM ARRAY
0x0600 0x0640 0x0680 0x06C0 0x0700 0x0740 0x0780 0x07C0 EEPROM BASE + 0x07FF 0x07F0 - 0x07FF, EEPROM Protection/Reserved Field EEPROM Protected High Sectors 64, 128, 192, 256, 320, 384, 448, 512 bytes
Figure 3-2. EEPROM Memory Map
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 97
Chapter 3 2 Kbyte EEPROM Module (EETS2KV1)
The EEPROM module also contains a set of 12 control and status registers located in address space module base + 0x0000 to module base + 0x000B. Table 3-2 gives an overview of all EETS2K registers.
Table 3-2. EEPROM Register Map
Module Base + 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B
1 1
Register Name EEPROM Clock Divider Register (ECLKDIV) RESERVED1 RESERVED21 EEPROM Configuration Register (ECNFG) EEPROM Protection Register (EPROT) EEPROM Status Register (ESTAT) EEPROM Command Register (ECMD) RESERVED31 EEPROM High Address Register (EADDRHI) EEPROM Low Address Register (EADDRLO) EEPROM High Data Register (EDATAHI) EEPROM Low Data Register (EDATALO)
Normal Mode Access R/W R R R/W R/W R/W R/W R R/W R/W R/W R/W
Intended for factory test purposes only.
MC9S12HZ256 Data Sheet, Rev. 2.05 98 Freescale Semiconductor
Chapter 3 2 Kbyte EEPROM Module (EETS2KV1)
3.3.2
Register Descriptions
Bit 7 R W EDIVLD 6 PRDIV8 0 5 EDIV5 0 4 EDIV4 0 3 EDIV3 0 2 EDIV2 0 1 EDIV1 0 Bit 0 EDIV0 0
Register Name ECLKDIV
RESERVED1
R W
0
RESERVED2
R W
0
0
0
0
0
0
0
0
ECNFG
R W
CBEIE
CCIE NV6
0
0
0
0
0
0
EPROT
R W
EPOPEN
NV5
NV4
EPDIS 0
EP2 BLANK
EP1 0
EPO 0
ESTAT
R W
CBEIF 0
CCIF
PVIOL
ACCERR 0
ECMD
R W
CMDB6 0
CMDB5 0
0
CMDB2 0
0
CMDB0 0
RESERVED3
R W
0
0
0
0
EADDRHI
R W
0
0
0
0
0
0
EABHI
EADDRLO
R W
EABLO
EDATAHI
R W
EDHI
EDATALO
R W = Unimplemented or Reserved
EDLO
Figure 3-3. EETS2K Register Summary
3.3.2.1
EEPROM Clock Divider Register (ECLKDIV)
The ECLKDIV register is used to control timed events in program and erase algorithms.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 99
Chapter 3 2 Kbyte EEPROM Module (EETS2KV1)
7 R W Reset 0 EDIVLD
6 PRDIV8 0
5 EDIV5 0
4 EDIV4 0
3 EDIV3 0
2 EDIV2 0
1 EDIV1 0
0 EDIV0 0
= Unimplemented or Reserved
Figure 3-4. EEPROM Clock Divider Register (ECLKDIV)
All bits in the ECLKDIV register are readable while bits 6-0 are write once and bit 7 is not writable.
Table 3-3. ECLKDIV Field Descriptions
Field 7 EDIVLD 6 PRDIV8 5:0 EDIV[5:0] Description Clock Divider Loaded 0 Register has not been written. 1 Register has been written to since the last reset. Enable Prescaler by 8 0 The oscillator clock is directly fed into the ECLKDIV divider. 1 The oscillator clock is divided by 8 before feeding into the clock divider. Clock Divider Bits -- The combination of PRDIV8 and EDIV[5:0] must divide the oscillator clock down to a frequency of 150 kHz - 200 kHz. The maximum divide ratio is 512. Please refer to Section 3.4.1.1, "Writing the ECLKDIV Register" for more information.
3.3.2.2
RESERVED1
This register is reserved for factory testing and is not accessible to the user.
7 R W Reset 0 0 0 0 0 0 0 0 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
= Unimplemented or Reserved
Figure 3-5. RESERVED1
All bits read 0 and are not writable.
3.3.2.3
RESERVED2
This register is reserved for factory testing and is not accessible to the user.
7 R W Reset 0 0 0 0 0 0 0 0 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
= Unimplemented or Reserved
Figure 3-6. RESERVED2
MC9S12HZ256 Data Sheet, Rev. 2.05 100 Freescale Semiconductor
Chapter 3 2 Kbyte EEPROM Module (EETS2KV1)
All bits read 0 and are not writable.
3.3.2.4
EEPROM Configuration Register (ECNFG)
The ECNFG register enables the EEPROM interrupts.
7 R CBEIE W Reset 0 0 0 0 0 0 0 0 CCIE 6 5 0 4 0 3 0 2 0 1 0 0 0
= Unimplemented or Reserved
Figure 3-7. EEPROM Configuration Register (ECNFG)
CBEIE and CCIE bits are readable and writable while bits 5-0 read 0 and are not writable.
Table 3-4. ECNFG Field Descriptions
Field 7 CBEIE Description Command Buffer Empty Interrupt Enable -- The CBEIE bit enables the interrupts in case of an empty command buffer in the EEPROM. 0 Command buffer empty interrupts disabled. 1 An interrupt will be requested whenever the CBEIF flag is set (see Section 3.3.2.6, "EEPROM Status Register (ESTAT)"). Command Complete Interrupt Enable -- The CCIE bit enables the interrupts in case of all commands being completed in the EEPROM. 0 Command complete interrupts disabled. 1 An interrupt will be requested whenever the CCIF flag is set (see Section 3.3.2.6, "EEPROM Status Register (ESTAT)").
6 CCIE
3.3.2.5
EEPROM Protection Register (EPROT)
The EPROT register defines which EEPROM sectors are protected against program or erase.
7 R EPOPEN W Reset F F F F F F F F 6 NV6 5 NV5 4 NV4 EPDIS EP2 EP1 EP0 3 2 1 0
= Unimplemented or Reserved
Figure 3-8. EEPROM Protection Register (EPROT)
The EPROT register is loaded from EEPROM array address 0x07FD during reset, as indicated by the F in Figure 3-8. All bits in the EPROT register are readable. Bits NV[6:4] are not writable. The EPOPEN and EPDIS bits in the EPROT register can only be written to the protected state (i.e., 0). The EP[2:0] bits can be written anytime until bit EPDIS is cleared. If the EPOPEN bit is cleared, then the state of the EPDIS and EP[2:0] bits is irrelevant.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 101
Chapter 3 2 Kbyte EEPROM Module (EETS2KV1)
To change the EEPROM protection that will be loaded on reset, the upper sector of EEPROM must first be unprotected, then the EEPROM protect byte located at address 0x07FD must be written to. A protected EEPROM sector is disabled by the EPDIS bit while the size of the protected sector is defined by the EP bits in the EPROT register. Trying to alter any of the protected areas will result in a protect violation error and PVIOL flag will be set in the ESTAT register. A mass erase of a whole EEPROM block is only possible when protection is fully disabled by setting the EPOPEN and EPDIS bits. An attempt to mass erase an EEPROM block while protection is enabled will set the PVIOL flag in the ESTAT register.
Table 3-5. EPROT Field Descriptions
Field 7 EPOPEN Description Opens EEPROM for Program or Erase 0 The whole EEPROM array is protected. In this case, the EPDIS and EP bits within the protection register are ignored. 1 The EEPROM sectors not protected are enabled for program or erase. Nonvolatile Flag Bits -- These three bits are available to the user as nonvolatile flags. EEPROM Protection Address Range Disable -- The EPDIS bit determines whether there is a protected area in the space of the EEPROM address map. 0 Protection enabled 1 Protection disabled EEPROM Protection Address Size -- The EP[2:0] bits determine the size of the protected sector. Refer to Table 3-6.
6:4 NV[6:4] 3 EPDIS
2:0 EP[2:0]
Table 3-6. EEPROM Address Range Protection
EP[2:0] 000 001 010 011 100 101 110 111 Protected Address Range 0x07C0-0x07FF 0x0780-0x07FF 0x0740-0x07FF 0x0700-0x07FF 0x06C0-0x07FF 0x0680-0x07FF 0x0640-0x07FF 0x0600-0x07FF Protected Size 64 bytes 128 bytes 192 bytes 256 bytes 320 bytes 384 bytes 448 bytes 512 bytes
3.3.2.6
EEPROM Status Register (ESTAT)
The ESTAT register defines the EEPROM state machine command status and EEPROM array access, protection and erase verify status.
MC9S12HZ256 Data Sheet, Rev. 2.05 102 Freescale Semiconductor
Chapter 3 2 Kbyte EEPROM Module (EETS2KV1)
7 R CBEIF W Reset 1
6 CCIF
5 PVIOL
4 ACCERR 0
3 0
2 BLANK
1 0
0 0
1
0
0
0
0
0
= Unimplemented or Reserved
Figure 3-9. EEPROM Status Register (ESTAT - Normal Mode)
7 R CBEIF W Reset 1 1 0 0 0 0 0 1 6 CCIF PVIOL ACCERR 5 4 3 0 2 BLANK FAIL 1 0 DONE
= Unimplemented or Reserved
Figure 3-10. EEPROM Status Register (ESTAT - Special Mode)
CBEIF, PVIOL, and ACCERR bits are readable and writable, CCIF and BLANK bits are readable but not writable, remaining bits read 0 and are not writable in normal mode. FAIL is readable and writable in special mode. FAIL must be clear when starting a command write sequence. DONE is readable but not writable in special mode.
Table 3-7. ESTAT Field Descriptions
Field 7 CBEIF Description Command Buffer Empty Interrupt Flag -- The CBEIF flag indicates that the address, data, and command buffers are empty so that a new command sequence can be started. The CBEIF flag is cleared by writing a 1 to CBEIF. Writing a 0 to the CBEIF flag has no effect on CBEIF. Writing a 0 to CBEIF after writing an aligned word to the EEPROM address space but before CBEIF is cleared will abort a command sequence and cause the ACCERR flag in the ESTAT register to be set. Writing a 0 to CBEIF outside of a command sequence will not set the ACCERR flag. The CBEIF flag is used together with the CBEIE bit in the ECNFG register to generate an interrupt request. 0 Buffers are full 1 Buffers are ready to accept a new command Command Complete Interrupt Flag -- The CCIF flag indicates that there are no more commands pending. The CCIF flag is cleared when CBEIF is cleared and sets automatically upon completion of all active and pending commands. The CCIF flag does not set when an active command completes and a pending command is fetched from the command buffer. Writing to the CCIF flag has no effect. The CCIF flag is used together with the CCIE bit in the ECNFG register to generate an interrupt request. 0 Command in progress 1 All commands are completed Protection Violation -- The PVIOL flag indicates an attempt was made to program or erase an address in a protected EEPROM memory area (Section 3.4.1.4, "Illegal EEPROM Operations"). The PVIOL flag is cleared by writing a 1 to PVIOL. Writing a 0 to the PVIOL flag has no effect on PVIOL. While PVIOL is set, it is not possible to launch another command in the EEPROM. 0 No failure 1 A protection violation has occurred
6 CCIF
5 PVIOL
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 103
Chapter 3 2 Kbyte EEPROM Module (EETS2KV1)
Table 3-7. ESTAT Field Descriptions (continued)
Field 4 ACCERR Description EEPROM Access Error -- The ACCERR flag indicates an illegal access to the selected EEPROM array (Section 3.4.1.4, "Illegal EEPROM Operations). This can be either a violation of the command sequence, issuing an illegal command (illegal combination of the CMDBx bits in the ECMD register) or the execution of a CPU STOP instruction while a command is executing (CCIF = 0). The ACCERR flag is cleared by writing a 1 to ACCERR. Writing a 0 to the ACCERR flag has no effect on ACCERR. While ACCERR is set, it is not possible to launch another command in the EEPROM. 0 No failure 1 Access error has occurred Array Has Been Verified as Erased -- The BLANK flag indicates that an erase verify command has checked the EEPROM array and found it to be erased. The BLANK flag is cleared by hardware when CBEIF is cleared as part of a new valid command sequence. Writing to the BLANK flag has no effect on BLANK. 0 If an erase verify command has been requested and the CCIF flag is set, then a 0 in BLANK indicates array is not erased 1 EEPROM array verifies as erased Flag Indicating a Failed EEPROM Operation -- The FAIL flag will set if the erase verify operation fails (EEPROM block verified as not erased). The FAIL flag is cleared writing a 1 to FAIL. Writing a 0 to the FAIL flag has no effect on FAIL. 0 EEPROM operation completed without error 1 EEPROM operation failed Flag Indicating a Completed EEPROM Operation 0 EEPROM operation is active (program, erase, erase verify) 1 EEPROM operation not active
2 BLANK
1 FAIL
0 DONE
3.3.2.7
EEPROM Command Register (ECMD)
The ECMD register defines the EEPROM commands.
7 R W Reset 0 0 0 0 0 0 0 0 0 CMDB6 CMDB5 6 5 4 0 3 0 CMDB2 2 1 0 CMDB0 0
= Unimplemented or Reserved
Figure 3-11. EEPROM Command Register (ECMD)
CMDB6, CMDB5, CMDB2, and CMDB0 bits are readable and writable during a command sequence while bits 7, 4, 3, and 1 read 0 and are not writable.
Table 3-8. ECMD Field Descriptions
Field 6, 5, 2, 0 CMDB[6:5] CMDB2 CMDB0 Description EEPROM Command -- Valid EEPROM commands are shown in Table 3-9. Any other command written than those mentioned in Table 3-9 sets the ACCERR bit in the ESTAT register.
MC9S12HZ256 Data Sheet, Rev. 2.05 104 Freescale Semiconductor
Chapter 3 2 Kbyte EEPROM Module (EETS2KV1)
Table 3-9. Valid EEPROM Command List
Command 0x05 0x20 0x40 0x41 0x60 Meaning Erase verify Word program Sector erase Mass erase Sector modify
3.3.2.8
RESERVED3
This register is reserved for factory testing and is not accessible to the user.
7 R W Reset 0 0 0 0 0 0 0 0 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
= Unimplemented or Reserved
Figure 3-12. RESERVED3
All bits read 0 and are not writable.
3.3.2.9
EEPROM Address Register (EADDR)
EADDRHI and EADDRLO are the EEPROM address registers.
7 R W Reset 0 0 0 0 0 0 0 0 0 6 0 5 0 4 0 3 0 2 0 EABHI 1 0
= Unimplemented or Reserved
Figure 3-13. EEPROM Address High Register (EADDRHI)
7 R EABLO W Reset 0 0 0 0 0 0 0 0 6 5 4 3 2 1 0
Figure 3-14. EEPROM Address Low Register (EADDRLO)
In normal modes, all EADDRHI and EADDRLO bits read 0 and are not writable. In special modes, all EADDRHI and EADDRLO bits are readable and writable except EADDRHI[7:2] which are not writable and always read 0.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 105
Chapter 3 2 Kbyte EEPROM Module (EETS2KV1)
For sector erase, the MCU address bits AB[1:0] are ignored. For mass erase, any address within the block is valid to start the command.
MC9S12HZ256 Data Sheet, Rev. 2.05 106 Freescale Semiconductor
Chapter 3 2 Kbyte EEPROM Module (EETS2KV1)
3.3.2.10
EEPROM Data Register (EDATA)
EDATAHI and EDATALO are the EEPROM data registers.
7 R EDHI W Reset 0 0 0 0 0 0 0 0 6 5 4 3 2 1 0
Figure 3-15. EEPROM Data High Register (EDATAHI)
7 R EDLO W Reset 0 0 0 0 0 0 0 0 6 5 4 3 2 1 0
Figure 3-16. EEPROM Data Low Register (EDATALO)
In normal modes, all EDATAHI and EDATALO bits read 0 and are not writable. In special modes, all EDATAHI and EDATALO bits are readable and writable.
3.4
3.4.1
Functional Description
Program and Erase Operation
Write and read operations are both used for the program and erase algorithms described in this subsection. These algorithms are controlled by a state machine whose timebase, EECLK, is derived from the oscillator clock via a programmable divider. The command register as well as the associated address and data registers operate as a buffer and a register (2-stage FIFO) so that a new command along with the necessary data and address can be stored to the buffer while the previous command is remains in progress. The pipelined operation allows a simplification of command launching. Buffer empty as well as command completion are signalled by flags in the EEPROM status register. Interrupts for the EEPROM will be generated if enabled. The next four subsections describe: * How to write the ECLKDIV register. * Command write sequences used to program, erase, and verify the EEPROM memory. * Valid EEPROM commands. * Errors resulting from illegal EEPROM operations.
3.4.1.1
Writing the ECLKDIV Register
Prior to issuing any program or erase command, it is first necessary to write the ECLKDIV register to divide the oscillator down to within 150 kHz to 200 kHz range. The program and erase timings are also a
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 107
Chapter 3 2 Kbyte EEPROM Module (EETS2KV1)
function of the bus clock, such that the ECLKDIV determination must take this information into account. If we define: * EECLK as the clock of the EEPROM timing control block * Tbus as the period of the bus clock * INT(x) as taking the integer part of x (e.g., INT(4.323)=4), then ECLKDIV register bits PRDIV8 and EDIV[5:0] are to be set as described in Figure 3-17. For example, if the oscillator clock is 950 kHz and the bus clock is 10 MHz, ECLKDIV bits EDIV[5:0] must be set to 4 (binary 000100) and bit PRDIV8 set to 0. The resulting EECLK is then 190 kHz. As a result, the EEPROM algorithm timings are increased over optimum target by: ( 200 - 190 ) 200 x 100 = 5% Command execution time will increase proportionally with the period of EECLK. CAUTION Because of the impact of clock synchronization on the accuracy of the functional timings, programming or erasing the EEPROM cannot be performed if the bus clock runs at less than 1 MHz. Programming the EEPROM with an oscillator clock < 150 kHz must be avoided. Setting ECLKDIV to a value such that EECLK < 150 kHz can reduce the lifetime of the EEPROM due to overstress. Setting ECLKDIV to a value such that (1/EECLK+Tbus) < 5s can result in incomplete programming or erasure of the memory array cells. If the ECLKDIV register is written, the bit EDIVLD is set automatically. If this bit is 0, the register has not been written since the last reset. EEPROM commands will not be executed if this register has not been written to.
MC9S12HZ256 Data Sheet, Rev. 2.05 108 Freescale Semiconductor
Chapter 3 2 Kbyte EEPROM Module (EETS2KV1)
START
Tbus 1 s?
NO
PROGRAM/ERASE IMPOSSIBLE
yes PRDIV8 = 0 (reset)
OSCILLATOR CLOCK > 12.8 MHz? yes PRDIV8 = 1 PRDCLK = oscillator clock/8
NO
PRDCLK = oscillator clock
PRDCLK[MHz]*(5+Tbus[s]) an integer? YES
NO
EDIV[5:0] = INT(PRDCLK[MHz]*(5+Tbus[s]))
EDIV[5:0] = PRDCLK[MHz]*(5+Tbus[s])-1
TRY TO DECREASE Tbus
EECLK = (PRDCLK)/(1+EDIV[5:0])
1/EECLK [MHz] + Tbus[ms] 5 AND EECLK > 0.15 MHz ? NO
YES
END
YES
EDIV[5:0] 4?
NO
PROGRAM/ERASE IMPOSSIBLE
Figure 3-17. PRDIV8 and EDIV Bits Determination Procedure
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 109
Chapter 3 2 Kbyte EEPROM Module (EETS2KV1)
3.4.1.2
Command Write Sequence
The EEPROM command controller is used to supervise the command write sequence to execute program, erase, mass erase, sector modify, and erase verify operations. Before starting a command write sequence, it is necessary to check that there is no pending access error or protection violation (the ACCERR and PVIOL flags must be cleared in the ESTAT register). After this initial step, the CBEIF flag must be tested to ensure that the address, data and command buffers are empty. If so, the command sequence can be started. The following 3-step command write sequence must be strictly adhered to and no intermediate access to the EEPROM array is permitted between the 3 steps. It is possible to read any EEPROM register during a command sequence. The command write sequence is as follows: 1. Write an aligned word to be to a valid EEPROM array address. The address and data will be stored in internal buffers. -- For program and sector modify, all address and data bits are valid. -- For erase, the value of the data bytes are ignored. -- For mass erase and erase verify, the address can be anywhere in the available address space of the array. -- For sector erase, the address bits[1:0] are ignored. 2. Write a valid command, listed in Table 3-10, to the ECMD register. 3. Clear the CBEIF flag by writing a 1 to CBEIF to launch the command. When the CBEIF flag is cleared, the CCIF flag is cleared by hardware indicating that the command was successfully launched. The CBEIF flag will be set again indicating the address, data, and command buffers are ready for a new command write sequence to begin. The completion of the command is indicated by the CCIF flag setting. The CCIF flag only sets when all active and pending commands have been completed. The EEPROM command controller will flag errors in command write sequences by means of the ACCERR (access error) and PVIOL (protection violation) flags in the ESTAT register. An erroneous command write sequence will abort and set the appropriate flag. If set, the user must clear the ACCERR or PVIOL flags before commencing another command write sequence. By writing a 0 to the CBEIF flag the command sequence can be aborted after the word write to the EEPROM address space or after writing a command to the ECMD register and before the command is launched. Writing a 0 to the CBEIF flag in this way will set the ACCERR flag. A summary of the launching of a program operation is shown in Figure 3-18. For other operations, the user writes the appropriate command to the ECMD register.
MC9S12HZ256 Data Sheet, Rev. 2.05 110 Freescale Semiconductor
Chapter 3 2 Kbyte EEPROM Module (EETS2KV1)
Read: Register ECLKDIV Clock Register Written Check
Bit EDIVLD set? yes
no
Write: Register ECLKDIV
1.
Write: Array Address and Program Data Write: Register ECMD Program Command 0x20 Write: Register ESTAT Clear bit CBEIF 0x80 Read: Register ESTAT Bit PVIOL Set? no NOTE: command sequence aborted by writing 0x00 to ESTAT register. NOTE: command sequence aborted by writing 0x00 to ESTAT register.
2.
3.
Protection Violation Check
yes Write: Register ESTAT Clear bit PVIOL 0x20
Access Error Check
Bit ACCERR Set? no
yes Write: Register ESTAT Clear bit ACCERR 0x10 yes yes Next Write? no
Address, Data, Command Buffer Empty Check
Bit CBEIF Set? no
Bit Polling for Command Completion Check
Bit CCIF Set? yes EXIT
no
Read: Register ESTAT
Figure 3-18. Example Program Command Flow
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 111
Chapter 3 2 Kbyte EEPROM Module (EETS2KV1)
3.4.1.3
Valid EEPROM Commands
Table 3-10 summarizes the valid EEPROM commands. Also shown are the effects of the commands on the EEPROM array.
Table 3-10. Valid EEPROM Commands
ECMD 0x05 0x20 0x40 0x41 0x60 Meaning Erase Verify Program Sector Erase Mass Erase Sector Modify Function on EEPROM Array Verify all memory bytes of the EEPROM array are erased. If the array is erased, the BLANK bit will set in the ESTAT register upon command completion. Program a word (two bytes). Erase two words (four bytes) of EEPROM array. Erase all of the EEPROM array. A mass erase of the full array is only possible when EPDIS and EPOPEN are set. Erase two words of EEPROM, re-program one word.
CAUTION An EEPROM word must be in an erased state before being programmed. Cumulative programming of bits within a word is not allowed. The sector modify command (0x60) is a two-step command which first erases a sector (2 words) of the EEPROM array and then re-programs one of the words in that sector. The EEPROM sector which is erased by the sector modify command is the sector containing the address of the aligned array write which starts the valid command sequence. That same address is re-programmed with the data which is written. By launching a sector modify command and then pipelining a program command it is possible to completely replace the contents of an EEPROM sector.
3.4.1.4
Illegal EEPROM Operations
The ACCERR flag will be set during the command write sequence if any of the following illegal operations are performed causing the command write sequence to immediately abort: 1. Writing to the EEPROM address space before initializing ECLKDIV. 2. Writing a misaligned word or a byte to the valid EEPROM address space. 3. Writing to the EEPROM address space while CBEIF is not set. 4. Writing a second word to the EEPROM address space before executing a program or erase command on the previously written word. 5. Writing to any EEPROM register other than ECMD after writing a word to the EEPROM address space. 6. Writing a second command to the ECMD register before executing the previously written command. 7. Writing an invalid command to the ECMD register in normal mode. 8. Writing to any EEPROM register other than ESTAT (to clear CBEIF) after writing to the command register (ECMD).
MC9S12HZ256 Data Sheet, Rev. 2.05 112 Freescale Semiconductor
Chapter 3 2 Kbyte EEPROM Module (EETS2KV1)
9. The part enters stop mode and a program or erase command is in progress. The command is aborted and any pending command is killed. 10. A 0 is written to the CBEIF bit in the ESTAT register. The ACCERR flag will not be set if any EEPROM register is read during the command sequence. If the EEPROM array is read during execution of an algorithm (i.e., CCIF bit in the ESTAT register is low), the read will return non-valid data and the ACCERR flag will not be set. When an ACCERR flag is set in the ESTAT register, the command state machine is locked. It is not possible to launch another command until the ACCERR flag is cleared. The PVIOL flag will be set during the command write sequence after the word write to the EEPROM address space and the command sequence will be aborted if any of the following illegal operations are performed. 1. Writing a EEPROM address to program in a protected area of the EEPROM. 2. Writing a EEPROM address to erase in a protected area of the EEPROM. 3. Writing the mass erase command to ECMD while any protection is enabled. When the PVIOL flag is set in the ESTAT register the command state machine is locked. It is not possible to launch another command until the PVIOL flag is cleared.
3.5
3.5.1
Operating Modes
Wait Mode
If an EEPROM command is active (CCIF = 0) when the MCU enters wait mode, that command and any pending command will be completed. The EETS2K module can recover the MCU from wait mode if the interrupts are enabled (see Section 3.7, "Interrupts").
3.5.2
Stop Mode
If a command is active (CCIF = 0) when the MCU enters stop mode, the operation will be aborted and if the operation is program, erase, or sector modify, the data being programmed or erased may be corrupted and the CCIF and ACCERR flags will be set. If active, the high voltage circuitry to the EEPROM array will be switched off when entering stop mode. Upon exit from stop mode, the CBEIF flag is set and any pending command will not be launched. The ACCERR flag must be cleared before starting a new command write sequence. NOTE As active commands are immediately aborted when the MCU enters stop mode, it is strongly recommended that the user does not use the STOP instruction during program, erase, or sector modify operations.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 113
Chapter 3 2 Kbyte EEPROM Module (EETS2KV1)
3.5.3
Background Debug Mode
In background debug mode (BDM), the EPROT register is writable. If the chip is unsecured then all EEPROM commands listed in Table 3-10 can be executed. If the chip is secured in special single-chip mode, then the only possible command to execute is mass erase.
3.6
Resets
If a reset occurs while any EEPROM command is in progress, that command will be immediately aborted. The state of the word being programmed or the sector / block being erased is not guaranteed.
3.7
Interrupts
The EEPROM module can generate an interrupt when all EEPROM commands are completed or the address, data, and command buffers are empty.
Table 3-11. EEPROM Interrupt Sources
Interrupt Source EEPROM address, data and command buffers empty All commands are completed on EEPROM Interrupt Flag CBEIF (ESTAT register) CCIF (ESTAT register) Local Enable CBEIE CCIE Global (CCR) Mask I Bit I Bit
NOTE Vector addresses and their relative interrupt priority are determined at the MCU level. For a detailed description of the register bits, refer to Section 3.3.2.4, "EEPROM Configuration Register (ECNFG)" and Section 3.3.2.6, "EEPROM Status Register (ESTAT)".
MC9S12HZ256 Data Sheet, Rev. 2.05 114 Freescale Semiconductor
Chapter 4 Port Integration Module (PIM9HZ256V2)
4.1 lntroduction
The port integration module establishes the interface between the peripheral modules and the I/O pins for for ports AD, L, M, P, T, U and V. This section covers: * Port A, B, E, and K and the BKGD pin, which are shared between the core logic (including multiplexed bus interface) and the LCD driver * Port AD associated with ATD module (channels 7 through 0) and keyboard wake-up interrupts * Port L connected to the LCD driver and ATD (channels 15 through 8) modules * Port M connected to 2 CAN modules * Port P connected to 1 SCI, 1 IIC and PWM modules * Port S connected to 1 SCI and 1 SPI modules * Port T connected to the timer module (TIM) and the LCD driver * Port U and V associated with PWM motor control and stepper stall detect modules Each I/O pin can be configured by several registers: input/output selection, drive strength reduction, enable and select of pull resistors, wired-or mode selection, interrupt enable, and/or status flags. NOTE Ports A, B, E and K, and the BKGD pin are shared between core logic (including multiplexed bus interface) and the LCD driver. Refer to the MEBI block description chapter for details on these ports.
4.1.1
Features
A standard port has the following minimum features: * Input/output selection * 5-V output drive with two selectable drive strength (or slew rates) * 5-V digital and analog input * Input with selectable pull-up or pull-down device Optional features: * * Open drain for wired-OR connections Interrupt input with glitch filtering
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 115
Chapter 4 Port Integration Module (PIM9HZ256V2)
4.1.2
Block Diagram
Figure 4-1 is a block diagram of the PIM9HZ256.
Port Integration Module
BKGD PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 PK0 PK1 PK2 PK3 PK7 PL0 PL1 PL2 PL3 PL4 PL5 PL6 PL7 PT0 PT1 PT2 PT3 PT4 PT5 PT6 PT7 PP0 PP1 PP2 PP3 PP4 PP5
BKGD
BKGD/MODC/TAGHI FP0 FP1 FP2 FP3 FP4 FP5 FP6 FP7 FP8 FP9 FP10 FP11 FP12 FP13 FP14 FP15 ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 XIRQ IRQ R/W LSTRB/TAGLO ECLK IPIPE0/MODA IPIPE1/MODB NOACC/XCLKS XADDR14 XADDR15 XADDR16 XADDR17 ECS/ROMONE AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 IOC0 IOC1 IOC2 IOC3 IOC4 IOC5 IOC6 IOC7 TXD RXD TXD SPI/MISO SPO/MOSI SCK SS RXCAN TXCAN RXCAN TXCAN M0C0M M0C0P M0C1M M0C1P M1C0M M1C0P M1C1M M1C1P M2C0M M2C0P M2C1M M2C1P M3C0M M3C0P M3C1M M3C1P AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 KWAD0 KWAD1 KWAD2 KWAD3 KWAD4 KWAD5 KWAD6 KWAD7 PS0 PS1 PS4 PS5 PS6 PS7 PM2 PM3 PM4 PM5 PU0 PU1 PU2 PU3 PU4 PU5 PU6 PU7 PV0 PV1 PV2 PV3 PV4 PV5 PV6 PV7 PAD0 PAD1 PAD2 PAD3 PAD4 PAD5 PAD6 PAD7
Port B
SPI
LCD Driver
CAN0 CAN1 SSD0
M0COSM M0COSP M0SINM M0SINP M1COSM M1COSP M1SINM M1SINP
Port A
Core
PWM Motor Controller
Port E
FP20 FP21
SSD1
SSD2
M2COSM M2COSP M2SINM M2SINP
Port T
PWM0 PWM1 PWM2 PWM3 PWM4 PWM5
Port P
PWM
RXD SDA SCL
Figure 4-1. PIM9HZ256 Block Diagram
MC9S12HZ256 Data Sheet, Rev. 2.05 116 Freescale Semiconductor
Timer (TIM)
FP22 BP0 BP1 BP2 BP3 FP23 FP16 FP17 FP18 FP19 FP28 FP29 FP30 FP31 FP24 FP25 FP26 FP27
Port K
SSD3
M3COSM M3COSP M3SINM M3SINP
ATD
SCI1 IIC
Port AD
Port L
Port V
Port U
Port M
Port S
SCI0
Chapter 4 Port Integration Module (PIM9HZ256V2)
4.2
External Signal Description
This section lists and describes the signals that connect off chip. Table 4-1 shows all the pins and their functions that are controlled by the PIM9HZ256. The order in which the pin functions are listed represents the functions priority (top - highest priority, bottom - lowest priority).
Table 4-1. Detailed Signal Descriptions (Sheet 1 of 6)
Port -- Pin Name Pin Function Description Refer to the MEBI block description chapter Refer to the BDM block description chapter Refer to the MEBI block description chapter Refer to the MEBI block description chapter LCD driver interface General-purpose I/O Refer to the MEBI block description chapter LCD driver interface General-purpose I/O Refer to the MEBI block description chapter LCD driver interface General-purpose I/O Refer to the MEBI block description chapter LCD driver interface General-purpose I/O Refer to the MEBI block description chapter LCD driver interface General-purpose I/O Refer to OSC block description chapter Refer to the MEBI block description chapter LCD driver interface General-purpose I/O Refer to the MEBI block description chapter General-purpose I/O Refer to the MEBI block description chapter General-purpose I/O Refer to the MEBI block description chapter General-purpose I/O Refer to the MEBI block description chapter LCD driver interface General-purpose I/O LCD driver interface Refer to the MEBI block description chapter Refer to the MEBI block description chapter General-purpose I/O Refer to the MEBI block description chapter General-purpose I/O Pin Function after Reset Refer to the MEBI block description chapter Refer to the MEBI block description chapter
Port K
Port E
BKGD MODC BKGD TAGHI PK7 ECS/ROMONE FP23 GPIO PK3 XADDR17 BP3 GPIO PK2 XADDR16 BP2 GPIO PK1 XADDR15 BP1 GPIO PK0 XADDR14 BP0 GPIO PE7 XCLKS NOACC FP22 GPIO PE6 IPIPE1/MODB GPIO PE5 IPIPE0/MODA GPIO PE4 ECLK GPIO PE3 LSTRB/TAGLO FP21 GPIO PE2 FP20 R/W/GPIO PE1 IRQ GPIO PE0 XIRQ GPIO
Refer to the MEBI block description chapter
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 117
Chapter 4 Port Integration Module (PIM9HZ256V2)
Table 4-1. Detailed Signal Descriptions (Sheet 2 of 6)
Port Port A Pin Name PA7 Pin Function ADDR15/DATA15 FP15 GPIO ADDR14/DATA14 FP14 GPIO ADDR13/DATA13 FP13 GPIO ADDR12/DATA12 FP12 GPIO ADDR11/DATA11 FP11 GPIO ADDR10/DATA10 FP10 GPIO ADDR9/DATA9 FP9 GPIO ADDR8/DATA8 FP8 GPIO ADDR7/DATA7 FP7 GPIO ADDR6/DATA6 FP6 GPIO ADDR5/DATA5 FP5 GPIO ADDR4/DATA4 FP4 GPIO ADDR3/DATA3 FP3 GPIO ADDR2/DATA2 FP2 GPIO ADDR1/DATA1 FP1 GPIO ADDR0/DATA0 FP0 GPIO Description Refer to the MEBI block description chapter LCD driver interface General-purpose I/O Refer to the MEBI block description chapter LCD driver interface General-purpose I/O Refer to the MEBI block description chapter LCD driver interface General-purpose I/O Refer to the MEBI block description chapter LCD driver interface General-purpose I/O Refer to the MEBI block description chapter LCD driver interface General-purpose I/O Refer to the MEBI block description chapter LCD driver interface General-purpose I/O Refer to the MEBI block description chapter LCD driver interface General-purpose I/O Refer to the MEBI block description chapter LCD driver interface General-purpose I/O Refer to the MEBI block description chapter LCD driver interface General-purpose I/O Refer to the MEBI block description chapter LCD driver interface General-purpose I/O Refer to the MEBI block description chapter LCD driver interface General-purpose I/O Refer to the MEBI block description chapter LCD driver interface General-purpose I/O Refer to the MEBI block description chapter LCD driver interface General-purpose I/O Refer to the MEBI block description chapter LCD driver interface General-purpose I/O Refer to the MEBI block description chapter LCD driver interface General-purpose I/O Refer to the MEBI block description chapter LCD driver interface General-purpose I/O Pin Function after Reset Refer to the MEBI block description chapter
PA6
PA5
PA4
PA3
PA2
PA1
PA0
Port B
PB7
Refer to the MEBI block description chapter
PB6
PB5
PB4
PB3
PB2
PB1
PB0
MC9S12HZ256 Data Sheet, Rev. 2.05 118 Freescale Semiconductor
Chapter 4 Port Integration Module (PIM9HZ256V2)
Table 4-1. Detailed Signal Descriptions (Sheet 3 of 6)
Port Port AD Pin Name PAD7 Pin Function AN7 KWAD7 GPIO AN6 KWAD6 GPIO AN5 KWAD5 GPIO AN4 KWAD4 GPIO AN3 KWAD3 GPIO AN2 KWAD2 GPIO AN1 KWAD1 GPIO AN0 KWAD0 GPIO FP31 AN15 GPIO FP30 AN14 GPIO FP29 AN13 GPIO FP28 AN12 GPIO FP19 AN11 GPIO FP18 AN10 GPIO FP17 AN9 GPIO FP16 AN8 GPIO Description Analog-to-digital converter input channel 7 Keyboard wake-up interrupt 7 General-purpose I/O Analog-to-digital converter input channel 6 Keyboard wake-up interrupt 6 General-purpose I/O Analog-to-digital converter input channel 5 Keyboard wake-up interrupt 5 General-purpose I/O Analog-to-digital converter input channel 4 Keyboard wake-up interrupt 4 General-purpose I/O Analog-to-digital converter input channel 3 Keyboard wake-up interrupt 3 General-purpose I/O Analog-to-digital converter input channel 2 Keyboard wake-up interrupt 2 General-purpose I/O Analog-to-digital converter input channel 1 Keyboard wake-up interrupt 1 General-purpose I/O Analog-to-digital converter input channel 0 Keyboard wake-up interrupt 0 General-purpose I/O LCD driver interface Analog-to-digital converter input channel 15 General-purpose I/O LCD driver interface Analog-to-digital converter input channel 14 General-purpose I/O LCD driver interface Analog-to-digital converter input channel 13 General-purpose I/O LCD driver interface Analog-to-digital converter input channel 12 General-purpose I/O LCD driver interface Analog-to-digital converter input channel 11 General-purpose I/O LCD driver interface Analog-to-digital converter input channel 10 General-purpose I/O LCD driver interface Analog-to-digital converter input channel 9 General-purpose I/O LCD driver interface Analog-to-digital converter input channel 8 General-purpose I/O Pin Function after Reset GPIO
PAD6
PAD5
PAD4
PAD3
PAD2
PAD1
PAD0
Port L
PL7
GPIO
PL6
PL5
PL4
PL3
PL2
PL1
PL0
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 119
Chapter 4 Port Integration Module (PIM9HZ256V2)
Table 4-1. Detailed Signal Descriptions (Sheet 4 of 6)
Port Port M Pin Name PM5 PM4 PM3 PM2 Port P PP5 Pin Function TXCAN1 GPIO RXCAN1 GPIO TXCAN0 GPIO RXCAN0 GPIO PWM5 SCL GPIO PWM4 SDA GPIO PWM3 GPIO PWM2 RXD1 GPIO PWM1 GPIO PWM0 TXD1 GPIO SS GPIO SCK GPIO MOSI GPIO MISO GPIO TXD0 GPIO RXD0 GPIO Description MSCAN1 transmit pin General-purpose I/O MSCAN1 receive pin General-purpose I/O MSCAN0 transmit pin General-purpose I/O MSCAN0 receive pin General-purpose I/O Pulse-width modulator channel 5 Inter-integrated circuit serial clock line General-purpose I/O Pulse-width modulator channel 4 Inter-integrated circuit serial data line General-purpose I/O Pulse-width modulator channel 3 General-purpose I/O Pulse-width modulator channel 2 Serial communication interface 1 receive pin General-purpose I/O Pulse-width modulator channel 1 General-purpose I/O Pulse-width modulator channel 0 Serial communication interface 1 transmit pin General-purpose I/O Serial peripheral interface slave select input/output in master mode, input in slave mode General-purpose I/O Serial peripheral interface serial clock pin General-purpose I/O Serial peripheral interface master out/slave in pin General-purpose I/O Serial peripheral interface master in/slave out pin General-purpose I/O Serial communication interface 0 transmit pin General-purpose I/O Serial communication interface 0 receive pin General-purpose I/O Pin Function after Reset GPIO
GPIO
PP4
PP3 PP2
PP1 PP0
Port S
PS7
GPIO
PS6 PS5 PS4 PS1 PS0
MC9S12HZ256 Data Sheet, Rev. 2.05 120 Freescale Semiconductor
Chapter 4 Port Integration Module (PIM9HZ256V2)
Table 4-1. Detailed Signal Descriptions (Sheet 5 of 6)
Port Port T Pin Name PT7 PT6 PT5 PT4 PT3 Pin Function IOC7 GPIO IOC6 GPIO IOC5 GPIO IOC4 GPIO FP27 IOC3 GPIO FP26 IOC2 GPIO FP25 IOC1 GPIO FP24 IOC0 GPIO M1SINP M1C1P GPIO M1SINM M1C1M GPIO M1COSP M1C0P GPIO M1COSM M1C0M GPIO M0SINP M0C1P GPIO M0SINM M0C1M GPIO M0COSP M0C0P GPIO M0COSM M0C0M GPIO Description Timer channel 7 General-purpose I/O Timer channel 6 General-purpose I/O Timer channel 5 General-purpose I/O Timer channel 4 General-purpose I/O LCD driver interface Timer channel 3 General-purpose I/O LCD driver interface Timer channel 2 General-purpose I/O LCD driver interface Timer channel 1 General-purpose I/O LCD driver interface Timer channel 0 General-purpose I/O SSD1 Sine+ Node PWM motor controller channel 3 General-purpose I/O SSD1 Sine- Node PWM motor controller channel 3 General-purpose I/O SSD1 Cosine+ Node PWM motor controller channel 2 General-purpose I/O SSD1 Cosine- Node PWM motor controller channel 2 General-purpose I/O SSD0 Sine+ Node PWM motor controller channel 1 General-purpose I/O SSD0 Sine- Node PWM motor controller channel 1 General-purpose I/O SSD0 Cosine+ Node PWM motor controller channel 0 General-purpose I/O SSD0 Cosine- Node PWM motor controller channel 0 General-purpose I/O Pin Function after Reset GPIO
PT2
PT1
PT0
Port U
PU7
GPIO
PU6
PU5
PU4
PU3
PU2
PU1
PU0
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 121
Chapter 4 Port Integration Module (PIM9HZ256V2)
Table 4-1. Detailed Signal Descriptions (Sheet 6 of 6)
Port Port V Pin Name PV7 Pin Function M3SINP M3C1P GPIO M3SINM M3C1M GPIO M3COSP M3C0P GPIO M3COSM M3C0M GPIO M2SINP M2C1P GPIO M2SINM M2C1M GPIO M2COSP M2C0P GPIO M2COSM M2C0M GPIO Description SSD3 sine+ node PWM motor controller channel 7 General-purpose I/O SSD3 sine- node PWM motor controller channel 7 General-purpose I/O SSD3 cosine+ node PWM motor controller channel 6 General-purpose I/O SSD3 cosine- node PWM motor controller channel 6 General-purpose I/O SSD2 sine+ node PWM motor controller channel 5 General-purpose I/O SSD2 sine- node PWM motor controller channel 5 General-purpose I/O SSD2 cosine+ node PWM motor controller channel 4 General-purpose I/O SSD2 cosine- node PWM motor controller channel 4 General-purpose I/O Pin Function after Reset GPIO
PV6
PV5
PV4
PV3
PV2
PV1
PV0
MC9S12HZ256 Data Sheet, Rev. 2.05 122 Freescale Semiconductor
Chapter 4 Port Integration Module (PIM9HZ256V2)
4.3
Memory Map and Register Definition
This section provides a detailed description of all registers. Table 4-2 is a standard memory map of port integration module.
Table 4-2. PIM9HZ256 Memory Map
Address Offset 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 - 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C 0x000D 0x000E 0x000F 0x0010 0x0011 0x0012 0x0013 0x0014 0x0015 0x0016 0x0017 0x0018 0x0019 0x001A 0x001B 0x001C 0x001D 0x001E 0x001F - 0x002F Port T I/O Register (PTT) Port T Input Register (PTIT) Port T Data Direction Register (DDRT) Port T Reduced Drive Register (RDRT) Port T Pull Device Enable Register (PERT) Port T Polarity Select Register (PPST) Reserved Port S I/O Register (PTS) Port S Input Register (PTIS) Port S Data Direction Register (DDRS) Port S Reduced Drive Register (RDRS) Port S Pull Device Enable Register (PERS) Port S Polarity Select Register (PPSS) Port S Wired-OR Mode Register (WOMS) Reserved Port M I/O Register (PTM) Port M Input Register (PTIM) Port M Data Direction Register (DDRM) Port M Reduced Drive Register (RDRM) Port M Pull Device Enable Register (PERM) Port M Polarity Select Register (PPSM) Port M Wired-OR Mode Register (WOMM) Reserved Port P I/O Register (PTP) Port P Input Register (PTIP) Port P Data Direction Register (DDRP) Port P Reduced Drive Register (RDRP) Port P Pull Device Enable Register (PERP) Port P Polarity Select Register (PPSP) Port P Wired-OR Mode Register (WOMP) Reserved Use Access R/W R R/W R/W R/W R/W -- R/W R R/W R/W R/W R/W R/W -- R/W R R/W R/W R/W R/W R/W -- R/W R R/W R/W R/W R/W R/W --
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 123
Chapter 4 Port Integration Module (PIM9HZ256V2)
Table 4-2. PIM9HZ256 Memory Map (continued)
Address Offset 0x0030 0x0031 0x0032 0x0033 0x0034 0x0035 0x0036 - 0x0037 0x0038 0x0039 0x003A 0x003B 0x003C 0x003D 0x003E - 0x003F 0x0040 0x0041 0x0042 0x0043 0x0044 0x0045 0x0046 - 0x0050 0x0051 0x0052 0x0053 0x0054 0x0055 0x0056 0x0057 0x0058 0x0059 0x005A 0x005B 0x005C 0x005D 0x005E 0x005F 0x0060 - 0x007F Port L I/O Register (PTL) Port L Input Register (PTIL) Port L Data Direction Register (DDRL) Port L Reduced Drive Register (RDRL) Port L Pull Device Enable Register (PERL) Port L Polarity Select Register (PPSL) Reserved Port U I/O Register (PTU) Port U Input Register (PTIU) Port U Data Direction Register (DDRU) Port U Slew Rate Register (SRRU) Port U Pull Device Enable Register (PERU) Port U Polarity Select Register (PPSU) Reserved Port V I/O Register (PTV) Port V Input Register (PTIV) Port V Data Direction Register (DDRV) Port V Slew Rate Register (SRRV) Port V Pull Device Enable Register (PERV) Port V Polarity Select Register (PPSV) Reserved Port AD I/O Register (PTAD) Reserved Port AD Input Register (PTIAD) Reserved Port AD Data Direction Register (DDRAD) Reserved Port AD Reduced Drive Register (RDRAD) Reserved Port AD Pull Device Enable Register (PERAD) Reserved Port AD Polarity Select Register (PPSAD) Reserved Port AD Interrupt Enable Register (PIEAD) Reserved Port AD Interrupt Flag Register (PIFAD) Reserved Use Access R/W R R/W R/W R/W R/W -- R/W R R/W R/W R/W R/W -- R/W R R/W R/W R/W R/W -- R/W -- R -- R/W -- R/W -- R/W -- R/W -- R/W -- R/W --
MC9S12HZ256 Data Sheet, Rev. 2.05 124 Freescale Semiconductor
Chapter 4 Port Integration Module (PIM9HZ256V2)
4.3.1
Port AD
Port AD is associated with the analog-to-digital converter (ATD) and keyboard wake-up (KWU) interrupts. Each pin is assigned to these modules according to the following priority: ATD > KWU > general-purpose I/O. For the pins of port AD to be used as inputs, the corresponding bits of the ATDDIEN1 register in the ATD module must be set to 1 (digital input buffer is enabled). The ATDDIEN1 register does not affect the port AD pins when they are configured as outputs. Refer to the ATD block description chapter for information on the ATDDIEN1 register. During reset, port AD pins are configured as high-impedance analog inputs (digital input buffer is disabled).
4.3.1.1
Port AD I/O Register (PTAD)
7 6 5 4 3 2 1 0
R PTAD7 W KWU: ATD: Reset KWAD7 AN7 0 KWAD6 AN6 0 KWAD5 AN55 0 KWAD4 AN4 0 KWAD3 AN3 0 KWAD2 AN2 0 KWAD1 AN1 0 KWAD0 AN0 0 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0
Figure 4-2. Port AD I/O Register (PTAD)
Read: Anytime. Write: Anytime. If the data direction bit of the associated I/O pin (DDRADx) is set to 1 (output), a write to the corresponding I/O Register bit sets the value to be driven to the Port AD pin. If the data direction bit of the associated I/O pin (DDRADx) is set to 0 (input), a write to the corresponding I/O Register bit takes place but has no effect on the Port AD pin. If the associated data direction bit (DDRADx) is set to 1 (output), a read returns the value of the I/O register bit. If the associated data direction bit (DDRADx) is set to 0 (input) and the associated ATDDIEN1 bits is set to 0 (digital input buffer is disabled), the associated I/O register bit (PTADx) reads "1". If the associated data direction bit (DDRADx) is set to 0 (input) and the associated ATDDIEN1 bits is set to 1 (digital input buffer is enabled), a read returns the value of the pin.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 125
Chapter 4 Port Integration Module (PIM9HZ256V2)
4.3.1.2
Port AD Input Register (PTIAD)
7 6 5 4 3 2 1 0
R W Reset
PTIAD7
PTIAD6
PTIAD5
PTIAD4
PTIAD3
PTIAD2
PTIAD1
PTIAD0
1
1
1
1
1
1
1
1
= Reserved or Unimplemented
Figure 4-3. Port AD Input Register (PTIAD)
Read: Anytime. Write: Never; writes to these registers have no effect. If the ATDDIEN1 bit of the associated I/O pin is set to 0 (digital input buffer is disabled), a read returns a 1. If the ATDDIEN1 bit of the associated I/O pin is set to 1 (digital input buffer is enabled), a read returns the status of the associated pin.
4.3.1.3
Port AD Data Direction Register (DDRAD)
7 6 5 4 3 2 1 0
R DDRAD7 W Reset 0 0 0 0 0 0 0 0 DDRAD6 DDRAD5 DDRAD4 DDRAD3 DDRAD2 DDRAD1 DDRAD0
Figure 4-4. Port AD Data Direction Register (DDRAD)
Read: Anytime. Write: Anytime. This register configures port pins PAD[7:0] as either input or output. If a data direction bit is 0 (pin configured as input), then a read value on PTADx depends on the associated ATDDIEN1 bit. If the associated ATDDIEN1 bit is set to 1 (digital input buffer is enabled), a read on PTADx returns the value on port AD pin. If the associated ATDDIEN1 bit is set to 0 (digital input buffer is disabled), a read on PTADx returns a 1.
Table 4-3. DDRAD Field Descriptions
Field 7:0 Data Direction Port AD DDRAD[7:0] 0 Associated pin is configured as input. 1 Associated pin is configured as output. Description
MC9S12HZ256 Data Sheet, Rev. 2.05 126 Freescale Semiconductor
Chapter 4 Port Integration Module (PIM9HZ256V2)
4.3.1.4
Port AD Reduced Drive Register (RDRAD)
7 6 5 4 3 2 1 0
R RDRAD7 W Reset 0 0 0 0 0 0 0 0 RDRAD6 RDRAD5 RDRAD4 RDRAD3 RDRAD2 RDRAD1 RDRAD0
Figure 4-5. Port AD Reduced Drive Register (RDRAD)
Read: Anytime. Write: Anytime. This register configures the drive strength of configured output pins as either full or reduced. If a pin is configured as input, the corresponding Reduced Drive Register bit has no effect.
Table 4-4. RDRAD Field Descriptions
Field Description
7:0 Reduced Drive Port AD RDRAD[7:0] 0 Full drive strength at output. 1 Associated pin drives at about 1/3 of the full drive strength.
4.3.1.5
Port AD Pull Device Enable Register (PERAD)
7 6 5 4 3 2 1 0
R PERAD7 W Reset 0 0 0 0 0 0 0 0 PERAD6 PERAD5 PERAD4 PERAD3 PERAD2 PERAD1 PERAD0
Figure 4-6. Port AD Pull Device Enable Register (PERAD)
Read: Anytime. Write: Anytime. This register configures whether a pull-up or a pull-down device is activated on configured input pins. If a pin is configured as output, the corresponding Pull Device Enable Register bit has no effect.
Table 4-5. PERAD Field Descriptions
Field 7:0 Pull Device Enable Port AD PERAD[7:0] 0 Pull-up or pull-down device is disabled. 1 Pull-up or pull-down device is enabled. Description
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 127
Chapter 4 Port Integration Module (PIM9HZ256V2)
4.3.1.6
Port AD Polarity Select Register (PPSAD)
7 6 5 4 3 2 1 0
R PPSAD7 W Reset 0 0 0 0 0 0 0 0 PPSAD6 PPSAD5 PPSAD4 PPSAD3 PPSAD2 PPSAD1 PPSAD0
Figure 4-7. Port AD Polarity Select Register (PPSAD)
Read: Anytime. Write: Anytime. The Port AD Polarity Select Register serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting a pull-up or pull-down device if enabled (PERADx = 1). The Port AD Polarity Select Register is effective only when the corresponding Data Direction Register bit is set to 0 (input). In pull-down mode (PPSADx = 1), a rising edge on a port AD pin sets the corresponding PIFADx bit. In pull-up mode (PPSADx = 0), a falling edge on a port AD pin sets the corresponding PIFADx bit.
Table 4-6. PPSAD Field Descriptions
Field Description
7:0 Polarity Select Port AD PPSAD[7:0] 0 A pull-up device is connected to the associated port AD pin, and detects falling edge for interrupt generation. 1 A pull-down device is connected to the associated port AD pin, and detects rising edge for interrupt generation.
4.3.1.7
Port AD Interrupt Enable Register (PIEAD)
7 6 5 4 3 2 1 0
R PIEAD7 W Reset 0 0 0 0 0 0 0 0 PIEAD6 PIEAD5 PIEAD4 PIEAD3 PIEAD2 PIEAD1 PIEAD0
Figure 4-8. Port AD Interrupt Enable Register (PIEAD)
Read: Anytime. Write: Anytime. This register disables or enables on a per pin basis the edge sensitive external interrupt associated with port AD.
Table 4-7. PIEAD Field Descriptions
Field 7:0 PIEAD[7:0] Interrupt Enable Port AD 0 Interrupt is disabled (interrupt flag masked). 1 Interrupt is enabled. Description
MC9S12HZ256 Data Sheet, Rev. 2.05 128 Freescale Semiconductor
Chapter 4 Port Integration Module (PIM9HZ256V2)
4.3.1.8
Port AD Interrupt Flag Register (PIFAD)
7 6 5 4 3 2 1 0
R PIFAD7 W Reset 0 0 0 0 0 0 0 0 PIFAD6 PIFAD5 PIFAD4 PIFAD3 PIFAD2 PIFAD1 PIFAD0
Figure 4-9. Port AD Interrupt Flag Register (PIFAD)
Read: Anytime. Write: Anytime. Each flag is set by an active edge on the associated input pin. The active edge could be rising or falling based on the state of the corresponding PPSADx bit. To clear each flag, write "1" to the corresponding PIFADx bit. Writing a "0" has no effect. NOTE If the ATDDIEN1 bit of the associated pin is set to 0 (digital input buffer is disabled), active edges can not be detected.
Table 4-8. PIFAD Field Descriptions
Field 7:0 PIFAD[7:0] Description Interrupt Flags Port AD 0 No active edge pending. Writing a "0" has no effect. 1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set). Writing a "1" clears the associated flag.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 129
Chapter 4 Port Integration Module (PIM9HZ256V2)
4.3.2
Port L
Port L is associated with the analog-to-digital converter (ATD) and the liquid crystal display (LCD) driver. If the ATD module is enabled, the AN[15:8] inputs of ATD module are available on port L pins PL[7:0]. If the corresponding LCD frontplane drivers are enabled, the FP[31:29] and FP[19:16] outputs of LCD module are available on port L pins PL[7:0] and the general purpose I/Os are disabled. For the pins of port L to be used as inputs, the corresponding LCD frontplane drivers must be disabled and the associated ATDDIEN0 register in the ATD module must be set to 1 (digital input buffer is enabled). The ATDDIEN0 register does not affect the port L pins when they are configured as outputs. Refer to the LCD block description chapter for information on enabling and disabling the LCD and its frontplane drivers. Refer to the ATD block description chapter for information on the ATDDIEN0 register. During reset, port L pins are configured as inputs with pull down.
4.3.2.1
Port L I/O Register (PTL)
7 6 5 4 3 2 1 0
R PTL7 W ATD: LCD: Reset AN15 1 0 AN14 1 0 AN13 1 0 AN12 1 0 AN11 1 0 AN10 1 0 AN9 1 0 AN8 1 0 PTL6 PTL5 PTL4 PTL3 PTL2 PTL1 PTL0
Figure 4-10. Port L I/O Register (PTL)
Read: Anytime. Write: Anytime. If the data direction bit of the associated I/O pin (DDRLx) is set to 1 (output), a write to the corresponding I/O Register bit sets the value to be driven to the Port L pin. If the data direction bit of the associated I/O pin (DDRLx) is set to 0 (input), a write to the corresponding I/O Register bit takes place but has no effect on the Port L pin. If the associated data direction bit (DDRLx) is set to 1 (output), a read returns the value of the I/O register bit. If the associated data direction bit (DDRLx) is set to 0 (input) and the associated ATDDIEN0 bits is set to 0 (digital input buffer is disabled), the associated I/O register bit (PTLx) reads "1". If the associated data direction bit (DDRLx) is set to 0 (input), the associated ATDDIEN0 bit is set to 1 (digital input buffer is enabled), and the LCD frontplane driver is enabled (and LCD module is enabled), the associated I/O register bit (PTLx) reads "1". If the associated data direction bit (DDRLx) is set to 0 (input), the associated ATDDIEN0 bit is set to 1 (digital input buffer is enabled), and the LCD frontplane driver is disabled (or LCD module is disabled), a read returns the value of the pin.
MC9S12HZ256 Data Sheet, Rev. 2.05 130 Freescale Semiconductor
Chapter 4 Port Integration Module (PIM9HZ256V2)
4.3.2.2
Port L Input Register (PTIL)
7 6 5 4 3 2 1 0
R W Reset
PTIL7
PTIL6
PTIL5
PTIL4
PTIL3
PTIL2
PTIL1
PTIL0
1
1
1
1
1
1
1
1
= Reserved or Unimplemented
Figure 4-11. Port L Input Register (PTIL)
Read: Anytime. Write: Never, writes to this register have no effect. If the LCD frontplane driver of an associated I/O pin is enabled (and LCD module is enabled) or the associated ATDDIEN0 bit is set to 0 (digital input buffer is disabled), a read returns a 1. If the LCD frontplane driver of an associated I/O pin is disabled (or LCD module is disabled) and the associated ATDDIEN0 bit is set to 1 (digital input buffer is enabled), a read returns the status of the associated pin.
4.3.2.3
Port L Data Direction Register (DDRL)
7 6 5 4 3 2 1 0
R DDRL7 W Reset 0 0 0 0 0 0 0 0 DDRL6 DDRL5 DDRL4 DDRL3 DDRL2 DDRL1 DDRL0
Figure 4-12. Port L Data Direction Register (DDRL)
Read: Anytime. Write: Anytime. This register configures port pins PL[7:0] as either input or output. If a LCD frontplane driver is enabled (and LCD module is enabled), it outputs an analog signal to the corresponding pin and the associated Data Direction Register bit has no effect. If a LCD frontplane driver is disabled (or LCD module is disabled), the corresponding Data Direction Register bit reverts to control the I/O direction of the associated pin.
Table 4-9. DDRL Field Descriptions
Field 7:0 DDRL[7:0] Data Direction Port L 0 Associated pin is configured as input. 1 Associated pin is configured as output. Description
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 131
Chapter 4 Port Integration Module (PIM9HZ256V2)
4.3.2.4
Port L Reduced Drive Register (RDRL)
7 6 5 4 3 2 1 0
R RDRL7 W Reset 0 0 0 0 0 0 0 0 RDRL6 RDRL5 RDRL4 RDRL3 RDRL2 RDRL1 RDRL0
Figure 4-13. Port L Reduced Drive Register (RDRL)
Read: Anytime. Write: Anytime. This register configures the drive strength of configured output pins as either full or reduced. If a pin is configured as input, the corresponding Reduced Drive Register bit has no effect.
Table 4-10. RDRL Field Descriptions
Field 7:0 RDRL[7:0] Description Reduced Drive Port L 0 Full drive strength at output. 1 Associated pin drives at about 1/3 of the full drive strength.
4.3.2.5
Port L Pull Device Enable Register (PERL)
7 6 5 4 3 2 1 0
R PERL7 W Reset 1 1 1 1 1 1 1 1 PERL6 PERL5 PERL4 PERL3 PERL2 PERL1 PERL0
Figure 4-14. Port L Pull Device Enable Register (PERL)
Read:Anytime. Write:Anytime. This register configures whether a pull-up or a pull-down device is activated on configured input pins. If a pin is configured as output, the corresponding Pull Device Enable Register bit has no effect.
Table 4-11. PERL Field Descriptions
Field 7:0 PERL[7:0] Pull Device Enable Port L 0 Pull-up or pull-down device is disabled. 1 Pull-up or pull-down device is enabled. Description
MC9S12HZ256 Data Sheet, Rev. 2.05 132 Freescale Semiconductor
Chapter 4 Port Integration Module (PIM9HZ256V2)
4.3.2.6
Port L Polarity Select Register (PPSL)
7 6 5 4 3 2 1 0
R PPSL7 W Reset 1 1 1 1 1 1 1 1 PPSL6 PPSL5 PPSL4 PPSL3 PPSL2 PPSL1 PPSL0
Figure 4-15. Port L Polarity Select Register (PPSL)
Read: Anytime. Write: Anytime. The Port L Polarity Select Register selects whether a pull-down or a pull-up device is connected to the pin. The Port L Polarity Select Register is effective only when the corresponding Data Direction Register bit is set to 0 (input) and the corresponding Pull Device Enable Register bit is set to 1.
Table 4-12. PPSL Field Descriptions
Field 7:0 PPSL[7:0] Description Pull Select Port L 0 A pull-up device is connected to the associated port L pin. 1 A pull-down device is connected to the associated port L pin.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 133
Chapter 4 Port Integration Module (PIM9HZ256V2)
4.3.3
Port M
Port M is associated with Freescale's scalable controller area network (CAN1 and CAN0) modules. Each pin is assigned to these modules according to the following priority: CAN1/CAN0 > general-purpose I/O. When the CAN1 module is enabled, PM[5:4] pins become TXCAN1 (transmitter) and RXCAN1 (receiver) pins for the CAN1 module. When the CAN0 module is enabled, PM[3:2] pins become TXCAN0 (transmitter) and RXCAN0 (receiver) pins for the CAN0 module. Refer to the MSCAN block description chapter for information on enabling and disabling the CAN module. During reset, port M pins are configured as high-impedance inputs.
4.3.3.1
Port M I/O Register (PTM)
7 6 5 4 3 2 1 0
R W CAN0/CAN1: Reset
0
0 PTM5 PTM4 PTM3 PTM2
0
0
TXCAN1
0 0 0
RXCAN1
0
TXCAN0
0
RXCAN0
0 0 0
= Reserved or Unimplemented
Figure 4-16. Port M I/O Register (PTM)
Read: Anytime. Write: Anytime. If the associated data direction bit (DDRMx) is set to 1 (output), a read returns the value of the I/O register bit. If the associated data direction bit (DDRMx) is set to 0 (input), a read returns the value of the pin.
4.3.3.2
Port M Input Register (PTIM)
7 6 5 4 3 2 1 0
R W Reset
0
0
PTIM5
PTIM4
PTIM3
PTIM2
0
0
0
0
u
u
u
u
0
0
= Reserved or Unimplemented
u = Unaffected by reset
Figure 4-17. Port M Input Register (PTIM)
Read: Anytime. Write: Never, writes to this register have no effect. This register always reads back the status of the associated pins.
MC9S12HZ256 Data Sheet, Rev. 2.05 134 Freescale Semiconductor
Chapter 4 Port Integration Module (PIM9HZ256V2)
4.3.3.3
Port M Data Direction Register (DDRM)
7 6 5 4 3 2 1 0
R W Reset
0
0 DDRM5 DDRM4 0 DDRM3 0 DDRM2 0
0
0
0
0
0
0
0
= Reserved or Unimplemented
Figure 4-18. Port M Data Direction Register (DDRM)
Read: Anytime. Write: Anytime. This register configures port pins PM[5:2] as either input or output. When a CAN module is enabled, the corresponding transmitter (TXCANx) pin becomes an output, the corresponding receiver (RXCANx) pin becomes an input, and the associated Data Direction Register bits have no effect. If a CAN module is disabled, the corresponding Data Direction Register bit reverts to control the I/O direction of the associated pin.
Table 4-13. DDRM Field Descriptions
Field 5:2 DDRM[5:2] Data Direction Port M 0 Associated pin is configured as input. 1 Associated pin is configured as output. Description
4.3.3.4
Port M Reduced Drive Register (RDRM)
7 6 5 4 3 2 1 0
R W Reset
0
0 RDRM5 RDRM4 0 RDRM3 0 RDRM2 0
0
0
0
0
0
0
0
= Reserved or Unimplemented
Figure 4-19. Port M Reduced Drive Register (RDRM)
Read: Anytime. Write: Anytime. This register configures the drive strength of configured output pins as either full or reduced. If a pin is configured as input, the corresponding Reduced Drive Register bit has no effect.
Table 4-14. RDRM Field Descriptions
Field 5:2 RDRM[5:2] Description Reduced Drive Port M 0 Full drive strength at output 1 Associated pin drives at about 1/3 of the full drive strength.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 135
Chapter 4 Port Integration Module (PIM9HZ256V2)
4.3.3.5
Port M Pull Device Enable Register (PERM)
7 6 5 4 3 2 1 0
R W Reset
0
0 PERM5 PERM4 0 PERM3 0 PERM2 0
0
0
0
0
0
0
0
= Reserved or Unimplemented
Figure 4-20. Port M Pull Device Enable Register (PERM)
Read: Anytime. Write: Anytime. This register configures whether a pull-up or a pull-down device is activated on configured input or wired-or output pins. If a pin is configured as push-pull output, the corresponding Pull Device Enable Register bit has no effect.
Table 4-15. PERM Field Descriptions
Field 5:2 PERM[5:2] Pull Device Enable Port M 0 Pull-up or pull-down device is disabled. 1 Pull-up or pull-down device is enabled. Description
4.3.3.6
Port M Polarity Select Register (PPSM)
7 6 5 4 3 2 1 0
R W Reset
0
0 PPSM5 PPSM4 0 PPSM3 0 PPSM2 0
0
0
0
0
0
0
0
= Reserved or Unimplemented
Figure 4-21. Port M Polarity Select Register (PPSM)
Read: Anytime. Write: Anytime. The Port M Polarity Select Register selects whether a pull-down or a pull-up device is connected to the pin. The Port M Polarity Select Register is effective only when the corresponding Data Direction Register bit is set to 0 (input) and the corresponding Pull Device Enable Register bit is set to 1. If a CAN module is enabled, a pull-up device can be activated on the receiver pin, and on the transmitter pin if the corresponding wired-OR mode bit is set. Pull-down devices can not be activated on CAN pins.
MC9S12HZ256 Data Sheet, Rev. 2.05 136 Freescale Semiconductor
Chapter 4 Port Integration Module (PIM9HZ256V2)
Table 4-16. PPSM Field Descriptions
Field 5:2 PPSM[5:2] Description Pull Select Port M 0 A pull-up device is connected to the associated port M pin. 1 A pull-down device is connected to the associated port M pin.
4.3.3.7
Port M Wired-OR Mode Register (WOMM)
7 6 5 4 3 2 1 0
R W Reset
0
0 WOMM5 WOMM4 0 WOMM3 0 WOMM2 0
0
0
0
0
0
0
0
= Reserved or Unimplemented
Figure 4-22. Port M Wired-OR Mode Register (WOMM)
Read: Anytime. Write: Anytime. This register selects whether a port M output is configured as push-pull or wired-or. When a Wired-OR Mode Register bit is set to 1, the corresponding output pin is driven active low only (open drain) and a high level is not driven. A Wired-OR Mode Register bit has no effect if the corresponding pin is configured as an input. These bits apply also to the CAN transmitter and allow a multipoint connection of several serial modules.
Table 4-17. WOMM Field Descriptions
Field 5:2 Wired-OR Mode Port M WOMM[5:2] 0 Output buffers operate as push-pull outputs. 1 Output buffers operate as open-drain outputs. Description
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 137
Chapter 4 Port Integration Module (PIM9HZ256V2)
4.3.4
Port P
Port P is associated with the Pulse Width Modulator (PWM), serial communication interface (SCI1) and Inter-IC bus (IIC) modules. Each pin is assigned to these modules according to the following priority: PWM > SCI1/IIC > general-purpose I/O. When a PWM channel is enabled, the corresponding pin becomes a PWM output with the exception of PP[5] which can be PWM input or output. Refer to the PWM block description chapter for information on enabling and disabling the PWM channels. When the IIC bus is enabled, the PP[5:4] pins become SCL and SDA respectively as long as the corresponding PWM channels are disabled. Refer to the IIC block description chapter for information on enabling and disabling the IIC bus. When the SCI1 receiver and transmitter are enabled, the PP[2] and PP[0] pins become RXD1 and TXD1 respectively as long as the corresponding PWM channels are disabled. Refer to the SCI block description chapter for information on enabling and disabling the SCI receiver and transmitter. During reset, port P pins are configured as high-impedance inputs.
4.3.4.1
Port P I/O Register (PTP)
7 6 5 4 3 2 1 0
R W SCI1/IIC: PWM: Reset
0
0 PTP5 PTP4 PTP3 PTP2 PTP1 PTP0
SCL PWM5
0 0 0
SDA PWM4
0
RXD1 PWM3
0
TXD1 PWM1
0
PWM2
0
PWM0
0
= Reserved or Unimplemented
Figure 4-23. Port P I/O Register (PTP)
Read: Anytime. Write: Anytime. If the associated data direction bit (DDRPx) is set to 1 (output), a read returns the value of the I/O register bit. If the associated data direction bit (DDRPx) is set to 0 (input), a read returns the value of the pin. The PWM function takes precedence over the general-purpose I/O function if the associated PWM channel is enabled. The PWM channels 4-0 are outputs if the respective channels are enabled. PWM channel 5 can be an output, or an input if the shutdown feature is enabled. The IIC function takes precedence over the general-purpose I/O function if the IIC bus is enabled and the corresponding PWM channels remain disabled. The SDA and SCL pins are bidirectional with outputs configured as open-drain. If enabled, the SCI1 transmitter takes precedence over the general-purpose I/O function, and the corresponding TXD1 pin is configured as an output. If enabled, the SCI1 receiver takes precedence over the general-purpose I/O function, and the corresponding RXD1 pin is configured as an input.
MC9S12HZ256 Data Sheet, Rev. 2.05 138 Freescale Semiconductor
Chapter 4 Port Integration Module (PIM9HZ256V2)
4.3.4.2
Port P Input Register (PTIP)
7 6 5 4 3 2 1 0
R W Reset
0
0
PTIP5
PTIP4
PTIP3
PTIP2
PTIP1
PTIP0
0
0
u
u
u
u
u
u
= Reserved or Unimplemented
u = Unaffected by reset
Figure 4-24. Port P I/O Register (PTP)
Read: Anytime. Write: Never, writes to this register have no effect. This register always reads back the status of the associated pins.
4.3.4.3
Port P Data Direction Register (DDRP)
7 6 5 4 3 2 1 0
R W Reset
0
0 DDRP5 DDRP4 0 DDRP3 0 DDRP2 0 DDRP1 0 DDRP0 0
0
0
0
= Reserved or Unimplemented
Figure 4-25. Port P Data Direction Register (DDRP)
Read: Anytime. Write: Anytime. This register configures port pins PP[5:0] as either input or output. If a PWM channel is enabled, the corresponding pin is forced to be an output and the associated Data Direction Register bit has no effect. Channel 5 can also force the corresponding pin to be an input if the shutdown feature is enabled. When the IIC bus is enabled, the PP[5:4] pins become the SCL and SDA bidirectional pins respectively as long as the corresponding PWM channels are disabled. The associated Data Direction Register bits have no effect. When the SCI1 transmitter is enabled, the PP[0] pin becomes the TXD1 output pin and the associated Data Direction Register bit has no effect. When the SCI1 receiver is enabled, the PP[2] pin becomes the RXD1 input pin and the associated Data Direction Register bit has no effect. If the PWM, IIC and SCI1 functions are disabled, the corresponding Data Direction Register bit reverts to control the I/O direction of the associated pin.
Table 4-18. DDRP Field Descriptions
Field 5:0 DDRP[5:0] Data Direction Port P 0 Associated pin is configured as input. 1 Associated pin is configured as output. Description
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 139
Chapter 4 Port Integration Module (PIM9HZ256V2)
4.3.4.4
Port P Reduced Drive Register (RDRP)
7 6 5 4 3 2 1 0
R W Reset
0
0 RDRP5 RDRP4 0 RDRP3 0 RDRP2 0 RDRP1 0 RDRP0 0
0
0
0
= Reserved or Unimplemented
Figure 4-26. Port P Reduced Drive Register (RDRP)
Read:Anytime. Write:Anytime. This register configures the drive strength of configured output pins as either full or reduced. If a pin is configured as input, the corresponding Reduced Drive Register bit has no effect.
Table 4-19. RDRP Field Descriptions
Field 5:0 RDRP[5:0] Description Reduced Drive Port P 0 Full drive strength at output. 1 Associated pin drives at about 1/3 of the full drive strength.
MC9S12HZ256 Data Sheet, Rev. 2.05 140 Freescale Semiconductor
Chapter 4 Port Integration Module (PIM9HZ256V2)
4.3.4.5
Port P Pull Device Enable Register (PERP)
7 6 5 4 3 2 1 0
R W Reset
0
0 PERP5 PERP4 0 PERP3 0 PERP2 0 PERP1 0 PERP0 0
0
0
0
= Reserved or Unimplemented
Figure 4-27. Port P Pull Device Enable Register (PERP)
Read: Anytime. Write: Anytime. This register configures whether a pull-up or a pull-down device is activated on configured input pins. If a pin is configured as output, the corresponding Pull Device Enable Register bit has no effect.
Table 4-20. PERP Field Descriptions
Field 5:0 PERP[5:0] Pull Device Enable Port P 0 Pull-up or pull-down device is disabled. 1 Pull-up or pull-down device is enabled. Description
4.3.4.6
Port P Polarity Select Register (PPSP)
7 6 5 4 3 2 1 0
R W Reset
0
0 PPSP5 PPSP4 0 PPSP3 0 PPSP2 0 PPSP1 0 PPSP0 0
0
0
0
= Reserved or Unimplemented
Figure 4-28. Port P Polarity Select Register (PPSP)
Read: Anytime. Write: Anytime. The Port P Polarity Select Register selects whether a pull-down or a pull-up device is connected to the pin. The Port P Polarity Select Register is effective only when the corresponding Data Direction Register bit is set to 0 (input) and the corresponding Pull Device Enable Register bit is set to 1.
Table 4-21. PPSP Field Descriptions
Field 5:0 PPSP[5:0] Description Polarity Select Port P 0 A pull-up device is connected to the associated port P pin. 1 A pull-down device is connected to the associated port P pin.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 141
Chapter 4 Port Integration Module (PIM9HZ256V2)
4.3.4.7
Port P Wired-OR Mode Register (WOMP)
7 6 5 4 3 2 1 0
R W Reset
0
0 WOMP5 WOMP4 0
0 WOMP2 0 0
0 WOMPO 0 0
0
0
0
= Reserved or Unimplemented
Figure 4-29. Port P Wired-OR Mode Register (WOMP)
Read: Anytime. Write: Anytime. This register selects whether a port P output is configured as push-pull or wired-or. When a Wired-OR Mode Register bit is set to 1, the corresponding output pin is driven active low only (open drain) and a high level is not driven. A Wired-OR Mode Register bit has no effect if the corresponding pin is configured as an input. If the IIC is enabled and the corresponding PWM channels are disabled, the PP[5:4] pins are configured as wired-or and the corresponding Wired-OR Mode Register bits have no effect.
Table 4-22. WOMP Field Descriptions
Field 5:4 Wired-OR Mode Port P WOMP[5:4] 0 Output buffers operate as push-pull outputs. 1 Output buffers operate as open-drain outputs. 2 WOMP2 0 WOMP0 Wired-OR Mode Port P 0 Output buffers operate as push-pull outputs. 1 Output buffers operate as open-drain outputs. Wired-OR Mode Port P 0 Output buffers operate as push-pull outputs. 1 Output buffers operate as open-drain outputs. Description
MC9S12HZ256 Data Sheet, Rev. 2.05 142 Freescale Semiconductor
Chapter 4 Port Integration Module (PIM9HZ256V2)
4.3.5
Port S
Port S is associated with the serial peripheral interface (SPI) and serial communication interface (SCI0). Each pin is assigned to these modules according to the following priority: SPI/SCI0 > general-purpose I/O. When the SPI is enabled, the PS[7:4] pins become SS, SCK, MOSI, and MISO respectively. Refer to the SPI block description chapter for information on enabling and disabling the SPI. When the SCI0 receiver and transmitter are enabled, the PS[1:0] pins become TXD0 and RXD0 respectively. Refer to the SCI block description chapter for information on enabling and disabling the SCI receiver and transmitter. During reset, port S pins are configured as high-impedance inputs.
4.3.5.1
Port S I/O Register (PTS)
7 6 5 4 3 2 1 0
R PTS7 W SPI/SCI: Reset PTS6 PTS5 PTS4
0
0 PTS1 PTS0
SS
0
SCK
0
MOSI
0
MISO
0 0 0
TXD0
0
RXD0
0
= Reserved or Unimplemented
Figure 4-30. Port S I/O Register (PTS)
Read: Anytime. Write: Anytime. If the associated data direction bit (DDRSx) is set to 1 (output), a read returns the value of the I/O register bit. If the associated data direction bit (DDRSx) is set to 0 (input), a read returns the value of the pin. The SPI function takes precedence over the general-purpose I/O function if the SPI is enabled. If enabled, the SCI0 transmitter takes precedence over the general-purpose I/O function, and the corresponding TXD0 pin is configured as an output. If enabled, the SCI0 receiver takes precedence over the general-purpose I/O function, and the corresponding RXD0 pin is configured as an input.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 143
Chapter 4 Port Integration Module (PIM9HZ256V2)
4.3.5.2
Port S Input Register (PTIS)
7 6 5 4 3 2 1 0
R W Reset
PTIS7
PTIS6
PTIS5
PTIS4
0
0
PTIS1
PTIS0
u
u
u
u
0
0
u
u
= Reserved or Unimplemented
u = Unaffected by reset
Figure 4-31. Port S Input Register (PTIS)
Read: Anytime. Write: Never, writes to this register have no effect. This register always reads back the status of the associated pins.
4.3.5.3
Port S Data Direction Register (DDRS)
7 6 5 4 3 2 1 0
R DDRS7 W Reset 0 0 0 0 DDRS6 DDRS5 DDRS4
0
0 DDRS1 DDRS0 0
0
0
0
= Reserved or Unimplemented
Figure 4-32. Port S Data Direction Register (DDRS)
Read: Anytime. Write: Anytime. This register configures port pins PS[7:4] and PS[2:0] as either input or output. When the SPI is enabled, the PS[7:4] pins become the SPI bidirectional pins. The associated Data Direction Register bits have no effect. When the SCI0 transmitter is enabled, the PS[1] pin becomes the TXD0 output pin and the associated Data Direction Register bit has no effect. When the SCI0 receiver is enabled, the PS[0] pin becomes the RXD0 input pin and the associated Data Direction Register bit has no effect. If the SPI and SCI0 functions are disabled, the corresponding Data Direction Register bit reverts to control the I/O direction of the associated pin.
Table 4-23. DDRS Field Descriptions
Field 7:4 DDRS[7:4] 1:0 DDRS[1:0] Data Direction Port S 0 Associated pin is configured as input. 1 Associated pin is configured as output. Data Direction Port S 0 Associated pin is configured as input. 1 Associated pin is configured as output. Description
MC9S12HZ256 Data Sheet, Rev. 2.05 144 Freescale Semiconductor
Chapter 4 Port Integration Module (PIM9HZ256V2)
4.3.5.4
Port S Reduced Drive Register (RDRS)
7 6 5 4 3 2 1 0
R RDRS7 W Reset 0 0 0 0 RDRS6 RDRS5 RDRS4
0
0 RDRS1 RDRS0 0
0
0
0
= Reserved or Unimplemented
Figure 4-33. Port S Reduced Drive Register (RDRS)
Read: Anytime. Write: Anytime. This register configures the drive strength of configured output pins as either full or reduced. If a pin is configured as input, the corresponding Reduced Drive Register bit has no effect.
Table 4-24. RDRS Field Descriptions
Field 7:4 RDRS[7:4] 1:0 RDRS[1:0] Description Reduced Drive Port S 0 Full drive strength at output. 1 Associated pin drives at about 1/3 of the full drive strength. Reduced Drive Port S 0 Full drive strength at output. 1 Associated pin drives at about 1/3 of the full drive strength.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 145
Chapter 4 Port Integration Module (PIM9HZ256V2)
4.3.5.5
Port S Pull Device Enable Register (PERS)
7 6 5 4 3 2 1 0
R PERS7 W Reset 0 0 0 0 PERS6 PERS5 PERS4
0
0 PERS1 PERS0 0
0
0
0
= Reserved or Unimplemented
Figure 4-34. Port S Pull Device Enable Register (PERS)
Read: Anytime. Write: Anytime. This register configures whether a pull-up or a pull-down device is activated on configured input or wired-or (open drain) output pins. If a pin is configured as push-pull output, the corresponding Pull Device Enable Register bit has no effect.
Table 4-25. PERS Field Descriptions
Field 7:4 PERS[7:4] 1:0 PERS[1:0] Pull Device Enable Port S 0 Pull-up or pull-down device is disabled. 1 Pull-up or pull-down device is enabled. Pull Device Enable Port S 0 Pull-up or pull-down device is disabled. 1 Pull-up or pull-down device is enabled. Description
4.3.5.6
Port S Polarity Select Register (PPSS)
7 6 5 4 3 2 1 0
R PPSS7 W Reset 0 0 0 0 PPSS6 PPSS5 PPSS4
0
0 PPSS1 PPSS0 0
0
0
0
= Reserved or Unimplemented
Figure 4-35. Port S Polarity Select Register (PPSS)
Read: Anytime. Write: Anytime. The Port S Polarity Select Register selects whether a pull-down or a pull-up device is connected to the pin. The Port S Polarity Select Register is effective only when the corresponding Data Direction Register bit is set to 0 (input) and the corresponding Pull Device Enable Register bit is set to 1.
MC9S12HZ256 Data Sheet, Rev. 2.05 146 Freescale Semiconductor
Chapter 4 Port Integration Module (PIM9HZ256V2)
Table 4-26. PPSS Field Descriptions
Field 7:4 PPSS[7:4] 1:0 PPSS[1:0] Description Pull Select Port S 0 A pull-up device is connected to the associated port S pin. 1 A pull-down device is connected to the associated port S pin. Pull Select Port S 0 A pull-up device is connected to the associated port S pin. 1 A pull-down device is connected to the associated port S pin.
4.3.5.7
Port S Wired-OR Mode Register (WOMS)
7 6 5 4 3 2 1 0
R WOMS7 W Reset 0 0 0 0 WOMS6 WOMS5 WOMS4
0
0 WOMS1 WOMS0 0
0
0
0
= Reserved or Unimplemented
Figure 4-36. Port S Wired-OR Mode Register (WOMS)
Read: Anytime. Write: Anytime. This register selects whether a port S output is configured as push-pull or wired-or. When a Wired-OR Mode Register bit is set to 1, the corresponding output pin is driven active low only (open drain) and a high level is not driven. A Wired-OR Mode Register bit has no effect if the corresponding pin is configured as an input.
Table 4-27. WOMS Field Descriptions
Field 7:4 Wired-OR Mode Port S WOMS[7:4] 0 Output buffers operate as push-pull outputs. 1 Output buffers operate as open-drain outputs. 1:0 Wired-OR Mode Port S WOMS[1:0] 0 Output buffers operate as push-pull outputs. 1 Output buffers operate as open-drain outputs. Description
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 147
Chapter 4 Port Integration Module (PIM9HZ256V2)
4.3.6
Port T
Port T is associated with the 8-channel timer (TIM) and the liquid crystal display (LCD) driver. Each pin is assigned to these modules according to the following priority: LCD Driver > timer > general-purpose I/O. If the corresponding LCD frontplane drivers are enabled (and LCD module is enabled), the FP[27:24] outputs of the LCD module are available on port T pins PT[3:0]. If the corresponding LCD frontplane drivers are disabled (or LCD module is disabled) and the timer is enabled, the timer channels configured for output compare are available on port T pins PT[3:0]. Refer to the LCD block description chapter for information on enabling and disabling the LCD and its frontplane drivers.Refer to the TIM block description chapter for information on enabling and disabling the TIM module. During reset, port T pins are configured as inputs with pull down.
4.3.6.1
Port T I/O Register (PTT)
7 6 5 4 3 2 1 0
R PTT7 W TIM: LCD: Reset 0 0 0 0 PTT6 PTT5 PTT4 PTT3 PTT2 PTT1 PTT0
OC7
OC6
OC5
OC4
OC3 1
0
OC2 1
0
OC1 1
0
OC0 1
0
Figure 4-37. Port T I/O Register (PTT)
Read: Anytime. Write: Anytime. If the associated data direction bit (DDRTx) is set to 1 (output), a read returns the value of the I/O register bit. If the associated data direction bit (DDRTx) is set to 0 (input) and the LCD frontplane driver is enabled (and LCD module is enabled), the associated I/O register bit (PTTx) reads "1". If the associated data direction bit (DDRTx) is set to 0 (input) and the LCD frontplane driver is disabled (or LCD module is disabled), a read returns the value of the pin.
MC9S12HZ256 Data Sheet, Rev. 2.05 148 Freescale Semiconductor
Chapter 4 Port Integration Module (PIM9HZ256V2)
4.3.6.2
Port T Input Register (PTIT)
7 6 5 4 3 2 1 0
R W Reset
PTIT7
PTIT6
PTIT5
PTIT4
PTIT3
PTIT2
PTIT1
PTIT0
u
u
u
u
u
u
u
u
= Reserved or Unimplemented
u = Unaffected by reset
Figure 4-38. Port T Input Register (PTIT)
Read: Anytime. Write: Never, writes to this register have no effect. If the LCD frontplane driver of an associated I/O pin is enabled (and LCD module is enabled), a read returns a 1. If the LCD frontplane driver of the associated I/O pin is disabled (or LCD module is disabled), a read returns the status of the associated pin.
4.3.6.3
Port T Data Direction Register (DDRT)
7 6 5 4 3 2 1 0
R DDRT7 W Reset 0 0 0 0 0 0 0 0 DDRT6 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0
Figure 4-39. Port T Data Direction Register (DDRT)
Read: Anytime. Write: Anytime. This register configures port pins PT[7:0] as either input or output. If a LCD frontplane driver is enabled (and LCD module is enabled), it outputs an analog signal to the corresponding pin and the associated Data Direction Register bit has no effect. If a LCD frontplane driver is disabled (or LCD module is disabled), the corresponding Data Direction Register bit reverts to control the I/O direction of the associated pin. If the TIM module is enabled, each port pin configured for output compare is forced to be an output and the associated Data Direction Register bit has no effect. If the associated timer output compare is disabled, the corresponding Data Direction Register bit reverts to control the I/O direction of the associated pin. If the TIM module is enabled, each port pin configured as an input capture has the corresponding Data Direction Register bit controlling the I/O direction of the associated pin.
Table 4-28. DDRT Field Descriptions
Field 7:0 DDRT[7:0] Data Direction Port T 0 Associated pin is configured as input. 1 Associated pin is configured as output. Description
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 149
Chapter 4 Port Integration Module (PIM9HZ256V2)
4.3.6.4
Port T Reduced Drive Register (RDRT)
7 6 5 4 3 2 1 0
R RDRT7 W Reset 0 0 0 0 0 0 0 0 RDRT6 RDRT5 RDRT4 RDRT3 RDRT2 RDRT1 RDRT0
Figure 4-40. Port T Reduced Drive Register (RDRT)
Read: Anytime. Write: Anytime. This register configures the drive strength of configured output pins as either full or reduced. If a pin is configured as input, the corresponding Reduced Drive Register bit has no effect.
Table 4-29. RDRT Field Descriptions
Field 7:0 RDRT[7:0] Description Reduced Drive Port T 0 Full drive strength at output. 1 Associated pin drives at about 1/3 of the full drive strength.
MC9S12HZ256 Data Sheet, Rev. 2.05 150 Freescale Semiconductor
Chapter 4 Port Integration Module (PIM9HZ256V2)
4.3.6.5
Port T Pull Device Enable Register (PERT)
7 6 5 4 3 2 1 0
R PERT7 W Reset 1 1 1 1 1 1 1 1 PERT6 PERT5 PERT4 PERT3 PERT2 PERT1 PERT0
Figure 4-41. Port T Pull Device Enable Register (PERT)
Read: Anytime. Write: Anytime. This register configures whether a pull-up or a pull-down device is activated on configured input pins. If a pin is configured as output, the corresponding Pull Device Enable Register bit has no effect.
Table 4-30. PERT Field Descriptions
Field 7:0 PERT[7:0] Pull Device Enable Port T 0 Pull-up or pull-down device is disabled. 1 Pull-up or pull-down device is enabled. Description
4.3.6.6
Port T Polarity Select Register (PPST)
7 6 5 4 3 2 1 0
R PPST7 W Reset 1 1 1 1 1 1 1 1 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0
Figure 4-42. Port T Polarity Select Register (PPST)
Read: Anytime. Write: Anytime. The Port T Polarity Select Register selects whether a pull-down or a pull-up device is connected to the pin. The Port T Polarity Select Register is effective only when the corresponding Data Direction Register bit is set to 0 (input) and the corresponding Pull Device Enable Register bit is set to 1.
Table 4-31. PPST Field Descriptions
Field 7:0 PPST[7:0] Description Pull Select Port T 0 A pull-up device is connected to the associated port T pin. 1 A pull-down device is connected to the associated port T pin.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 151
Chapter 4 Port Integration Module (PIM9HZ256V2)
4.3.7
Port U
Port U is associated with the stepper stall detect (SSD1 and SSD0) and motor controller (MC1 and MC0) modules. Each pin is assigned to these modules according to the following priority: SSD1/SSD0 > MC1/MC0 > general-purpose I/O. If SSD1 module is enabled, the PU[7:4] pins are controlled by the SSD1 module. If SSD1 module is disabled, the PU[7:4] pins are controlled by the motor control PWM channels 3 and 2 (MC1). If SSD0 module is enabled, the PU[3:0] pins are controlled by the SSD0 module. If SSD0 module is disabled, the PU[3:0] pins are controlled by the motor control PWM channels 1 and 0 (MC0). Refer to the SSD and MC block description chapters for information on enabling and disabling the SSD module and the motor control PWM channels respectively. During reset, port U pins are configured as high-impedance inputs.
4.3.7.1
Port U I/O Register (PTU)
7 6 5 4 3 2 1 0
R PTU7 W MC: SSD1/ SSD0: Reset M1C1P M1SINP 0 M1C1M M1SINM 0 M1COP M1COSP 0 M1COM M1COSM 0 M0C1P M0SINP 0 M0C1M M0SINM 0 M0C0P M1COSP 0 M0C0M M0COSM 0 PTU6 PTU5 PTU4 PTU3 PTU2 PTU1 PTU0
Figure 4-43. Port U I/O Register (PTU)
Read: Anytime. Write: Anytime. If the associated data direction bit (DDRUx) is set to 1 (output), a read returns the value of the I/O register bit. If the associated data direction bit (DDRUx) is set to 0 (input) and the slew rate is enabled, the associated I/O register bit (PTUx) reads "1". If the associated data direction bit (DDRUx) is set to 0 (input) and the slew rate is disabled, a read returns the value of the pin.
MC9S12HZ256 Data Sheet, Rev. 2.05 152 Freescale Semiconductor
Chapter 4 Port Integration Module (PIM9HZ256V2)
4.3.7.2
Port U Input Register (PTIU)
7 6 5 4 3 2 1 0
R W Reset
PTIU7
PTIU6
PTIU5
PTIU4
PTIU3
PTIU2
PTIU1
PTIU0
u
u
u
u
u
u
u
u
= Reserved or Unimplemented
u = Unaffected by reset
Figure 4-44. Port U Input Register (PTIU)
Read: Anytime. Write: Never, writes to this register have no effect. If the associated slew rate control is enabled (digital input buffer is disabled), a read returns a "1". If the associated slew rate control is disabled (digital input buffer is enabled), a read returns the status of the associated pin.
4.3.7.3
Port U Data Direction Register (DDRU)
7 6 5 4 3 2 1 0
R DDRU7 W Reset 0 0 0 0 0 0 0 0 DDRU6 DDRU5 DDRU4 DDRU3 DDRU2 DDRU1 DDRU0
Figure 4-45. Port U Data Direction Register (DDRU)
Read: Anytime. Write: Anytime. This register configures port pins PU[7:0] as either input or output. When enabled, the SSD or MC modules force the I/O state to be an output for each associated pin and the associated Data Direction Register bit has no effect. If the SSD and MC modules are disabled, the corresponding Data Direction Register bits revert to control the I/O direction of the associated pins.
Table 4-32. DDRU Field Descriptions
Field 7:0 DDRU[7:0] Data Direction Port U 0 Associated pin is configured as input. 1 Associated pin is configured as output. Description
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 153
Chapter 4 Port Integration Module (PIM9HZ256V2)
4.3.7.4
Port U Slew Rate Register (SRRU)
7 6 5 4 3 2 1 0
R SRRU7 W Reset 0 0 0 0 0 0 0 0 SRRU6 SRRU5 SRRU4 SRRU3 SRRU2 SRRU1 SRRU0
Figure 4-46. Port U Slew Rate Register (SRRU)
Read: Anytime. Write: Anytime. This register enables the slew rate control and disables the digital input buffer for port pins PU[7:0].
Table 4-33. SRRU Field Descriptions
Field 7:0 SRRU[7:0] Description Slew Rate Port U 0 Disables slew rate control and enables digital input buffer. 1 Enables slew rate control and disables digital input buffer.
4.3.7.5
Port U Pull Device Enable Register (PERU)
7 6 5 4 3 2 1 0
R PERU7 W Reset 0 0 0 0 0 0 0 0 PERU6 PERU5 PERU4 PERU3 PERU2 PERU1 PERU0
Figure 4-47. Port U Pull Device Enable Register (PERU)
Read: Anytime. Write: Anytime. This register configures whether a pull-up or a pull-down device is activated on configured input pins. If a pin is configured as output, the corresponding Pull Device Enable Register bit has no effect.
Table 4-34. PERU Field Descriptions
Field 7:0 PERU[7:0] Pull Device Enable Port U 0 Pull-up or pull-down device is disabled. 1 Pull-up or pull-down device is enabled. Description
MC9S12HZ256 Data Sheet, Rev. 2.05 154 Freescale Semiconductor
Chapter 4 Port Integration Module (PIM9HZ256V2)
4.3.7.6
Port U Polarity Select Register (PPSU)
7 6 5 4 3 2 1 0
R PPSU7 W Reset 0 0 0 0 0 0 0 0 PPSU6 PPSU5 PPSU4 PPSU3 PPSU2 PPSU1 PPSU0
Figure 4-48. Port U Polarity Select Register (PPSU)
Read: Anytime. Write: Anytime. The Port U Polarity Select Register selects whether a pull-down or a pull-up device is connected to the pin. The Port U Polarity Select Register is effective only when the corresponding Data Direction Register bit is set to 0 (input) and the corresponding Pull Device Enable Register bit is set to 1.
Table 4-35. PPSU Field Descriptions
Field 7:0 PPSU[7:0] Description Pull Select Port U 0 A pull-up device is connected to the associated port U pin. 1 A pull-down device is connected to the associated port U pin.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 155
Chapter 4 Port Integration Module (PIM9HZ256V2)
4.3.8
Port V
Port V is associated with the stepper stall detect (SSD3 and SSD2) and motor controller (MC3 and MC2) modules. Each pin is assigned to these modules according to the following priority: SSD3/SSD2 > MC3/MC2 > general-purpose I/O. If SSD3 module is enabled, the PV[7:4] pins are controlled by the SSD3 module. If SSD3 module is disabled, the PV[7:4] pins are controlled by the motor control PWM channels 7 and 6 (MC3). If SSD2 module is enabled, the PV[3:0] pins are controlled by the SSD2 module. If SSD2 module is disabled, the PV[3:0] pins are controlled by the motor control PWM channels 5 and 4 (MC2). Refer to the SSD and MC block description chapters for information on enabling and disabling the SSD module and the motor control PWM channels respectively. During reset, port V pins are configured as high-impedance inputs.
4.3.8.1
Port V I/O Register (PTV)
7 6 5 4 3 2 1 0
R PTV7 W MC: SSD3/ SSD2 Reset M3C1P M3SINP 0 M3C1M M3SINM 0 M3C0P M3COSP 0 M3C0M M3COSM 0 M2C1P M2SINP 0 M2C1M M2SINM 0 M2C0P M2COSP 0 M2C0M M2COSM 0 PTV6 PTV5 PTV4 PTV3 PTV2 PTV1 PTV0
Figure 4-49. Port V I/O Register (PTV)
Read: Anytime. Write: anytime. If the associated data direction bit (DDRVx) is set to 1 (output), a read returns the value of the I/O register bit. If the associated data direction bit (DDRVx) is set to 0 (input) and the slew rate is enabled, the associated I/O register bit (PTVx) reads "1". If the associated data direction bit (DDRVx) is set to 0 (input) and the slew rate is disabled, a read returns the value of the pin.
MC9S12HZ256 Data Sheet, Rev. 2.05 156 Freescale Semiconductor
Chapter 4 Port Integration Module (PIM9HZ256V2)
4.3.8.2
Port V Input Register (PTIV)
7 6 5 4 3 2 1 0
R W Reset
PTIV7
PTIV6
PTIV5
PTIV4
PTIV3
PTIV2
PTIV1
PTIV0
u
u
u
u
u
u
u
u
= Reserved or Unimplemented
u = Unaffected by reset
Figure 4-50. Port V Input Register (PTIV)
Read: Anytime. Write: Never, writes to this register have no effect. If the associated slew rate control is enabled (digital input buffer is disabled), a read returns a "1". If the associated slew rate control is disabled (digital input buffer is enabled), a read returns the status of the associated pin.
4.3.8.3
Port V Data Direction Register (DDRV)
7 6 5 4 3 2 1 0
R DDRV7 W Reset 0 0 0 0 0 0 0 0 DDRV6 DDRV5 DDRV4 DDRV3 DDRV2 DDRV1 DDRV0
Figure 4-51. Port V Data Direction Register (DDRV)
Read: Anytime. Write: Anytime. This register configures port pins PV[7:0] as either input or output. When enabled, the SSD or MC modules force the I/O state to be an output for each associated pin and the associated Data Direction Register bit has no effect. If the SSD and MC modules are disabled, the corresponding Data Direction Register bits revert to control the I/O direction of the associated pins.
Table 4-36. DDRV Field Descriptions
Field 7:0 DDRV[7:0] Data Direction Port V 0 Associated pin is configured as input. 1 Associated pin is configured as output. Description
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 157
Chapter 4 Port Integration Module (PIM9HZ256V2)
4.3.8.4
Port V Slew Rate Register (SRRV)
7 6 5 4 3 2 1 0
R SRRV7 W Reset 0 0 0 0 0 0 0 0 SRRV6 SRRV5 SRRV4 SRRV3 SRRV2 SRRV1 SRRV0
Figure 4-52. Port V Slew Rate Register (SRRV)
Read: anytime. Write: Anytime. This register enables the slew rate control and disables the digital input buffer for port pins PV[7:0].
Table 4-37. SRRV Field Descriptions
Field 7:0 SRRV[7:0] Description Slew Rate Port V 0 Disables slew rate control and enables digital input buffer. 1 Enables slew rate control and disables digital input buffer.
4.3.8.5
Port V Pull Device Enable Register (PERV)
7 6 5 4 3 2 1 0
R PERV7 W Reset 0 0 0 0 0 0 0 0 PERV6 PERV5 PERV4 PERV3 PERV2 PERV1 PERV0
Figure 4-53. Port V Pull Device Enable Register (PERV)
Read: Anytime. Write: Anytime. This register configures whether a pull-up or a pull-down device is activated on configured input pins. If a pin is configured as output, the corresponding Pull Device Enable Register bit has no effect.
Table 4-38. PERV Field Descriptions
Field 7:0 PERV[7:0] Pull Device Enable Port V 0 Pull-up or pull-down device is disabled. 1 Pull-up or pull-down device is enabled. Description
MC9S12HZ256 Data Sheet, Rev. 2.05 158 Freescale Semiconductor
Chapter 4 Port Integration Module (PIM9HZ256V2)
4.3.8.6
Port V Polarity Select Register (PPSV)
7 6 5 4 3 2 1 0
R PPSV7 W Reset 0 0 0 0 0 0 0 0 PPSV6 PPSV5 PPSV4 PPSV3 PPSV2 PPSV1 PPSV0
Figure 4-54. Port V Polarity Select Register (PPSV)
Read: Anytime. Write: Anytime. The Port V Polarity Select Register selects whether a pull-down or a pull-up device is connected to the pin. The Port V Polarity Select Register is effective only when the corresponding Data Direction Register bit is set to 0 (input) and the corresponding Pull Device Enable Register bit is set to 1.
Table 4-39. PPSV Field Descriptions
Field 7:0 PPSV[7:0] Description Pull Select Port V 0 A pull-up device is connected to the associated port V pin. 1 A pull-down device is connected to the associated port V pin.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 159
Chapter 4 Port Integration Module (PIM9HZ256V2)
4.4
Functional Description
Each pin associated with ports AD, L, P, S, T, U and V can act as general-purpose I/O. In addition the pin can act as an output from a peripheral module or an input to a peripheral module. A set of configuration registers is common to all ports. All registers can be written at any time, however a specific configuration might not become active. Example: Selecting a pull-up resistor. This resistor does not become active while the port is used as a push-pull output.
4.4.1
I/O Register
The I/O Register holds the value driven out to the pin if the port is used as a general-purpose I/O. Writing to the I/O Register only has an effect on the pin if the port is used as general-purpose output. When reading the I/O Register, the value of each pin is returned if the corresponding Data Direction Register bit is set to 0 (pin configured as input). If the data direction register bits is set to 1, the content of the I/O Register bit is returned. This is independent of any other configuration (Figure 4-55). Due to internal synchronization circuits, it can take up to 2 bus cycles until the correct value is read on the I/O Register when changing the data direction register.
4.4.2
Input Register
The Input Register is a read-only register and generally returns the value of the pin (Figure 4-55). It can be used to detect overload or short circuit conditions. Due to internal synchronization circuits, it can take up to 2 bus cycles until the correct value is read on the Input Register when changing the Data Direction Register.
4.4.3
Data Direction Register
The Data Direction Register defines whether the pin is used as an input or an output. A Data Direction Register bit set to 0 configures the pin as an input. A Data Direction Register bit set to 0 configures the pin as an output. If a peripheral module controls the pin the contents of the data direction register is ignored (Figure 4-55).
MC9S12HZ256 Data Sheet, Rev. 2.05 160 Freescale Semiconductor
Chapter 4 Port Integration Module (PIM9HZ256V2)
PTIx
0 1
PTx
0 1
PAD
DDRx Digital Module
data out output enable
0 1
module enable
Figure 4-55. Illustration of I/O Pin Functionality
Figure 4-56 shows the state of digital inputs and outputs when an analog module drives the port. When the analog module is enabled all associated digital output ports are disabled and all associated digital input ports read "1". 1
Digital Input
1 0
Module Enable
Analog Module
Digital Output Analog Output
0 1
PAD
PIM Boundary
Figure 4-56. Digital Ports and Analog Module
4.4.4
Reduced Drive Register
If the port is used as an output the Reduced Drive Register allows the configuration of the drive strength.
4.4.5
Pull Device Enable Register
The Pull Device Enable Register turns on a pull-up or pull-down device. The pull device becomes active only if the pin is used as an input or as a wired-or output.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 161
Chapter 4 Port Integration Module (PIM9HZ256V2)
4.4.6
Polarity Select Register
The Polarity Select Register selects either a pull-up or pull-down device if enabled. The pull device becomes active only if the pin is used as an input or as a wired-or output.
4.4.7
Pin Configuration Summary
The following table summarizes the effect of various configuration in the Data Direction (DDR), Input/Output (I/O), reduced drive (RDR), Pull Enable (PE), Pull Select (PS) and Interrupt Enable (IE) register bits. The PS configuration bit is used for two purposes: 1. Configure the sensitive interrupt edge (rising or falling), if interrupt is enabled. 2. Select either a pull-up or pull-down device if PE is set to "1".
Table 4-40. Pin Configuration Summary
DDR 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
1 2
IO X X X X X X X 0 1 0 1 0 1 0 1
RDR X X X X X X X 0 0 1 1 0 0 1 1
PE 0 1 1 0 0 1 1 X X X X X X X X
PS X 0 1 0 1 0 1 X X X X 0 1 0 1
IE1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
Function2 Input Input Input Input Input Input Input Output to 0, Full Drive Output to 1, Full Drive Output to 0, Reduced Drive Output to 1, Reduced Drive Output to 0, Full Drive Output to 1, Full Drive Output to 0, Reduced Drive Output to 1, Reduced Drive
Pull Device Disabled Pull Up Pull Down Disabled Disabled Pull Up Pull Down Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled
Interrupt Disabled Disabled Disabled Falling Edge Rising Edge Falling Edge Rising Edge Disabled Disabled Disabled Disabled Falling Edge Rising Edge Falling Edge Rising Edge
Applicable only on Port AD. Digital outputs are disabled and digital input logic is forced to "1" when an analog module associated with the port is enabled.
MC9S12HZ256 Data Sheet, Rev. 2.05 162 Freescale Semiconductor
Chapter 4 Port Integration Module (PIM9HZ256V2)
4.5
Resets
The reset values of all registers are given in the register description in Section 4.3, "Memory Map and Register Definition". All ports start up as general-purpose inputs on reset.
4.5.1
Reset Initialization
All registers including the data registers get set/reset asynchronously. Table 4-41 summarizes the port properties after reset initialization.
P
Table 4-41. Port Reset State Summary
Reset States Port Data Direction Refer to section Bus Control and Input/Output Pull Mode Pull Down Pull Down Pull Down1 Pull Down Pull Down Input Input Input Input Input Input Input Input Pull Down Hi-z Hi-z Hi-z Pull Down Hi-z Hi-z Hi-z Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled N/A Disabled Disabled N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Disabled Red. Drive/ Slew Rate Wired-OR Mode Interrupt
A B E K BKGD pin T S M P L U V AD
1
Refer to section Bus Control and Input/Output
PE[1:0] pins have pull-ups instead of pull-downs.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 163
Chapter 4 Port Integration Module (PIM9HZ256V2)
4.6
4.6.1
Interrupts
General
Port AD generates an edge sensitive interrupt if enabled. It offers eight I/O pins with edge triggered interrupt capability in wired-or fashion. The interrupt enable as well as the sensitivity to rising or falling edges can be individually configured on per pin basis. All eight bits/pins share the same interrupt vector. Interrupts can be used with the pins configured as inputs (with the corresponding ATDDIEN1 bit set to 1) or outputs. An interrupt is generated when a bit in the port interrupt flag register and its corresponding port interrupt enable bit are both set. This external interrupt feature is capable to wake up the CPU when it is in stop or wait mode. A digital filter on each pin prevents pulses (Figure 4-58) shorter than a specified time from generating an interrupt. The minimum time varies over process conditions, temperature and voltage (Figure 4-57 and Table 4-42).
Glitch, filtered out, no interrupt flag set
Valid pulse, interrupt flag set
tifmin tifmax Figure 4-57. Interrupt Glitch Filter on Port AD (PPS = 0)
Table 4-42. Pulse Detection Criteria
Mode Pulse STOP Unit Ignored Uncertain Valid
1
STOP1 Unit tpulse <= 3.2 3.2 < tpulse < 10 s s s
tpulse <= 3 3 < tpulse <4
Bus Clock Bus Clock Bus Clock
tpulse >= 4
tpulse >= 10
These values include the spread of the oscillator frequency over temperature, voltage and process.
MC9S12HZ256 Data Sheet, Rev. 2.05 164 Freescale Semiconductor
Chapter 4 Port Integration Module (PIM9HZ256V2)
tpulse
Figure 4-58. Pulse Illustration
A valid edge on an input is detected if 4 consecutive samples of a passive level are followed by 4 consecutive samples of an active level directly or indirectly The filters are continuously clocked by the bus clock in RUN and WAIT mode. In STOP mode the clock is generated by a single RC oscillator in the port integration module. To maximize current saving the RC oscillator runs only if the following condition is true on any pin: Sample count <= 4 and port interrupt enabled (PIE=1) and port interrupt flag not set (PIF=0).
4.6.2
Interrupt Sources
Table 4-43. Port Integration Module Interrupt Sources
Interrupt Source Port AD Interrupt Flag PIFAD[7:0] Local Enable PIEAD[7:0] Global (CCR) Mask I Bit
NOTE Vector addresses and their relative interrupt priority are determined at the MCU level.
4.6.3
Operation in Stop Mode
All clocks are stopped in STOP mode. The port integration module has asynchronous paths on port AD to generate wake-up interrupts from stop mode. For other sources of external interrupts refer to the respective block description chapters.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 165
Chapter 4 Port Integration Module (PIM9HZ256V2)
MC9S12HZ256 Data Sheet, Rev. 2.05 166 Freescale Semiconductor
Chapter 5 Clocks and Reset Generator (CRGV4)
5.1 Introduction
This specification describes the function of the clocks and reset generator (CRG).
5.1.1
Features
The main features of this block are: * Phase-locked loop (PLL) frequency multiplier -- Reference divider -- Automatic bandwidth control mode for low-jitter operation -- Automatic frequency lock detector -- CPU interrupt on entry or exit from locked condition -- Self-clock mode in absence of reference clock * System clock generator -- Clock quality check -- Clock switch for either oscillator- or PLL-based system clocks -- User selectable disabling of clocks during wait mode for reduced power consumption * Computer operating properly (COP) watchdog timer with time-out clear window * System reset generation from the following possible sources: -- Power-on reset -- Low voltage reset Refer to the device overview section for availability of this feature. -- COP reset -- Loss of clock reset -- External pin reset * Real-time interrupt (RTI)
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 167
Chapter 5 Clocks and Reset Generator (CRGV4)
5.1.2
Modes of Operation
This subsection lists and briefly describes all operating modes supported by the CRG. * Run mode All functional parts of the CRG are running during normal run mode. If RTI or COP functionality is required the individual bits of the associated rate select registers (COPCTL, RTICTL) have to be set to a nonzero value. * Wait mode This mode allows to disable the system and core clocks depending on the configuration of the individual bits in the CLKSEL register. * Stop mode Depending on the setting of the PSTP bit, stop mode can be differentiated between full stop mode (PSTP = 0) and pseudo-stop mode (PSTP = 1). -- Full stop mode The oscillator is disabled and thus all system and core clocks are stopped. The COP and the RTI remain frozen. -- Pseudo-stop mode The oscillator continues to run and most of the system and core clocks are stopped. If the respective enable bits are set the COP and RTI will continue to run, else they remain frozen. * Self-clock mode Self-clock mode will be entered if the clock monitor enable bit (CME) and the self-clock mode enable bit (SCME) are both asserted and the clock monitor in the oscillator block detects a loss of clock. As soon as self-clock mode is entered the CRG starts to perform a clock quality check. Self-clock mode remains active until the clock quality check indicates that the required quality of the incoming clock signal is met (frequency and amplitude). Self-clock mode should be used for safety purposes only. It provides reduced functionality to the MCU in case a loss of clock is causing severe system conditions.
5.1.3
Block Diagram
Figure 5-1 shows a block diagram of the CRG.
MC9S12HZ256 Data Sheet, Rev. 2.05 168 Freescale Semiconductor
Chapter 5 Clocks and Reset Generator (CRGV4)
Voltage Regulator
Power-on Reset Low Voltage Reset 1
CRG
RESET
COP Timeout
XCLKS EXTAL XTAL
Clock Monitor
CM fail
Reset Generator Clock Quality Checker COP RTI
System Reset
OSCCLK
Oscillator
Bus Clock Core Clock Oscillator Clock
Registers
XFC VDDPLL VSSPLL PLLCLK
PLL
Clock and Reset Control
Real-Time Interrupt PLL Lock Interrupt Self-Clock Mode Interrupt
1
Refer to the device overview section for availability of the low-voltage reset feature.
Figure 5-1. CRG Block Diagram
5.2
External Signal Description
This section lists and describes the signals that connect off chip.
5.2.1
VDDPLL, VSSPLL -- PLL Operating Voltage, PLL Ground
These pins provides operating voltage (VDDPLL) and ground (VSSPLL) for the PLL circuitry. This allows the supply voltage to the PLL to be independently bypassed. Even if PLL usage is not required VDDPLL and VSSPLL must be connected properly.
5.2.2
XFC -- PLL Loop Filter Pin
A passive external loop filter must be placed on the XFC pin. The filter is a second-order, low-pass filter to eliminate the VCO input ripple. The value of the external filter network and the reference frequency determines the speed of the corrections and the stability of the PLL. Refer to the device overview chapter for calculation of PLL loop filter (XFC) components. If PLL usage is not required the XFC pin must be tied to VDDPLL.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 169
Chapter 5 Clocks and Reset Generator (CRGV4)
VDDPLL
CS MCU RS
CP
XFC
Figure 5-2. PLL Loop Filter Connections
5.2.3
RESET -- Reset Pin
RESET is an active low bidirectional reset pin. As an input it initializes the MCU asynchronously to a known start-up state. As an open-drain output it indicates that an system reset (internal to MCU) has been triggered.
5.3
Memory Map and Register Definition
This section provides a detailed description of all registers accessible in the CRG.
5.3.1
Module Memory Map
Table 5-1 gives an overview on all CRG registers.
Table 5-1. CRG Memory Map
Address Offset 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B
1 2
Use CRG Synthesizer Register (SYNR) CRG Reference Divider Register (REFDV) CRG Test Flags Register (CTFLG)1 CRG Flags Register (CRGFLG) CRG Interrupt Enable Register (CRGINT) CRG Clock Select Register (CLKSEL) CRG PLL Control Register (PLLCTL) CRG RTI Control Register (RTICTL) CRG COP Control Register (COPCTL) CRG Force and Bypass Test Register CRG Test Control Register (CTCTL)3 (FORBYP)2
Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
CRG COP Arm/Timer Reset (ARMCOP)
CTFLG is intended for factory test purposes only. FORBYP is intended for factory test purposes only. 3 CTCTL is intended for factory test purposes only.
MC9S12HZ256 Data Sheet, Rev. 2.05 170 Freescale Semiconductor
Chapter 5 Clocks and Reset Generator (CRGV4)
NOTE Register address = base address + address offset, where the base address is defined at the MCU level and the address offset is defined at the module level.
5.3.2
Register Descriptions
This section describes in address order all the CRG registers and their individual bits.
Register Name SYNR R W REFDV R W CTFLG R W CRGFLG R W CRGINT R W CLKSEL R W PLLCTL R W RTICTL R W COPCTL R W FORBYP CTCTL R W R W = Unimplemented or Reserved 0 0 0 0 0 0 0 0 WCOP 0 RTIF PORF 0 LVRF 0 LOCKIF LOCK TRACK SCMIF SCM 0 0 0 0 0 0
Bit 7 0
6 0
5 SYN5 0
4 SYN4 0
3 SYN3
2 SYN2
1 SYN1
Bit 0 SYN0
REFDV3 0
REFDV2 0
REFDV1 0
REFDV0 0
RTIE
LOCKIE
0
0
SCMIE
0
PLLSEL
PSTP
SYSWAI
ROAWAI
PLLWAI 0
CWAI
RTIWAI
COPWAI
CME 0
PLLON
AUTO
ACQ
PRE
PCE
SCME
RTR6
RTR5 0
RTR4 0
RTR3 0
RTR2
RTR1
RTR0
RSBCK 0
CR2 0
CR1 0
CR0 0
0
0
0
Figure 5-3. CRG Register Summary
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 171
Chapter 5 Clocks and Reset Generator (CRGV4)
Register Name ARMCOP R W
Bit 7 0 Bit 7
6 0 Bit 6
5 0 Bit 5
4 0 Bit 4
3 0 Bit 3
2 0 Bit 2
1 0 Bit 1
Bit 0 0 Bit 0
= Unimplemented or Reserved
Figure 5-3. CRG Register Summary (continued)
5.3.2.1
CRG Synthesizer Register (SYNR)
The SYNR register controls the multiplication factor of the PLL. If the PLL is on, the count in the loop divider (SYNR) register effectively multiplies up the PLL clock (PLLCLK) from the reference frequency by 2 x (SYNR+1). PLLCLK will not be below the minimum VCO frequency (fSCM).
( SYNR + 1 ) PLLCLK = 2xOSCCLKx ---------------------------------( REFDV + 1 )
NOTE If PLL is selected (PLLSEL=1), Bus Clock = PLLCLK / 2 Bus Clock must not exceed the maximum operating system frequency.
7 6 5 4 3 2 1 0
R W Reset
0
0 SYN5 SYNR 0 SYN3 0 SYN2 0 SYN1 0 SYN0 0
0
0
0
= Unimplemented or Reserved
Figure 5-4. CRG Synthesizer Register (SYNR)
Read: anytime Write: anytime except if PLLSEL = 1 NOTE Write to this register initializes the lock detector bit and the track detector bit.
MC9S12HZ256 Data Sheet, Rev. 2.05 172 Freescale Semiconductor
Chapter 5 Clocks and Reset Generator (CRGV4)
5.3.2.2
CRG Reference Divider Register (REFDV)
The REFDV register provides a finer granularity for the PLL multiplier steps. The count in the reference divider divides OSCCLK frequency by REFDV + 1.
7 6 5 4 3 2 1 0
R W Reset
0
0
0
0 REFDV3 REFDV2 0 REFDV1 0 REFDV0 0
0
0
0
0
0
= Unimplemented or Reserved
Figure 5-5. CRG Reference Divider Register (REFDV)
Read: anytime Write: anytime except when PLLSEL = 1 NOTE Write to this register initializes the lock detector bit and the track detector bit.
5.3.2.3
Reserved Register (CTFLG)
This register is reserved for factory testing of the CRG module and is not available in normal modes.
7 6 5 4 3 2 1 0
R W Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 5-6. CRG Reserved Register (CTFLG)
Read: always reads 0x0000 in normal modes Write: unimplemented in normal modes NOTE Writing to this register when in special mode can alter the CRG functionality.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 173
Chapter 5 Clocks and Reset Generator (CRGV4)
5.3.2.4
CRG Flags Register (CRGFLG)
This register provides CRG status bits and flags.
7 6 5 4 3 2 1 0
R RTIF W Reset 0 Note 1 Note 2 0 PORF LVRF LOCKIF
LOCK
TRACK SCMIF
SCM
0
0
0
0
1. PORF is set to 1 when a power-on reset occurs. Unaffected by system reset. 2. LVRF is set to 1 when a low-voltage reset occurs. Unaffected by system reset. = Unimplemented or Reserved
Figure 5-7. CRG Flag Register (CRGFLG)
Read: anytime Write: refer to each bit for individual write conditions
Table 5-2. CRGFLG Field Descriptions
Field 7 RTIF Description Real-Time Interrupt Flag -- RTIF is set to 1 at the end of the RTI period. This flag can only be cleared by writing a 1. Writing a 0 has no effect. If enabled (RTIE = 1), RTIF causes an interrupt request. 0 RTI time-out has not yet occurred. 1 RTI time-out has occurred. Power-on Reset Flag -- PORF is set to 1 when a power-on reset occurs. This flag can only be cleared by writing a 1. Writing a 0 has no effect. 0 Power-on reset has not occurred. 1 Power-on reset has occurred. Low-Voltage Reset Flag -- If low voltage reset feature is not available (see the device overview chapter), LVRF always reads 0. LVRF is set to 1 when a low voltage reset occurs. This flag can only be cleared by writing a 1. Writing a 0 has no effect. 0 Low voltage reset has not occurred. 1 Low voltage reset has occurred. PLL Lock Interrupt Flag -- LOCKIF is set to 1 when LOCK status bit changes. This flag can only be cleared by writing a 1. Writing a 0 has no effect.If enabled (LOCKIE = 1), LOCKIF causes an interrupt request. 0 No change in LOCK bit. 1 LOCK bit has changed. Lock Status Bit -- LOCK reflects the current state of PLL lock condition. This bit is cleared in self-clock mode. Writes have no effect. 0 PLL VCO is not within the desired tolerance of the target frequency. 1 PLL VCO is within the desired tolerance of the target frequency. Track Status Bit -- TRACK reflects the current state of PLL track condition. This bit is cleared in self-clock mode. Writes have no effect. 0 Acquisition mode status. 1 Tracking mode status.
6 PORF
5 LVRF
4 LOCKIF
3 LOCK
2 TRACK
MC9S12HZ256 Data Sheet, Rev. 2.05 174 Freescale Semiconductor
Chapter 5 Clocks and Reset Generator (CRGV4)
Table 5-2. CRGFLG Field Descriptions (continued)
Field 1 SCMIF Description Self-Clock Mode Interrupt Flag -- SCMIF is set to 1 when SCM status bit changes. This flag can only be cleared by writing a 1. Writing a 0 has no effect. If enabled (SCMIE=1), SCMIF causes an interrupt request. 0 No change in SCM bit. 1 SCM bit has changed. Self-Clock Mode Status Bit -- SCM reflects the current clocking mode. Writes have no effect. 0 MCU is operating normally with OSCCLK available. 1 MCU is operating in self-clock mode with OSCCLK in an unknown state. All clocks are derived from PLLCLK running at its minimum frequency fSCM.
0 SCM
5.3.2.5
CRG Interrupt Enable Register (CRGINT)
This register enables CRG interrupt requests.
7 6 5 4 3 2 1 0
R RTIE W Reset 0
0
0 LOCKIE
0
0 SCMIE
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 5-8. CRG Interrupt Enable Register (CRGINT)
Read: anytime Write: anytime
Table 5-3. CRGINT Field Descriptions
Field 7 RTIE 4 LOCKIE 1 SCMIE Description Real-Time Interrupt Enable Bit 0 Interrupt requests from RTI are disabled. 1 Interrupt will be requested whenever RTIF is set. Lock Interrupt Enable Bit 0 LOCK interrupt requests are disabled. 1 Interrupt will be requested whenever LOCKIF is set. Self-Clock Mode Interrupt Enable Bit 0 SCM interrupt requests are disabled. 1 Interrupt will be requested whenever SCMIF is set.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 175
Chapter 5 Clocks and Reset Generator (CRGV4)
5.3.2.6
CRG Clock Select Register (CLKSEL)
This register controls CRG clock selection. Refer to Figure 5-17 for details on the effect of each bit.
7 6 5 4 3 2 1 0
R PLLSEL W Reset 0 0 0 0 0 0 0 0 PSTP SYSWAI ROAWAI PLLWAI CWAI RTIWAI COPWAI
Figure 5-9. CRG Clock Select Register (CLKSEL)
Read: anytime Write: refer to each bit for individual write conditions
Table 5-4. CLKSEL Field Descriptions
Field 7 PLLSEL Description PLL Select Bit -- Write anytime. Writing a 1 when LOCK = 0 and AUTO = 1, or TRACK = 0 and AUTO = 0 has no effect. This prevents the selection of an unstable PLLCLK as SYSCLK. PLLSEL bit is cleared when the MCU enters self-clock mode, stop mode or wait mode with PLLWAI bit set. 0 System clocks are derived from OSCCLK (Bus Clock = OSCCLK / 2). 1 System clocks are derived from PLLCLK (Bus Clock = PLLCLK / 2). Pseudo-Stop Bit -- Write: anytime -- This bit controls the functionality of the oscillator during stop mode. 0 Oscillator is disabled in stop mode. 1 Oscillator continues to run in stop mode (pseudo-stop). The oscillator amplitude is reduced. Refer to oscillator block description for availability of a reduced oscillator amplitude. Note: Pseudo-stop allows for faster stop recovery and reduces the mechanical stress and aging of the resonator in case of frequent stop conditions at the expense of a slightly increased power consumption. Note: Lower oscillator amplitude exhibits lower power consumption but could have adverse effects during any electro-magnetic susceptibility (EMS) tests. System Clocks Stop in Wait Mode Bit -- Write: anytime 0 In wait mode, the system clocks continue to run. 1 In wait mode, the system clocks stop. Note: RTI and COP are not affected by SYSWAI bit. Reduced Oscillator Amplitude in Wait Mode Bit -- Write: anytime -- Refer to oscillator block description chapter for availability of a reduced oscillator amplitude. If no such feature exists in the oscillator block then setting this bit to 1 will not have any effect on power consumption. 0 Normal oscillator amplitude in wait mode. 1 Reduced oscillator amplitude in wait mode. Note: Lower oscillator amplitude exhibits lower power consumption but could have adverse effects during any electro-magnetic susceptibility (EMS) tests. PLL Stops in Wait Mode Bit -- Write: anytime -- If PLLWAI is set, the CRG will clear the PLLSEL bit before entering wait mode. The PLLON bit remains set during wait mode but the PLL is powered down. Upon exiting wait mode, the PLLSEL bit has to be set manually if PLL clock is required. While the PLLWAI bit is set the AUTO bit is set to 1 in order to allow the PLL to automatically lock on the selected target frequency after exiting wait mode. 0 PLL keeps running in wait mode. 1 PLL stops in wait mode. Core Stops in Wait Mode Bit -- Write: anytime 0 Core clock keeps running in wait mode. 1 Core clock stops in wait mode.
6 PSTP
5 SYSWAI
4 ROAWAI
3 PLLWAI
2 CWAI
MC9S12HZ256 Data Sheet, Rev. 2.05 176 Freescale Semiconductor
Chapter 5 Clocks and Reset Generator (CRGV4)
Table 5-4. CLKSEL Field Descriptions (continued)
Field 1 RTIWAI 0 COPWAI Description RTI Stops in Wait Mode Bit -- Write: anytime 0 RTI keeps running in wait mode. 1 RTI stops and initializes the RTI dividers whenever the part goes into wait mode. COP Stops in Wait Mode Bit -- Normal modes: Write once --Special modes: Write anytime 0 COP keeps running in wait mode. 1 COP stops and initializes the COP dividers whenever the part goes into wait mode.
5.3.2.7
CRG PLL Control Register (PLLCTL)
This register controls the PLL functionality.
7 6 5 4 3 2 1 0
R CME W Reset 1 1 1 1 PLLON AUTO ACQ
0 PRE 0 0 PCE 0 SCME 1
= Unimplemented or Reserved
Figure 5-10. CRG PLL Control Register (PLLCTL)
Read: anytime Write: refer to each bit for individual write conditions
Table 5-5. PLLCTL Field Descriptions
Field 7 CME Description Clock Monitor Enable Bit -- CME enables the clock monitor. Write anytime except when SCM = 1. 0 Clock monitor is disabled. 1 Clock monitor is enabled. Slow or stopped clocks will cause a clock monitor reset sequence or self-clock mode. Note: Operating with CME = 0 will not detect any loss of clock. In case of poor clock quality this could cause unpredictable operation of the MCU. Note: In Stop Mode (PSTP = 0) the clock monitor is disabled independently of the CME bit setting and any loss of clock will not be detected. Phase Lock Loop On Bit -- PLLON turns on the PLL circuitry. In self-clock mode, the PLL is turned on, but the PLLON bit reads the last latched value. Write anytime except when PLLSEL = 1. 0 PLL is turned off. 1 PLL is turned on. If AUTO bit is set, the PLL will lock automatically. Automatic Bandwidth Control Bit -- AUTO selects either the high bandwidth (acquisition) mode or the low bandwidth (tracking) mode depending on how close to the desired frequency the VCO is running. Write anytime except when PLLWAI=1, because PLLWAI sets the AUTO bit to 1. 0 Automatic mode control is disabled and the PLL is under software control, using ACQ bit. 1 Automatic mode control is enabled and ACQ bit has no effect. Acquisition Bit -- Write anytime. If AUTO=1 this bit has no effect. 0 Low bandwidth filter is selected. 1 High bandwidth filter is selected.
6 PLLON
5 AUTO
4 ACQ
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 177
Chapter 5 Clocks and Reset Generator (CRGV4)
Table 5-5. PLLCTL Field Descriptions (continued)
Field 2 PRE Description RTI Enable during Pseudo-Stop Bit -- PRE enables the RTI during pseudo-stop mode. Write anytime. 0 RTI stops running during pseudo-stop mode. 1 RTI continues running during pseudo-stop mode. Note: If the PRE bit is cleared the RTI dividers will go static while pseudo-stop mode is active. The RTI dividers will not initialize like in wait mode with RTIWAI bit set. COP Enable during Pseudo-Stop Bit -- PCE enables the COP during pseudo-stop mode. Write anytime. 0 COP stops running during pseudo-stop mode 1 COP continues running during pseudo-stop mode Note: If the PCE bit is cleared the COP dividers will go static while pseudo-stop mode is active. The COP dividers will not initialize like in wait mode with COPWAI bit set. Self-Clock Mode Enable Bit -- Normal modes: Write once --Special modes: Write anytime -- SCME can not be cleared while operating in self-clock mode (SCM=1). 0 Detection of crystal clock failure causes clock monitor reset (see Section 5.5.1, "Clock Monitor Reset"). 1 Detection of crystal clock failure forces the MCU in self-clock mode (see Section 5.4.7.2, "Self-Clock Mode").
1 PCE
0 SCME
5.3.2.8
CRG RTI Control Register (RTICTL)
This register selects the timeout period for the real-time interrupt.
7 6 5 4 3 2 1 0
R W Reset
0 RTR6 0 0 RTR5 0 RTR4 0 RTR3 0 RTR2 0 RTR1 0 RTR0 0
= Unimplemented or Reserved
Figure 5-11. CRG RTI Control Register (RTICTL)
Read: anytime Write: anytime NOTE A write to this register initializes the RTI counter.
Table 5-6. RTICTL Field Descriptions
Field 6:4 RTR[6:4] 3:0 RTR[3:0] Description Real-Time Interrupt Prescale Rate Select Bits -- These bits select the prescale rate for the RTI. See Table 5-7. Real-Time Interrupt Modulus Counter Select Bits -- These bits select the modulus counter target value to provide additional granularity. Table 5-7 shows all possible divide values selectable by the RTICTL register. The source clock for the RTI is OSCCLK.
MC9S12HZ256 Data Sheet, Rev. 2.05 178 Freescale Semiconductor
Chapter 5 Clocks and Reset Generator (CRGV4)
Table 5-7. RTI Frequency Divide Rates
RTR[6:4] = RTR[3:0] 000 (OFF) OFF* OFF* OFF* OFF* OFF* OFF* OFF* OFF* OFF* OFF* OFF* OFF* OFF* OFF* OFF* OFF* 001 (210) 210 2x210 3x210 4x210 5x210 6x210 7x210 8x210 9x210 10x210 11x210 12x210 13x210 14x210 15x210 16x210 010 (211) 211 2x211 3x211 4x211 5x211 6x211 7x211 8x211 9x211 10x211 11x211 12x211 13x211 14x211 15x211 16x211 011 (212) 212 2x212 3x212 4x212 5x212 6x212 7x212 8x212 9x212 10x212 11x212 12x212 13x212 14x212 15x212 16x212 100 (213) 213 2x213 3x213 4x213 5x213 6x213 7x213 8x213 9x213 10x213 11x213 12x213 13x213 14x213 15x213 16x213 101 (214) 214 2x214 3x214 4x214 5x214 6x214 7x214 8x214 9x214 10x214 11x214 12x214 13x214 14x214 15x214 16x214 110 (215) 215 2x215 3x215 4x215 5x215 6x215 7x215 8x215 9x215 10x215 11x215 12x215 13x215 14x215 15x215 16x215 111 (216) 216 2x216 3x216 4x216 5x216 6x216 7x216 8x216 9x216 10x216 11x216 12x216 13x216 14x216 15x216 16x216
0000 (/1) 0001 (/2) 0010 (/3) 0011 (/4) 0100 (/5) 0101 (/6) 0110 (/7) 0111 (/8) 1000 (/9) 1001 (/10) 1010 (/11) 1011 (/12) 1100 (/ 13) 1101 (/14) 1110 (/15) 1111 (/ 16)
* Denotes the default value out of reset.This value should be used to disable the RTI to ensure future backwards compatibility.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 179
Chapter 5 Clocks and Reset Generator (CRGV4)
5.3.2.9
CRG COP Control Register (COPCTL)
This register controls the COP (computer operating properly) watchdog.
7 6 5 4 3 2 1 0
R WCOP W Reset 0 0 RSBCK
0
0
0 CR2 CR1 0 CR0 0
0
0
0
0
= Unimplemented or Reserved
Figure 5-12. CRG COP Control Register (COPCTL)
Read: anytime Write: WCOP, CR2, CR1, CR0: once in user mode, anytime in special mode Write: RSBCK: once
Table 5-8. COPCTL Field Descriptions
Field 7 WCOP Description Window COP Mode Bit -- When set, a write to the ARMCOP register must occur in the last 25% of the selected period. A write during the first 75% of the selected period will reset the part. As long as all writes occur during this window, 0x0055 can be written as often as desired. As soon as 0x00AA is written after the 0x0055, the time-out logic restarts and the user must wait until the next window before writing to ARMCOP. Table 5-9 shows the exact duration of this window for the seven available COP rates. 0 Normal COP operation 1 Window COP operation COP and RTI Stop in Active BDM Mode Bit 0 Allows the COP and RTI to keep running in active BDM mode. 1 Stops the COP and RTI counters whenever the part is in active BDM mode. COP Watchdog Timer Rate Select -- These bits select the COP time-out rate (see Table 5-9). The COP time-out period is OSCCLK period divided by CR[2:0] value. Writing a nonzero value to CR[2:0] enables the COP counter and starts the time-out period. A COP counter time-out causes a system reset. This can be avoided by periodically (before time-out) reinitializing the COP counter via the ARMCOP register.
6 RSBCK 2:0 CR[2:0]
Table 5-9. COP Watchdog Rates1
CR2 0 0 0 0 1 1 1 1
1
CR1 0 0 1 1 0 0 1 1
CR0 0 1 0 1 0 1 0 1
OSCCLK Cycles to Time Out COP disabled 214 216 218 220 222 223 224
OSCCLK cycles are referenced from the previous COP time-out reset (writing 0x0055/0x00AA to the ARMCOP register)
MC9S12HZ256 Data Sheet, Rev. 2.05 180 Freescale Semiconductor
Chapter 5 Clocks and Reset Generator (CRGV4)
5.3.2.10
Reserved Register (FORBYP)
NOTE This reserved register is designed for factory test purposes only, and is not intended for general user access. Writing to this register when in special modes can alter the CRG's functionality.
7 6 5 4 3 2 1 0
R W Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 5-13. Reserved Register (FORBYP)
Read: always read 0x0000 except in special modes Write: only in special modes
5.3.2.11
Reserved Register (CTCTL)
NOTE This reserved register is designed for factory test purposes only, and is not intended for general user access. Writing to this register when in special test modes can alter the CRG's functionality.
7 6 5 4 3 2 1 0
R W Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 5-14. Reserved Register (CTCTL)
Read: always read 0x0080 except in special modes Write: only in special modes
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 181
Chapter 5 Clocks and Reset Generator (CRGV4)
5.3.2.12
CRG COP Timer Arm/Reset Register (ARMCOP)
This register is used to restart the COP time-out period.
7 6 5 4 3 2 1 0
R W Reset
0 Bit 7 0
0 Bit 6 0
0 Bit 5 0
0 Bit 4 0
0 Bit 3 0
0 Bit 2 0
0 Bit 1 0
0 Bit 0 0
Figure 5-15. ARMCOP Register Diagram
Read: always reads 0x0000 Write: anytime When the COP is disabled (CR[2:0] = "000") writing to this register has no effect. When the COP is enabled by setting CR[2:0] nonzero, the following applies: Writing any value other than 0x0055 or 0x00AA causes a COP reset. To restart the COP time-out period you must write 0x0055 followed by a write of 0x00AA. Other instructions may be executed between these writes but the sequence (0x0055, 0x00AA) must be completed prior to COP end of time-out period to avoid a COP reset. Sequences of 0x0055 writes or sequences of 0x00AA writes are allowed. When the WCOP bit is set, 0x0055 and 0x00AA writes must be done in the last 25% of the selected time-out period; writing any value in the first 75% of the selected period will cause a COP reset.
5.4
Functional Description
This section gives detailed informations on the internal operation of the design.
5.4.1
Phase Locked Loop (PLL)
The PLL is used to run the MCU from a different time base than the incoming OSCCLK. For increased flexibility, OSCCLK can be divided in a range of 1 to 16 to generate the reference frequency. This offers a finer multiplication granularity. The PLL can multiply this reference clock by a multiple of 2, 4, 6,... 126,128 based on the SYNR register.
[ SYNR + 1 ] PLLCLK = 2 x OSCCLK x ---------------------------------[ REFDV + 1 ]
CAUTION Although it is possible to set the two dividers to command a very high clock frequency, do not exceed the specified bus frequency limit for the MCU. If (PLLSEL = 1), Bus Clock = PLLCLK / 2 The PLL is a frequency generator that operates in either acquisition mode or tracking mode, depending on the difference between the output frequency and the target frequency. The PLL can change between acquisition and tracking modes either automatically or manually.
MC9S12HZ256 Data Sheet, Rev. 2.05 182 Freescale Semiconductor
Chapter 5 Clocks and Reset Generator (CRGV4)
The VCO has a minimum operating frequency, which corresponds to the self-clock mode frequency fSCM.
REFERENCE EXTAL REDUCED CONSUMPTION OSCILLATOR XTAL OSCCLK REFDV <3:0> FEEDBACK LOCK DETECTOR LOCK
REFERENCE PROGRAMMABLE DIVIDER
VDDPLL/VSSPLL PDET PHASE DETECTOR UP DOWN CPUMP VCO
CRYSTAL MONITOR
LOOP PROGRAMMABLE DIVIDER SYN <5:0>
VDDPLL LOOP FILTER XFC PIN PLLCLK
supplied by:
VDDPLL/VSSPLL VDD/VSS
Figure 5-16. PLL Functional Diagram
5.4.1.1
PLL Operation
The oscillator output clock signal (OSCCLK) is fed through the reference programmable divider and is divided in a range of 1 to 16 (REFDV+1) to output the reference clock. The VCO output clock, (PLLCLK) is fed back through the programmable loop divider and is divided in a range of 2 to 128 in increments of [2 x (SYNR +1)] to output the feedback clock. See Figure 5-16. The phase detector then compares the feedback clock, with the reference clock. Correction pulses are generated based on the phase difference between the two signals. The loop filter then slightly alters the DC voltage on the external filter capacitor connected to XFC pin, based on the width and direction of the correction pulse. The filter can make fast or slow corrections depending on its mode, as described in the next subsection. The values of the external filter network and the reference frequency determine the speed of the corrections and the stability of the PLL.
5.4.1.2
Acquisition and Tracking Modes
The lock detector compares the frequencies of the feedback clock, and the reference clock. Therefore, the speed of the lock detector is directly proportional to the final reference frequency. The circuit determines the mode of the PLL and the lock condition based on this comparison.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 183
Chapter 5 Clocks and Reset Generator (CRGV4)
The PLL filter can be manually or automatically configured into one of two possible operating modes: * Acquisition mode In acquisition mode, the filter can make large frequency corrections to the VCO. This mode is used at PLL start-up or when the PLL has suffered a severe noise hit and the VCO frequency is far off the desired frequency. When in acquisition mode, the TRACK status bit is cleared in the CRGFLG register. * Tracking mode In tracking mode, the filter makes only small corrections to the frequency of the VCO. PLL jitter is much lower in tracking mode, but the response to noise is also slower. The PLL enters tracking mode when the VCO frequency is nearly correct and the TRACK bit is set in the CRGFLG register. The PLL can change the bandwidth or operational mode of the loop filter manually or automatically. In automatic bandwidth control mode (AUTO = 1), the lock detector automatically switches between acquisition and tracking modes. Automatic bandwidth control mode also is used to determine when the PLL clock (PLLCLK) is safe to use as the source for the system and core clocks. If PLL LOCK interrupt requests are enabled, the software can wait for an interrupt request and then check the LOCK bit. If CPU interrupts are disabled, software can poll the LOCK bit continuously (during PLL start-up, usually) or at periodic intervals. In either case, only when the LOCK bit is set, is the PLLCLK clock safe to use as the source for the system and core clocks. If the PLL is selected as the source for the system and core clocks and the LOCK bit is clear, the PLL has suffered a severe noise hit and the software must take appropriate action, depending on the application. The following conditions apply when the PLL is in automatic bandwidth control mode (AUTO = 1): * The TRACK bit is a read-only indicator of the mode of the filter. * The TRACK bit is set when the VCO frequency is within a certain tolerance, trk, and is clear when the VCO frequency is out of a certain tolerance, unt. * The LOCK bit is a read-only indicator of the locked state of the PLL. * The LOCK bit is set when the VCO frequency is within a certain tolerance, Lock, and is cleared when the VCO frequency is out of a certain tolerance, unl. * CPU interrupts can occur if enabled (LOCKIE = 1) when the lock condition changes, toggling the LOCK bit. The PLL can also operate in manual mode (AUTO = 0). Manual mode is used by systems that do not require an indicator of the lock condition for proper operation. Such systems typically operate well below the maximum system frequency (fsys) and require fast start-up. The following conditions apply when in manual mode: * ACQ is a writable control bit that controls the mode of the filter. Before turning on the PLL in manual mode, the ACQ bit should be asserted to configure the filter in acquisition mode. * After turning on the PLL by setting the PLLON bit software must wait a given time (tacq) before entering tracking mode (ACQ = 0). * After entering tracking mode software must wait a given time (tal) before selecting the PLLCLK as the source for system and core clocks (PLLSEL = 1).
MC9S12HZ256 Data Sheet, Rev. 2.05 184 Freescale Semiconductor
Chapter 5 Clocks and Reset Generator (CRGV4)
5.4.2
System Clocks Generator
PLLSEL or SCM WAIT(CWAI,SYSWAI), STOP PHASE LOCK LOOP PLLCLK
1 0
SYSCLK Core Clock WAIT(SYSWAI), STOP SCM WAIT(RTIWAI), STOP(PSTP,PRE), RTI enable /2 CLOCK PHASE GENERATOR Bus Clock
EXTAL OSCILLATOR OSCCLK
1
RTI
0
XTAL
WAIT(COPWAI), STOP(PSTP,PCE), COP enable Clock Monitor WAIT(SYSWAI), STOP Oscillator Clock COP
STOP(PSTP) Gating Condition = Clock Gate Oscillator Clock (running during Pseudo-Stop Mode
Figure 5-17. System Clocks Generator
The clock generator creates the clocks used in the MCU (see Figure 5-17). The gating condition placed on top of the individual clock gates indicates the dependencies of different modes (stop, wait) and the setting of the respective configuration bits. The peripheral modules use the bus clock. Some peripheral modules also use the oscillator clock. The memory blocks use the bus clock. If the MCU enters self-clock mode (see Section 5.4.7.2, "Self-Clock Mode"), oscillator clock source is switched to PLLCLK running at its minimum frequency fSCM. The bus clock is used to generate the clock visible at the ECLK pin. The core clock signal is the clock for the CPU. The core clock is twice the bus clock as shown in Figure 5-18. But note that a CPU cycle corresponds to one bus clock. PLL clock mode is selected with PLLSEL bit in the CLKSEL register. When selected, the PLL output clock drives SYSCLK for the main system including the CPU and peripherals. The PLL cannot be turned off by clearing the PLLON bit, if the PLL clock is selected. When PLLSEL is changed, it takes a maximum
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 185
Chapter 5 Clocks and Reset Generator (CRGV4)
of 4 OSCCLK plus 4 PLLCLK cycles to make the transition. During the transition, all clocks freeze and CPU activity ceases.
CORE CLOCK:
BUS CLOCK / ECLK
Figure 5-18. Core Clock and Bus Clock Relationship
5.4.3
Clock Monitor (CM)
If no OSCCLK edges are detected within a certain time, the clock monitor within the oscillator block generates a clock monitor fail event. The CRG then asserts self-clock mode or generates a system reset depending on the state of SCME bit. If the clock monitor is disabled or the presence of clocks is detected no failure is indicated by the oscillator block.The clock monitor function is enabled/disabled by the CME control bit.
5.4.4
Clock Quality Checker
The clock monitor performs a coarse check on the incoming clock signal. The clock quality checker provides a more accurate check in addition to the clock monitor. A clock quality check is triggered by any of the following events: * Power-on reset (POR) * Low voltage reset (LVR) * Wake-up from full stop mode (exit full stop) * Clock monitor fail indication (CM fail) A time window of 50000 VCO clock cycles1 is called check window. A number greater equal than 4096 rising OSCCLK edges within a check window is called osc ok. Note that osc ok immediately terminates the current check window. See Figure 5-19 as an example.
1. VCO clock cycles are generated by the PLL when running at minimum frequency fSCM. MC9S12HZ256 Data Sheet, Rev. 2.05 186 Freescale Semiconductor
Chapter 5 Clocks and Reset Generator (CRGV4)
check window 1 2 3 49999 50000
VCO clock OSCCLK
12345
4096 4095 osc ok
Figure 5-19. Check Window Example
The sequence for clock quality check is shown in Figure 5-20.
CM fail Clock OK POR LVR exit full stop Clock Monitor Reset Enter SCM num=0 yes no SCM active? num=50
check window
num=num+1 yes yes no SCME=1 ? no
osc ok ? yes SCM active? no
no
num<50 ?
yes
Switch to OSCCLK
Exit SCM
Figure 5-20. Sequence for Clock Quality Check
NOTE Remember that in parallel to additional actions caused by self-clock mode or clock monitor reset1 handling the clock quality checker continues to check the OSCCLK signal.
1. A Clock Monitor Reset will always set the SCME bit to logical'1'
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 187
Chapter 5 Clocks and Reset Generator (CRGV4)
NOTE The clock quality checker enables the PLL and the voltage regulator (VREG) anytime a clock check has to be performed. An ongoing clock quality check could also cause a running PLL (fSCM) and an active VREG during pseudo-stop mode or wait mode
5.4.5
Computer Operating Properly Watchdog (COP)
WAIT(COPWAI), STOP(PSTP,PCE), COP enable OSCCLK CR[2:0] 0:0:0 CR[2:0] 0:0:1
/ 16384 /4
/4 /4 /4 /2 /2 Figure 5-21. Clock Chain for COP
0:1:0
0:1:1
1:0:0
1:0:1
1:1:0
gating condition
= Clock Gate
1:1:1
COP TIMEOUT
The COP (free running watchdog timer) enables the user to check that a program is running and sequencing properly. The COP is disabled out of reset. When the COP is being used, software is responsible for keeping the COP from timing out. If the COP times out it is an indication that the software is no longer being executed in the intended sequence; thus a system reset is initiated (see Section 5.5.2, "Computer Operating Properly Watchdog (COP) Reset)." The COP runs with a gated OSCCLK (see Section Figure 5-21., "Clock Chain for COP"). Three control bits in the COPCTL register allow selection of seven COP time-out periods. When COP is enabled, the program must write 0x0055 and 0x00AA (in this order) to the ARMCOP register during the selected time-out period. As soon as this is done, the COP time-out period is restarted. If the program fails to do this and the COP times out, the part will reset. Also, if any value other than 0x0055 or 0x00AA is written, the part is immediately reset. Windowed COP operation is enabled by setting WCOP in the COPCTL register. In this mode, writes to the ARMCOP register to clear the COP timer must occur in the last 25% of the selected time-out period. A premature write will immediately reset the part. If PCE bit is set, the COP will continue to run in pseudo-stop mode.
MC9S12HZ256 Data Sheet, Rev. 2.05 188 Freescale Semiconductor
Chapter 5 Clocks and Reset Generator (CRGV4)
5.4.6
Real-Time Interrupt (RTI)
The RTI can be used to generate a hardware interrupt at a fixed periodic rate. If enabled (by setting RTIE=1), this interrupt will occur at the rate selected by the RTICTL register. The RTI runs with a gated OSCCLK (see Section Figure 5-22., "Clock Chain for RTI"). At the end of the RTI time-out period the RTIF flag is set to 1 and a new RTI time-out period starts immediately. A write to the RTICTL register restarts the RTI time-out period. If the PRE bit is set, the RTI will continue to run in pseudo-stop mode.
.
WAIT(RTIWAI), STOP(PSTP,PRE), RTI enable OSCCLK
/ 1024
RTR[6:4] 0:0:0
0:0:1
/2 /2 /2 /2 /2
gating condition
= Clock Gate
0:1:0
0:1:1
1:0:0
1:0:1
1:1:0
/2
1:1:1 4-BIT MODULUS COUNTER (RTR[3:0])
RTI TIMEOUT
Figure 5-22. Clock Chain for RTI
5.4.7
5.4.7.1
Modes of Operation
Normal Mode
The CRG block behaves as described within this specification in all normal modes.
5.4.7.2
Self-Clock Mode
The VCO has a minimum operating frequency, fSCM. If the external clock frequency is not available due to a failure or due to long crystal start-up time, the bus clock and the core clock are derived from the VCO
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 189
Chapter 5 Clocks and Reset Generator (CRGV4)
running at minimum operating frequency; this mode of operation is called self-clock mode. This requires CME = 1 and SCME = 1. If the MCU was clocked by the PLL clock prior to entering self-clock mode, the PLLSEL bit will be cleared. If the external clock signal has stabilized again, the CRG will automatically select OSCCLK to be the system clock and return to normal mode. See Section 5.4.4, "Clock Quality Checker" for more information on entering and leaving self-clock mode. NOTE In order to detect a potential clock loss, the CME bit should be always enabled (CME=1). If CME bit is disabled and the MCU is configured to run on PLL clock (PLLCLK), a loss of external clock (OSCCLK) will not be detected and will cause the system clock to drift towards the VCO's minimum frequency fSCM. As soon as the external clock is available again the system clock ramps up to its PLL target frequency. If the MCU is running on external clock any loss of clock will cause the system to go static.
5.4.8
Low-Power Operation in Run Mode
The RTI can be stopped by setting the associated rate select bits to 0. The COP can be stopped by setting the associated rate select bits to 0.
5.4.9
Low-Power Operation in Wait Mode
The WAI instruction puts the MCU in a low power consumption stand-by mode depending on setting of the individual bits in the CLKSEL register. All individual wait mode configuration bits can be superposed. This provides enhanced granularity in reducing the level of power consumption during wait mode. Table 5-10 lists the individual configuration bits and the parts of the MCU that are affected in wait mode.
Table 5-10. MCU Configuration During Wait Mode
PLLWAI PLL Core System RTI COP Oscillator
1
CWAI -- stopped -- -- -- --
SYSWAI -- stopped stopped -- -- --
RTIWAI -- -- -- stopped -- --
COPWAI -- -- -- -- stopped --
ROAWAI -- -- -- -- -- reduced1
stopped -- -- -- -- --
Refer to oscillator block description for availability of a reduced oscillator amplitude.
After executing the WAI instruction the core requests the CRG to switch MCU into wait mode. The CRG then checks whether the PLLWAI, CWAI and SYSWAI bits are asserted (see Figure 5-23). Depending on the configuration the CRG switches the system and core clocks to OSCCLK by clearing the PLLSEL bit, disables the PLL, disables the core clocks and finally disables the remaining system clocks. As soon as all clocks are switched off wait mode is active.
MC9S12HZ256 Data Sheet, Rev. 2.05 190 Freescale Semiconductor
Chapter 5 Clocks and Reset Generator (CRGV4)
Core req's Wait Mode.
PLLWAI=1 ?
no
yes
Clear PLLSEL, Disable PLL CWAI or SYSWAI=1 ?
no
yes
Disable
core clocks
SYSWAI=1 ?
no no
Enter Wait Mode Wait Mode left due to external reset
Exit Wait w. ext.RESET
yes
Disable system clocks CME=1 ?
no
INT ?
yes
CM fail ?
yes no
yes
Exit Wait w. CMRESET
no
SCME=1 ?
yes no
Exit Wait Mode
SCMIE=1 ? Generate SCM Interrupt (Wakeup from Wait)
yes
Exit Wait Mode SCM=1 ?
no
yes
Enter SCM
Enter SCM
Continue w. normal OP
Figure 5-23. Wait Mode Entry/Exit Sequence
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 191
Chapter 5 Clocks and Reset Generator (CRGV4)
There are five different scenarios for the CRG to restart the MCU from wait mode: * External reset * Clock monitor reset * COP reset * Self-clock mode interrupt * Real-time interrupt (RTI) If the MCU gets an external reset during wait mode active, the CRG asynchronously restores all configuration bits in the register space to its default settings and starts the reset generator. After completing the reset sequence processing begins by fetching the normal reset vector. Wait mode is exited and the MCU is in run mode again. If the clock monitor is enabled (CME=1) the MCU is able to leave wait mode when loss of oscillator/external clock is detected by a clock monitor fail. If the SCME bit is not asserted the CRG generates a clock monitor fail reset (CMRESET). The CRG's behavior for CMRESET is the same compared to external reset, but another reset vector is fetched after completion of the reset sequence. If the SCME bit is asserted the CRG generates a SCM interrupt if enabled (SCMIE=1). After generating the interrupt the CRG enters self-clock mode and starts the clock quality checker (see Section 5.4.4, "Clock Quality Checker"). Then the MCU continues with normal operation.If the SCM interrupt is blocked by SCMIE = 0, the SCMIF flag will be asserted and clock quality checks will be performed but the MCU will not wake-up from wait mode. If any other interrupt source (e.g. RTI) triggers exit from wait mode the MCU immediately continues with normal operation. If the PLL has been powered-down during wait mode the PLLSEL bit is cleared and the MCU runs on OSCCLK after leaving wait mode. The software must manually set the PLLSEL bit again, in order to switch system and core clocks to the PLLCLK. If wait mode is entered from self-clock mode, the CRG will continue to check the clock quality until clock check is successful. The PLL and voltage regulator (VREG) will remain enabled. Table 5-11 summarizes the outcome of a clock loss while in wait mode.
MC9S12HZ256 Data Sheet, Rev. 2.05 192 Freescale Semiconductor
Chapter 5 Clocks and Reset Generator (CRGV4)
Table 5-11. Outcome of Clock Loss in Wait Mode
CME 0 1 1 SCME X 0 1 SCMIE X X 0 Clock failure --> No action, clock loss not detected. Clock failure --> CRG performs Clock Monitor Reset immediately Clock failure --> Scenario 1: OSCCLK recovers prior to exiting Wait Mode. - MCU remains in Wait Mode, - VREG enabled, - PLL enabled, - SCM activated, - Start Clock Quality Check, - Set SCMIF interrupt flag. Some time later OSCCLK recovers. - CM no longer indicates a failure, - 4096 OSCCLK cycles later Clock Quality Check indicates clock o.k., - SCM deactivated, - PLL disabled depending on PLLWAI, - VREG remains enabled (never gets disabled in Wait Mode). - MCU remains in Wait Mode. Some time later either a wakeup interrupt occurs (no SCM interrupt) - Exit Wait Mode using OSCCLK as system clock (SYSCLK), - Continue normal operation. or an External Reset is applied. - Exit Wait Mode using OSCCLK as system clock, - Start reset sequence. Scenario 2: OSCCLK does not recover prior to exiting Wait Mode. - MCU remains in Wait Mode, - VREG enabled, - PLL enabled, - SCM activated, - Start Clock Quality Check, - Set SCMIF interrupt flag, - Keep performing Clock Quality Checks (could continue infinitely) while in Wait Mode. Some time later either a wakeup interrupt occurs (no SCM interrupt) - Exit Wait Mode in SCM using PLL clock (fSCM) as system clock, - Continue to perform additional Clock Quality Checks until OSCCLK is o.k. again. or an External RESET is applied. - Exit Wait Mode in SCM using PLL clock (fSCM) as system clock, - Start reset sequence, - Continue to perform additional Clock Quality Checks until OSCCLK is o.k.again. CRG Actions
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 193
Chapter 5 Clocks and Reset Generator (CRGV4)
Table 5-11. Outcome of Clock Loss in Wait Mode (continued)
CME 1 SCME 1 SCMIE 1 Clock failure --> - VREG enabled, - PLL enabled, - SCM activated, - Start Clock Quality Check, - SCMIF set. SCMIF generates Self-Clock Mode wakeup interrupt. - Exit Wait Mode in SCM using PLL clock (fSCM) as system clock, - Continue to perform a additional Clock Quality Checks until OSCCLK is o.k. again. CRG Actions
5.4.10
Low-Power Operation in Stop Mode
All clocks are stopped in STOP mode, dependent of the setting of the PCE, PRE and PSTP bit. The oscillator is disabled in STOP mode unless the PSTP bit is set. All counters and dividers remain frozen but do not initialize. If the PRE or PCE bits are set, the RTI or COP continues to run in pseudo-stop mode. In addition to disabling system and core clocks the CRG requests other functional units of the MCU (e.g. voltage-regulator) to enter their individual power-saving modes (if available). This is the main difference between pseudo-stop mode and wait mode. After executing the STOP instruction the core requests the CRG to switch the MCU into stop mode. If the PLLSEL bit remains set when entering stop mode, the CRG will switch the system and core clocks to OSCCLK by clearing the PLLSEL bit. Then the CRG disables the PLL, disables the core clock and finally disables the remaining system clocks. As soon as all clocks are switched off, stop mode is active. If pseudo-stop mode (PSTP = 1) is entered from self-clock mode the CRG will continue to check the clock quality until clock check is successful. The PLL and the voltage regulator (VREG) will remain enabled. If full stop mode (PSTP = 0) is entered from self-clock mode an ongoing clock quality check will be stopped. A complete timeout window check will be started when stop mode is exited again. Wake-up from stop mode also depends on the setting of the PSTP bit.
MC9S12HZ256 Data Sheet, Rev. 2.05 194 Freescale Semiconductor
Chapter 5 Clocks and Reset Generator (CRGV4) Core req's Stop Mode. Clear PLLSEL, Disable PLL
Exit Stop w. ext.RESET
Wait Mode left due to external
Enter Stop Mode
no
INT ?
no
PSTP=1 ?
yes
CME=1 ?
no
INT ?
no
yes
yes
CM fail ?
yes no
no
Clock OK ?
Exit Stop w. CMRESET
no
SCME=1 ?
yes yes
Exit Stop w. CMRESET
yes
no
SCME=1 ?
yes
SCMIE=1 ? Generate SCM Interrupt (Wakeup from Stop)
no
Exit Stop Mode
yes
Exit Stop Mode SCM=1 ?
Exit Stop Mode
Exit Stop Mode
no
yes
Enter SCM
Enter SCM
Enter SCM
Continue w. normal OP
Figure 5-24. Stop Mode Entry/Exit Sequence
5.4.10.1
Wake-Up from Pseudo-Stop (PSTP=1)
Wake-up from pseudo-stop is the same as wake-up from wait mode. There are also three different scenarios for the CRG to restart the MCU from pseudo-stop mode: * * * External reset Clock monitor fail Wake-up interrupt
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 195
Chapter 5 Clocks and Reset Generator (CRGV4)
If the MCU gets an external reset during pseudo-stop mode active, the CRG asynchronously restores all configuration bits in the register space to its default settings and starts the reset generator. After completing the reset sequence processing begins by fetching the normal reset vector. Pseudo-stop mode is exited and the MCU is in run mode again. If the clock monitor is enabled (CME = 1) the MCU is able to leave pseudo-stop mode when loss of oscillator/external clock is detected by a clock monitor fail. If the SCME bit is not asserted the CRG generates a clock monitor fail reset (CMRESET). The CRG's behavior for CMRESET is the same compared to external reset, but another reset vector is fetched after completion of the reset sequence. If the SCME bit is asserted the CRG generates a SCM interrupt if enabled (SCMIE=1). After generating the interrupt the CRG enters self-clock mode and starts the clock quality checker (see Section 5.4.4, "Clock Quality Checker"). Then the MCU continues with normal operation. If the SCM interrupt is blocked by SCMIE = 0, the SCMIF flag will be asserted but the CRG will not wake-up from pseudo-stop mode. If any other interrupt source (e.g. RTI) triggers exit from pseudo-stop mode the MCU immediately continues with normal operation. Because the PLL has been powered-down during stop mode the PLLSEL bit is cleared and the MCU runs on OSCCLK after leaving stop mode. The software must set the PLLSEL bit again, in order to switch system and core clocks to the PLLCLK. Table 5-12 summarizes the outcome of a clock loss while in pseudo-stop mode.
MC9S12HZ256 Data Sheet, Rev. 2.05 196 Freescale Semiconductor
Chapter 5 Clocks and Reset Generator (CRGV4)
Table 5-12. Outcome of Clock Loss in Pseudo-Stop Mode
CME 0 1 1 SCME X 0 1 SCMIE X X 0 Clock failure --> No action, clock loss not detected. Clock failure --> CRG performs Clock Monitor Reset immediately Clock Monitor failure --> Scenario 1: OSCCLK recovers prior to exiting Pseudo-Stop Mode. - MCU remains in Pseudo-Stop Mode, - VREG enabled, - PLL enabled, - SCM activated, - Start Clock Quality Check, - Set SCMIF interrupt flag. Some time later OSCCLK recovers. - CM no longer indicates a failure, - 4096 OSCCLK cycles later Clock Quality Check indicates clock o.k., - SCM deactivated, - PLL disabled, - VREG disabled. - MCU remains in Pseudo-Stop Mode. Some time later either a wakeup interrupt occurs (no SCM interrupt) - Exit Pseudo-Stop Mode using OSCCLK as system clock (SYSCLK), - Continue normal operation. or an External Reset is applied. - Exit Pseudo-Stop Mode using OSCCLK as system clock, - Start reset sequence. Scenario 2: OSCCLK does not recover prior to exiting Pseudo-Stop Mode. - MCU remains in Pseudo-Stop Mode, - VREG enabled, - PLL enabled, - SCM activated, - Start Clock Quality Check, - Set SCMIF interrupt flag, - Keep performing Clock Quality Checks (could continue infinitely) while in Pseudo-Stop Mode. Some time later either a wakeup interrupt occurs (no SCM interrupt) - Exit Pseudo-Stop Mode in SCM using PLL clock (fSCM) as system clock - Continue to perform additional Clock Quality Checks until OSCCLK is o.k. again. or an External RESET is applied. - Exit Pseudo-Stop Mode in SCM using PLL clock (fSCM) as system clock - Start reset sequence, - Continue to perform additional Clock Quality Checks until OSCCLK is o.k.again. CRG Actions
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 197
Chapter 5 Clocks and Reset Generator (CRGV4)
Table 5-12. Outcome of Clock Loss in Pseudo-Stop Mode (continued)
CME 1 SCME 1 SCMIE 1 Clock failure --> - VREG enabled, - PLL enabled, - SCM activated, - Start Clock Quality Check, - SCMIF set. SCMIF generates Self-Clock Mode wakeup interrupt. - Exit Pseudo-Stop Mode in SCM using PLL clock (fSCM) as system clock, - Continue to perform a additional Clock Quality Checks until OSCCLK is o.k. again. CRG Actions
5.4.10.2
Wake-up from Full Stop (PSTP=0)
The MCU requires an external interrupt or an external reset in order to wake-up from stop mode. If the MCU gets an external reset during full stop mode active, the CRG asynchronously restores all configuration bits in the register space to its default settings and will perform a maximum of 50 clock check_windows (see Section 5.4.4, "Clock Quality Checker"). After completing the clock quality check the CRG starts the reset generator. After completing the reset sequence processing begins by fetching the normal reset vector. Full stop mode is exited and the MCU is in run mode again. If the MCU is woken-up by an interrupt, the CRG will also perform a maximum of 50 clock check_windows (see Section 5.4.4, "Clock Quality Checker"). If the clock quality check is successful, the CRG will release all system and core clocks and will continue with normal operation. If all clock checks within the timeout-window are failing, the CRG will switch to self-clock mode or generate a clock monitor reset (CMRESET) depending on the setting of the SCME bit. Because the PLL has been powered-down during stop mode the PLLSEL bit is cleared and the MCU runs on OSCCLK after leaving stop mode. The software must manually set the PLLSEL bit again, in order to switch system and core clocks to the PLLCLK. NOTE In full stop mode, the clock monitor is disabled and any loss of clock will not be detected.
5.5
Resets
This section describes how to reset the CRG and how the CRG itself controls the reset of the MCU. It explains all special reset requirements. Because the reset generator for the MCU is part of the CRG, this section also describes all automatic actions that occur during or as a result of individual reset conditions. The reset values of registers and signals are provided in Section 5.3, "Memory Map and Register
MC9S12HZ256 Data Sheet, Rev. 2.05 198 Freescale Semiconductor
Chapter 5 Clocks and Reset Generator (CRGV4)
Definition." All reset sources are listed in Table 5-13. Refer to the device overview chapter for related vector addresses and priorities.
Table 5-13. Reset Summary
Reset Source Power-on Reset Low Voltage Reset External Reset Clock Monitor Reset COP Watchdog Reset Local Enable None None None PLLCTL (CME=1, SCME=0) COPCTL (CR[2:0] nonzero)
The reset sequence is initiated by any of the following events: * * * * * Low level is detected at the RESET pin (external reset). Power on is detected. Low voltage is detected. COP watchdog times out. Clock monitor failure is detected and self-clock mode was disabled (SCME = 0).
Upon detection of any reset event, an internal circuit drives the RESET pin low for 128 SYSCLK cycles (see Figure 5-25). Because entry into reset is asynchronous it does not require a running SYSCLK. However, the internal reset circuit of the CRG cannot sequence out of current reset condition without a running SYSCLK. The number of 128 SYSCLK cycles might be increased by n = 3 to 6 additional SYSCLK cycles depending on the internal synchronization latency. After 128+n SYSCLK cycles the RESET pin is released. The reset generator of the CRG waits for additional 64 SYSCLK cycles and then samples the RESET pin to determine the originating source. Table 5-14 shows which vector will be fetched.
Table 5-14. Reset Vector Selection
Sampled RESET Pin (64 Cycles After Release) 1 1 1 0 Clock Monitor Reset Pending 0 1 0 X COP Reset Pending 0 X 1 X Vector Fetch POR / LVR / External Reset Clock Monitor Reset COP Reset POR / LVR / External Reset with rise of RESET pin
NOTE External circuitry connected to the RESET pin should not include a large capacitance that would interfere with the ability of this signal to rise to a valid logic 1 within 64 SYSCLK cycles after the low drive is released.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 199
Chapter 5 Clocks and Reset Generator (CRGV4)
The internal reset of the MCU remains asserted while the reset generator completes the 192 SYSCLK long reset sequence. The reset generator circuitry always makes sure the internal reset is deasserted synchronously after completion of the 192 SYSCLK cycles. In case the RESET pin is externally driven low for more than these 192 SYSCLK cycles (external reset), the internal reset remains asserted too.
RESET )( )(
RESET pin released
CRG drives RESET pin low
SYSCLK
) ( 128+n cycles
possibly SYSCLK not running with n being min 3 / max 6 cycles depending on internal synchronization delay
) ( 64 cycles
) (
possibly RESET driven low externally
Figure 5-25. RESET Timing
5.5.1
* * *
Clock Monitor Reset
Clock monitor is enabled (CME=1) Loss of clock is detected Self-clock mode is disabled (SCME=0)
The CRG generates a clock monitor reset in case all of the following conditions are true:
The reset event asynchronously forces the configuration registers to their default settings (see Section 5.3, "Memory Map and Register Definition"). In detail the CME and the SCME are reset to logical `1' (which doesn't change the state of the CME bit, because it has already been set). As a consequence, the CRG immediately enters self-clock mode and starts its internal reset sequence. In parallel the clock quality check starts. As soon as clock quality check indicates a valid oscillator clock the CRG switches to OSCCLK and leaves self-clock mode. Because the clock quality checker is running in parallel to the reset generator, the CRG may leave self-clock mode while completing the internal reset sequence. When the reset sequence is finished the CRG checks the internally latched state of the clock monitor fail circuit. If a clock monitor fail is indicated processing begins by fetching the clock monitor reset vector.
5.5.2
Computer Operating Properly Watchdog (COP) Reset
When COP is enabled, the CRG expects sequential write of 0x0055 and 0x00AA (in this order) to the ARMCOP register during the selected time-out period. As soon as this is done, the COP time-out period restarts. If the program fails to do this the CRG will generate a reset. Also, if any value other than 0x0055 or 0x00AA is written, the CRG immediately generates a reset. In case windowed COP operation is enabled
MC9S12HZ256 Data Sheet, Rev. 2.05 200 Freescale Semiconductor
Chapter 5 Clocks and Reset Generator (CRGV4)
writes (0x0055 or 0x00AA) to the ARMCOP register must occur in the last 25% of the selected time-out period. A premature write the CRG will immediately generate a reset. As soon as the reset sequence is completed the reset generator checks the reset condition. If no clock monitor failure is indicated and the latched state of the COP timeout is true, processing begins by fetching the COP vector.
5.5.3
Power-On Reset, Low Voltage Reset
The on-chip voltage regulator detects when VDD to the MCU has reached a certain level and asserts power-on reset or low voltage reset or both. As soon as a power-on reset or low voltage reset is triggered the CRG performs a quality check on the incoming clock signal. As soon as clock quality check indicates a valid oscillator clock signal the reset sequence starts using the oscillator clock. If after 50 check windows the clock quality check indicated a non-valid oscillator clock the reset sequence starts using self-clock mode. Figure 5-26 and Figure 5-27 show the power-up sequence for cases when the RESET pin is tied to VDD and when the RESET pin is held low.
RESET
Clock Quality Check (no Self-Clock Mode) )(
Internal POR )( 128 SYSCLK Internal RESET )( 64 SYSCLK
Figure 5-26. RESET Pin Tied to VDD (by a Pull-Up Resistor)
RESET
Clock Quality Check (no Self-Clock Mode) )(
Internal POR )( 128 SYSCLK Internal RESET )( 64 SYSCLK
Figure 5-27. RESET Pin Held Low Externally
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 201
Chapter 5 Clocks and Reset Generator (CRGV4)
5.6
Interrupts
The interrupts/reset vectors requested by the CRG are listed in Table 5-15. Refer to the device overview chapter for related vector addresses and priorities.
Table 5-15. CRG Interrupt Vectors
Interrupt Source Real-time interrupt LOCK interrupt SCM interrupt CCR Mask I bit I bit I bit Local Enable CRGINT (RTIE) CRGINT (LOCKIE) CRGINT (SCMIE)
5.6.1
Real-Time Interrupt
The CRG generates a real-time interrupt when the selected interrupt time period elapses. RTI interrupts are locally disabled by setting the RTIE bit to 0. The real-time interrupt flag (RTIF) is set to 1 when a timeout occurs, and is cleared to 0 by writing a 1 to the RTIF bit. The RTI continues to run during pseudo-stop mode if the PRE bit is set to 1. This feature can be used for periodic wakeup from pseudo-stop if the RTI interrupt is enabled.
5.6.2
PLL Lock Interrupt
The CRG generates a PLL lock interrupt when the LOCK condition of the PLL has changed, either from a locked state to an unlocked state or vice versa. Lock interrupts are locally disabled by setting the LOCKIE bit to 0. The PLL Lock interrupt flag (LOCKIF) is set to1 when the LOCK condition has changed, and is cleared to 0 by writing a 1 to the LOCKIF bit.
5.6.3
Self-Clock Mode Interrupt
The CRG generates a self-clock mode interrupt when the SCM condition of the system has changed, either entered or exited self-clock mode. SCM conditions can only change if the self-clock mode enable bit (SCME) is set to 1. SCM conditions are caused by a failing clock quality check after power-on reset (POR) or low voltage reset (LVR) or recovery from full stop mode (PSTP = 0) or clock monitor failure. For details on the clock quality check refer to Section 5.4.4, "Clock Quality Checker." If the clock monitor is enabled (CME = 1) a loss of external clock will also cause a SCM condition (SCME = 1). SCM interrupts are locally disabled by setting the SCMIE bit to 0. The SCM interrupt flag (SCMIF) is set to 1 when the SCM condition has changed, and is cleared to 0 by writing a 1 to the SCMIF bit.
MC9S12HZ256 Data Sheet, Rev. 2.05 202 Freescale Semiconductor
Chapter 6 Oscillator (OSCV2)
6.1 Introduction
The OSC module provides two alternative oscillator concepts: * A low noise and low power Colpitts oscillator with amplitude limitation control (ALC) * A robust full swing Pierce oscillator with the possibility to feed in an external square wave
6.1.1
Features
The Colpitts OSC option provides the following features: * Amplitude limitation control (ALC) loop: -- Low power consumption and low current induced RF emission -- Sinusoidal waveform with low RF emission -- Low crystal stress (an external damping resistor is not required) -- Normal and low amplitude mode for further reduction of power and emission * An external biasing resistor is not required The Pierce OSC option provides the following features: * Wider high frequency operation range * No DC voltage applied across the crystal * Full rail-to-rail (2.5 V nominal) swing oscillation with low EM susceptibility * Fast start up Common features: * Clock monitor (CM) * Operation from the VDDPLL 2.5 V (nominal) supply rail
6.1.2
Modes of Operation
Two modes of operation exist: * Amplitude limitation controlled Colpitts oscillator mode suitable for power and emission critical applications * Full swing Pierce oscillator mode that can also be used to feed in an externally generated square wave suitable for high frequency operation and harsh environments
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 203
Chapter 6 Oscillator (OSCV2)
6.2
External Signal Description
This section lists and describes the signals that connect off chip.
6.2.1
VDDPLL and VSSPLL -- PLL Operating Voltage, PLL Ground
These pins provide the operating voltage (VDDPLL) and ground (VSSPLL) for the OSC circuitry. This allows the supply voltage to the OSC to be independently bypassed.
6.2.2
EXTAL and XTAL -- Clock/Crystal Source Pins
These pins provide the interface for either a crystal or a CMOS compatible clock to control the internal clock generator circuitry. EXTAL is the external clock input or the input to the crystal oscillator amplifier. XTAL is the output of the crystal oscillator amplifier. All the MCU internal system clocks are derived from the EXTAL input frequency. In full stop mode (PSTP = 0) the EXTAL pin is pulled down by an internal resistor of typical 200 k. NOTE Freescale Semiconductor recommends an evaluation of the application board and chosen resonator or crystal by the resonator or crystal supplier. The Crystal circuit is changed from standard. The Colpitts circuit is not suited for overtone resonators and crystals.
EXTAL CDC* MCU XTAL C2 VSSPLL * Due to the nature of a translated ground Colpitts oscillator a DC voltage bias is applied to the crystal. Please contact the crystal manufacturer for crystal DC bias conditions and recommended capacitor value CDC. C1 Crystal or Ceramic Resonator
Figure 6-1. Colpitts Oscillator Connections (XCLKS = 0)
NOTE The Pierce circuit is not suited for overtone resonators and crystals without a careful component selection.
MC9S12HZ256 Data Sheet, Rev. 2.05 204 Freescale Semiconductor
Chapter 6 Oscillator (OSCV2)
EXTAL MCU RS* XTAL C4 VSSPLL * Rs can be zero (shorted) when used with higher frequency crystals. Refer to manufacturer's data. C3 Crystal or Ceramic Resonator
RB
Figure 6-2. Pierce Oscillator Connections (XCLKS = 1)
EXTAL MCU XTAL
CMOS-Compatible External Oscillator (VDDPLL Level)
Not Connected
Figure 6-3. External Clock Connections (XCLKS = 1)
6.2.3
XCLKS -- Colpitts/Pierce Oscillator Selection Signal
The XCLKS is an input signal which controls whether a crystal in combination with the internal Colpitts (low power) oscillator is used or whether the Pierce oscillator/external clock circuitry is used. The XCLKS signal is sampled during reset with the rising edge of RESET. Table 6-1 lists the state coding of the sampled XCLKS signal. Refer to the device overview chapter for polarity of the XCLKS pin.
Table 6-1. Clock Selection Based on XCLKS XCLKS
0 1
Description
Colpitts oscillator selected Pierce oscillator/external clock selected
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 205
Chapter 6 Oscillator (OSCV2)
6.3
Memory Map and Register Definition
The CRG contains the registers and associated bits for controlling and monitoring the OSC module.
6.4
Functional Description
The OSC block has two external pins, EXTAL and XTAL. The oscillator input pin, EXTAL, is intended to be connected to either a crystal or an external clock source. The selection of Colpitts oscillator or Pierce oscillator/external clock depends on the XCLKS signal which is sampled during reset. The XTAL pin is an output signal that provides crystal circuit feedback. A buffered EXTAL signal, OSCCLK, becomes the internal reference clock. To improve noise immunity, the oscillator is powered by the VDDPLL and VSSPLL power supply pins. The Pierce oscillator can be used for higher frequencies compared to the low power Colpitts oscillator.
6.4.1
Amplitude Limitation Control (ALC)
The Colpitts oscillator is equipped with a feedback system which does not waste current by generating harmonics. Its configuration is "Colpitts oscillator with translated ground." The transconductor used is driven by a current source under the control of a peak detector which will measure the amplitude of the AC signal appearing on EXTAL node in order to implement an amplitude limitation control (ALC) loop. The ALC loop is in charge of reducing the quiescent current in the transconductor as a result of an increase in the oscillation amplitude. The oscillation amplitude can be limited to two values. The normal amplitude which is intended for non power saving modes and a small amplitude which is intended for low power operation modes. Please refer to the CRG block description chapter for the control and assignment of the amplitude value to operation modes.
6.4.2
Clock Monitor (CM)
The clock monitor circuit is based on an internal resistor-capacitor (RC) time delay so that it can operate without any MCU clocks. If no OSCCLK edges are detected within this RC time delay, the clock monitor indicates a failure which asserts self clock mode or generates a system reset depending on the state of SCME bit. If the clock monitor is disabled or the presence of clocks is detected no failure is indicated.The clock monitor function is enabled/disabled by the CME control bit, described in the CRG block description chapter.
6.5
Interrupts
OSC contains a clock monitor, which can trigger an interrupt or reset. The control bits and status bits for the clock monitor are described in the CRG block description chapter.
MC9S12HZ256 Data Sheet, Rev. 2.05 206 Freescale Semiconductor
Chapter 7 Analog-to-Digital Converter (ATD10B16CV4)
7.1 Introduction
The ATD10B16C is a 16-channel, 10-bit, multiplexed input successive approximation analog-to-digital converter. Refer to the Electrical Specifications chapter for ATD accuracy.
7.1.1
* * * * * * * * * * * * *
Features
8-/10-bit resolution 7 s, 10-bit single conversion time Sample buffer amplifier Programmable sample time Left/right justified, signed/unsigned result data External trigger control Conversion completion interrupt generation Analog input multiplexer for 16 analog input channels Analog/digital input pin multiplexing 1 to 16 conversion sequence lengths Continuous conversion mode Multiple channel scans Configurable external trigger functionality on any AD channel or any of four additional trigger inputs. The four additional trigger inputs can be chip external or internal. Refer to device specification for availability and connectivity Configurable location for channel wrap around (when converting multiple channels in a sequence)
*
7.1.2
Modes of Operation
There is software programmable selection between performing single or continuous conversion on a single channel or multiple channels.
7.1.3
Block Diagram
Refer to Figure 7-1 for a block diagram of the ATD0B16C block.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 207
Chapter 7 Analog-to-Digital Converter (ATD10B16CV4)
Bus Clock
Clock Prescaler Trigger Mux
ATD clock
ATD10B16C
ETRIG0 ETRIG1 ETRIG2 ETRIG3 (see Device Overview chapter for availability and connectivity) ATDCTL1
Mode and Timing Control
Sequence Complete Interrupt
ATDDIEN
VDDA VSSA VRH VRL AN15 AN14 AN13 AN12 AN11 AN10 AN9 AN8 Analog MUX
PORTAD Successive Approximation Register (SAR) and DAC
Results ATD 0 ATD 1 ATD 2 ATD 3 ATD 4 ATD 5 ATD 6 ATD 7 ATD 8 ATD 9 ATD 10 ATD 11 ATD 12 ATD 13 ATD 14 ATD 15
+ Sample & Hold 1 1 Comparator
AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0
Figure 7-1. ATD10B16C Block Diagram
MC9S12HZ256 Data Sheet, Rev. 2.05 208 Freescale Semiconductor
Chapter 7 Analog-to-Digital Converter (ATD10B16CV4)
7.2
External Signal Description
This section lists all inputs to the ATD10B16C block.
7.2.1
ANx (x = 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) -- Analog Input Channel x Pins
This pin serves as the analog input channel x. It can also be configured as general-purpose digital input and/or external trigger for the ATD conversion.
7.2.2
ETRIG3, ETRIG2, ETRIG1, ETRIG0 -- External Trigger Pins
These inputs can be configured to serve as an external trigger for the ATD conversion. Refer to the Device Overview chapter for availability and connectivity of these inputs.
7.2.3
VRH, VRL -- High Reference Voltage Pin, Low Reference Voltage Pin
VRH is the high reference voltage, VRL is the low reference voltage for ATD conversion.
7.2.4
VDDA, VSSA -- Analog Circuitry Power Supply Pins
These pins are the power supplies for the analog circuitry of the ATD10B16C block.
7.3
Memory Map and Register Definition
This section provides a detailed description of all registers accessible in the ATD10B16C.
7.3.1
Module Memory Map
Table 7-1 gives an overview of all ATD10B16C registers
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 209
Chapter 7 Analog-to-Digital Converter (ATD10B16CV4)
.
Table 7-1. ATD10B16C Memory Map
Address Offset 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C 0x000D 0x000E 0x000F 0x0010, 0x0011 0x0012, 0x0013 0x0014, 0x0015 0x0016, 0x0017 0x0018, 0x0019 0x001A, 0x001B 0x001C, 0x001D 0x001E, 0x001F 0x0020, 0x0021 0x0022, 0x0023 0x0024, 0x0025 0x0026, 0x0027 0x0028, 0x0029 0x002A, 0x002B 0x002C, 0x002D 0x002E, 0x002F
1
Use ATD Control Register 0 (ATDCTL0) ATD Control Register 1 (ATDCTL1) ATD Control Register 2 (ATDCTL2) ATD Control Register 3 (ATDCTL3) ATD Control Register 4 (ATDCTL4) ATD Control Register 5 (ATDCTL5) ATD Status Register 0 (ATDSTAT0) Unimplemented ATD Test Register 0 (ATDTEST0)1 ATD Test Register 1 (ATDTEST1) ATD Status Register 2 (ATDSTAT2) ATD Status Register 1 (ATDSTAT1) ATD Input Enable Register 0 (ATDDIEN0) ATD Input Enable Register 1 (ATDDIEN1) Port Data Register 0 (PORTAD0) Port Data Register 1 (PORTAD1) ATD Result Register 0 (ATDDR0H, ATDDR0L) ATD Result Register 1 (ATDDR1H, ATDDR1L) ATD Result Register 2 (ATDDR2H, ATDDR2L) ATD Result Register 3 (ATDDR3H, ATDDR3L) ATD Result Register 4 (ATDDR4H, ATDDR4L) ATD Result Register 5 (ATDDR5H, ATDDR5L) ATD Result Register 6 (ATDDR6H, ATDDR6L) ATD Result Register 7 (ATDDR7H, ATDDR7L) ATD Result Register 8 (ATDDR8H, ATDDR8L) ATD Result Register 9 (ATDDR9H, ATDDR9L) ATD Result Register 10 (ATDDR10H, ATDDR10L) ATD Result Register 11 (ATDDR11H, ATDDR11L) ATD Result Register 12 (ATDDR12H, ATDDR12L) ATD Result Register 13 (ATDDR13H, ATDDR13L) ATD Result Register 14 (ATDDR14H, ATDDR14L) ATD Result Register 15 (ATDDR15H, ATDDR15L)
Access R/W R/W R/W R/W R/W R/W R/W R R/W R R R/W R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
ATDTEST0 is intended for factory test purposes only.
NOTE Register Address = Base Address + Address Offset, where the Base Address is defined at the MCU level and the Address Offset is defined at the module level.
MC9S12HZ256 Data Sheet, Rev. 2.05 210 Freescale Semiconductor
Chapter 7 Analog-to-Digital Converter (ATD10B16CV4)
7.3.2
Register Descriptions
This section describes in address order all the ATD10B16C registers and their individual bits.
Register Name 0x0000 ATDCTL0 R W R W R W R W R W R W R W R W R W R W R W R W R W IEN15 IEN14 IEN13 IEN12 IEN11 IEN10 IEN9 IEN8 CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0 CCF15 CCF14 CCF13 CCF12 CCF11 CCF10 CCF9 Unimplemented SC CCF8 Unimplemented SRES8 0 0 0 Bit 7 0 6 0 5 0 4 0 3 2 1 Bit 0
WRAP3
WRAP2
WRAP1
WRAP0
0x0001 ATDCTL1 0x0002 ATDCTL2 0x0003 ATDCTL3 0x0004 ATDCTL4 0x0005 ATDCTL5 0x0006 ATDSTAT0 0x0007 Unimplemented 0x0008 ATDTEST0 0x0009 ATDTEST1 0x000A ATDSTAT2 0x000B ATDSTAT1 0x000C ATDDIEN0
ETRIGSEL
ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0 ASCIF
ADPU 0
AFFC
AWAI
ETRIGLE
ETRIGP
ETRIGE
ASCIE
S8C
S4C
S2C
S1C
FIFO
FRZ1
FRZ0
SMP1
SMP0
PRS4
PRS3
PRS2
PRS1
PRS0
DJM
DSGN 0
SCAN
MULT
CD CC3
CC CC2
CB CC1
CA CC0
SCF
ETORF
FIFOR
= Unimplemented or Reserved
u = Unaffected
Figure 7-2. ATD Register Summary
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 211
Chapter 7 Analog-to-Digital Converter (ATD10B16CV4)
Register Name 0x000D ATDDIEN1 0x000E PORTAD0 0x000F PORTAD1 R W R W R W
Bit 7 IEN7 PTAD15
6 IEN6 PTAD14
5 IEN5 PTAD13
4 IEN4 PTAD12
3 IEN3 PTAD11
2 IEN2 PTAD10
1 IEN1 PTAD9
Bit 0 IEN0 PTAD8
PTAD7
PTAD6
PTAD5
PTAD4
PTAD3
PTAD2
PTAD1
PTAD0
R BIT 9 MSB BIT 7 MSB 0x0010-0x002F W ATDDRxH- ATDDRxL R W
BIT 8 BIT 6
BIT 7 BIT 5
BIT 6 BIT 4
BIT 5 BIT 3
BIT 4 BIT 2
BIT 3 BIT 1
BIT 2 BIT 0
BIT 1 u
BIT 0 u
0 0
0 0
0 0
0 0
0 0
0 0
= Unimplemented or Reserved
u = Unaffected
Figure 7-2. ATD Register Summary (continued)
7.3.2.1
ATD Control Register 0 (ATDCTL0)
Writes to this register will abort current conversion sequence but will not start a new sequence.
7 6 5 4 3 2 1 0
R W Reset
0
0
0
0 WRAP3 WRAP2 1 WRAP1 1 WRAP0 1
0
0
0
0
1
= Unimplemented or Reserved
Figure 7-3. ATD Control Register 0 (ATDCTL0)
Read: Anytime Write: Anytime
Table 7-2. ATDCTL0 Field Descriptions
Field 3:0 WRAP[3:0] Description Wrap Around Channel Select Bits -- These bits determine the channel for wrap around when doing multi-channel conversions. The coding is summarized in Table 7-3.
MC9S12HZ256 Data Sheet, Rev. 2.05 212 Freescale Semiconductor
Chapter 7 Analog-to-Digital Converter (ATD10B16CV4)
Table 7-3. Multi-Channel Wrap Around Coding
WRAP3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 WRAP2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 WRAP1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 WRAP0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Multiple Channel Conversions (MULT = 1) Wrap Around to AN0 after Converting Reserved AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15
7.3.2.2
ATD Control Register 1 (ATDCTL1)
Writes to this register will abort current conversion sequence but will not start a new sequence.
7 6 5 4 3 2 1 0
R ETRIGSEL W Reset 0
0
0
0 ETRIGCH3 ETRIGCH2 1 ETRIGCH1 1 ETRIGCH0 1
0
0
0
1
= Unimplemented or Reserved
Figure 7-4. ATD Control Register 1 (ATDCTL1)
Read: Anytime Write: Anytime
Table 7-4. ATDCTL1 Field Descriptions
Field 7 ETRIGSEL Description External Trigger Source Select -- This bit selects the external trigger source to be either one of the AD channels or one of the ETRIG[3:0] inputs. See device specification for availability and connectivity of ETRIG[3:0] inputs. If ETRIG[3:0] input option is not available, writing a 1 to ETRISEL only sets the bit but has no effect, that means one of the AD channels (selected by ETRIGCH[3:0]) remains the source for external trigger. The coding is summarized in Table 7-5.
3:0 External Trigger Channel Select -- These bits select one of the AD channels or one of the ETRIG[3:0] inputs ETRIGCH[3:0] as source for the external trigger. The coding is summarized in Table 7-5.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 213
Chapter 7 Analog-to-Digital Converter (ATD10B16CV4)
Table 7-5. External Trigger Channel Select Coding
ETRIGSEL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1
1
ETRIGCH3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 1
ETRIGCH2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 X
ETRIGCH1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X X
ETRIGCH0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X X
External Trigger Source AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 ETRIG01 ETRIG11 ETRIG21 ETRIG31 Reserved Reserved
Only if ETRIG[3:0] input option is available (see device specification), else ETRISEL is ignored, that means external trigger source remains on one of the AD channels selected by ETRIGCH[3:0]
7.3.2.3
ATD Control Register 2 (ATDCTL2)
This register controls power down, interrupt and external trigger. Writes to this register will abort current conversion sequence but will not start a new sequence.
MC9S12HZ256 Data Sheet, Rev. 2.05 214 Freescale Semiconductor
Chapter 7 Analog-to-Digital Converter (ATD10B16CV4)
7
6
5
4
3
2
1
0
R ADPU W Reset 0 0 0 0 0 0 0 AFFC AWAI ETRIGLE ETRIGP ETRIGE ASCIE
ASCIF
0
= Unimplemented or Reserved
Figure 7-5. ATD Control Register 2 (ATDCTL2)
Read: Anytime Write: Anytime
Table 7-6. ATDCTL2 Field Descriptions
Field 7 ADPU Description ATD Power Down -- This bit provides on/off control over the ATD10B16C block allowing reduced MCU power consumption. Because analog electronic is turned off when powered down, the ATD requires a recovery time period after ADPU bit is enabled. 0 Power down ATD 1 Normal ATD functionality ATD Fast Flag Clear All 0 ATD flag clearing operates normally (read the status register ATDSTAT1 before reading the result register to clear the associate CCF flag). 1 Changes all ATD conversion complete flags to a fast clear sequence. Any access to a result register will cause the associate CCF flag to clear automatically. ATD Power Down in Wait Mode -- When entering Wait Mode this bit provides on/off control over the ATD10B16C block allowing reduced MCU power. Because analog electronic is turned off when powered down, the ATD requires a recovery time period after exit from Wait mode. 0 ATD continues to run in Wait mode 1 Halt conversion and power down ATD during Wait mode After exiting Wait mode with an interrupt conversion will resume. But due to the recovery time the result of this conversion should be ignored. External Trigger Level/Edge Control -- This bit controls the sensitivity of the external trigger signal. See Table 7-7 for details. External Trigger Polarity -- This bit controls the polarity of the external trigger signal. See Table 7-7 for details. External Trigger Mode Enable -- This bit enables the external trigger on one of the AD channels or one of the ETRIG[3:0] inputs as described in Table 7-5. If external trigger source is one of the AD channels, the digital input buffer of this channel is enabled. The external trigger allows to synchronize the start of conversion with external events. 0 Disable external trigger 1 Enable external trigger ATD Sequence Complete Interrupt Enable 0 ATD Sequence Complete interrupt requests are disabled. 1 ATD Interrupt will be requested whenever ASCIF = 1 is set. ATD Sequence Complete Interrupt Flag -- If ASCIE = 1 the ASCIF flag equals the SCF flag (see Section 7.3.2.7, "ATD Status Register 0 (ATDSTAT0)"), else ASCIF reads zero. Writes have no effect. 0 No ATD interrupt occurred 1 ATD sequence complete interrupt pending
6 AFFC
5 AWAI
4 ETRIGLE 3 ETRIGP 2 ETRIGE
1 ASCIE 0 ASCIF
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 215
Chapter 7 Analog-to-Digital Converter (ATD10B16CV4)
Table 7-7. External Trigger Configurations
ETRIGLE 0 0 1 1 ETRIGP 0 1 0 1 External Trigger Sensitivity Falling Edge Ring Edge Low Level High Level
MC9S12HZ256 Data Sheet, Rev. 2.05 216 Freescale Semiconductor
Chapter 7 Analog-to-Digital Converter (ATD10B16CV4)
7.3.2.4
ATD Control Register 3 (ATDCTL3)
This register controls the conversion sequence length, FIFO for results registers and behavior in Freeze Mode. Writes to this register will abort current conversion sequence but will not start a new sequence.
7 6 5 4 3 2 1 0
R W Reset
0 S8C 0 0 S4C 1 S2C 0 S1C 0 FIFO 0 FRZ1 0 FRZ0 0
= Unimplemented or Reserved
Figure 7-6. ATD Control Register 3 (ATDCTL3)
Read: Anytime Write: Anytime
Table 7-8. ATDCTL3 Field Descriptions
Field 6 S8C 5 S4C 4 S2C 3 S1C Description Conversion Sequence Length -- This bit controls the number of conversions per sequence. Table 7-9 shows all combinations. At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity to HC12 Family. Conversion Sequence Length -- This bit controls the number of conversions per sequence. Table 7-9 shows all combinations. At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity to HC12 Family. Conversion Sequence Length -- This bit controls the number of conversions per sequence. Table 7-9 shows all combinations. At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity to HC12 Family. Conversion Sequence Length -- This bit controls the number of conversions per sequence. Table 7-9 shows all combinations. At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity to HC12 Family.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 217
Chapter 7 Analog-to-Digital Converter (ATD10B16CV4)
Table 7-8. ATDCTL3 Field Descriptions (continued)
Field 2 FIFO Description Result Register FIFO Mode --If this bit is zero (non-FIFO mode), the A/D conversion results map into the result registers based on the conversion sequence; the result of the first conversion appears in the first result register, the second result in the second result register, and so on. If this bit is one (FIFO mode) the conversion counter is not reset at the beginning or ending of a conversion sequence; sequential conversion results are placed in consecutive result registers. In a continuously scanning conversion sequence, the result register counter will wrap around when it reaches the end of the result register file. The conversion counter value (CC3-0 in ATDSTAT0) can be used to determine where in the result register file, the current conversion result will be placed. Aborting a conversion or starting a new conversion by write to an ATDCTL register (ATDCTL5-0) clears the conversion counter even if FIFO=1. So the first result of a new conversion sequence, started by writing to ATDCTL5, will always be place in the first result register (ATDDDR0). Intended usage of FIFO mode is continuos conversion (SCAN=1) or triggered conversion (ETRIG=1). Finally, which result registers hold valid data can be tracked using the conversion complete flags. Fast flag clear mode may or may not be useful in a particular application to track valid data. 0 Conversion results are placed in the corresponding result register up to the selected sequence length. 1 Conversion results are placed in consecutive result registers (wrap around at end). Background Debug Freeze Enable -- When debugging an application, it is useful in many cases to have the ATD pause when a breakpoint (Freeze Mode) is encountered. These 2 bits determine how the ATD will respond to a breakpoint as shown in Table 7-10. Leakage onto the storage node and comparator reference capacitors may compromise the accuracy of an immediately frozen conversion depending on the length of the freeze period.
1:0 FRZ[1:0]
Table 7-9. Conversion Sequence Length Coding
S8C 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 S4C 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 S2C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 S1C 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Number of Conversions per Sequence 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MC9S12HZ256 Data Sheet, Rev. 2.05 218 Freescale Semiconductor
Chapter 7 Analog-to-Digital Converter (ATD10B16CV4)
Table 7-10. ATD Behavior in Freeze Mode (Breakpoint)
FRZ1 0 0 1 1 FRZ0 0 1 0 1 Behavior in Freeze Mode Continue conversion Reserved Finish current conversion, then freeze Freeze Immediately
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 219
Chapter 7 Analog-to-Digital Converter (ATD10B16CV4)
7.3.2.5
ATD Control Register 4 (ATDCTL4)
This register selects the conversion clock frequency, the length of the second phase of the sample time and the resolution of the A/D conversion (i.e., 8-bits or 10-bits). Writes to this register will abort current conversion sequence but will not start a new sequence.
7 6 5 4 3 2 1 0
R SRES8 W Reset 0 0 0 0 0 1 0 1 SMP1 SMP0 PRS4 PRS3 PRS2 PRS1 PRS0
Figure 7-7. ATD Control Register 4 (ATDCTL4)
Read: Anytime Write: Anytime
Table 7-11. ATDCTL4 Field Descriptions
Field 7 SRES8 Description A/D Resolution Select -- This bit selects the resolution of A/D conversion results as either 8 or 10 bits. The A/D converter has an accuracy of 10 bits. However, if low resolution is required, the conversion can be speeded up by selecting 8-bit resolution. 0 10 bit resolution 1 8 bit resolution Sample Time Select --These two bits select the length of the second phase of the sample time in units of ATD conversion clock cycles. Note that the ATD conversion clock period is itself a function of the prescaler value (bits PRS4-0). The sample time consists of two phases. The first phase is two ATD conversion clock cycles long and transfers the sample quickly (via the buffer amplifier) onto the A/D machine's storage node. The second phase attaches the external analog signal directly to the storage node for final charging and high accuracy. Table 7-12 lists the lengths available for the second sample phase. ATD Clock Prescaler -- These 5 bits are the binary value prescaler value PRS. The ATD conversion clock frequency is calculated as follows: [ BusClock ] ATDclock = ------------------------------- x 0.5 [ PRS + 1 ] Note: The maximum ATD conversion clock frequency is half the bus clock. The default (after reset) prescaler value is 5 which results in a default ATD conversion clock frequency that is bus clock divided by 12. Table 7-13 illustrates the divide-by operation and the appropriate range of the bus clock.
6:5 SMP[1:0]
4:0 PRS[4:0]
Table 7-12. Sample Time Select
SMP1 0 0 1 1 SMP0 0 1 0 1 Length of 2nd Phase of Sample Time 2 A/D conversion clock periods 4 A/D conversion clock periods 8 A/D conversion clock periods 16 A/D conversion clock periods
MC9S12HZ256 Data Sheet, Rev. 2.05 220 Freescale Semiconductor
Chapter 7 Analog-to-Digital Converter (ATD10B16CV4)
Table 7-13. Clock Prescaler Values
Prescale Value 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111
1
Total Divisor Value Divide by 2 Divide by 4 Divide by 6 Divide by 8 Divide by 10 Divide by 12 Divide by 14 Divide by 16 Divide by 18 Divide by 20 Divide by 22 Divide by 24 Divide by 26 Divide by 28 Divide by 30 Divide by 32 Divide by 34 Divide by 36 Divide by 38 Divide by 40 Divide by 42 Divide by 44 Divide by 46 Divide by 48 Divide by 50 Divide by 52 Divide by 54 Divide by 56 Divide by 58 Divide by 60 Divide by 62 Divide by 64
Max. Bus Clock1 4 MHz 8 MHz 12 MHz 16 MHz 20 MHz 24 MHz 28 MHz 32 MHz 36 MHz 40 MHz 44 MHz 48 MHz 52 MHz 56 MHz 60 MHz 64 MHz 68 MHz 72 MHz 76 MHz 80 MHz 84 MHz 88 MHz 92 MHz 96 MHz 100 MHz 104 MHz 108 MHz 112 MHz 116 MHz 120 MHz 124 MHz 128 MHz
Min. Bus Clock2 1 MHz 2 MHz 3 MHz 4 MHz 5 MHz 6 MHz 7 MHz 8 MHz 9 MHz 10 MHz 11 MHz 12 MHz 13 MHz 14 MHz 15 MHz 16 MHz 17 MHz 18 MHz 19 MHz 20 MHz 21 MHz 22 MHz 23 MHz 24 MHz 25 MHz 26 MHz 27 MHz 28 MHz 29 MHz 30 MHz 31 MHz 32 MHz
Maximum ATD conversion clock frequency is 2 MHz. The maximum allowed bus clock frequency is shown in this column. 2 Minimum ATD conversion clock frequency is 500 kHz. The minimum allowed bus clock frequency is shown in this column.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 221
Chapter 7 Analog-to-Digital Converter (ATD10B16CV4)
7.3.2.6
ATD Control Register 5 (ATDCTL5)
This register selects the type of conversion sequence and the analog input channels sampled. Writes to this register will abort current conversion sequence and start a new conversion sequence. If external trigger is enabled (ETRIGE = 1) an initial write to ATDCTL5 is required to allow starting of a conversion sequence which will then occur on each trigger event. Start of conversion means the beginning of the sampling phase.
7 6 5 4 3 2 1 0
R DJM W Reset 0 0 0 0 0 0 0 0 DSGN SCAN MULT CD CC CB CA
Figure 7-8. ATD Control Register 5 (ATDCTL5)
Read: Anytime Write: Anytime
Table 7-14. ATDCTL5 Field Descriptions
Field 7 DJM Description Result Register Data Justification -- This bit controls justification of conversion data in the result registers. See Section 7.3.2.16, "ATD Conversion Result Registers (ATDDRx)" for details. 0 Left justified data in the result registers. 1 Right justified data in the result registers. Result Register Data Signed or Unsigned Representation -- This bit selects between signed and unsigned conversion data representation in the result registers. Signed data is represented as 2's complement. Signed data is not available in right justification. See 7.3.2.16 ATD Conversion Result Registers (ATDDRx) for details. 0 Unsigned data representation in the result registers. 1 Signed data representation in the result registers. Table 7-15 summarizes the result data formats available and how they are set up using the control bits. Table 7-16 illustrates the difference between the signed and unsigned, left justified output codes for an input signal range between 0 and 5.12 Volts. Continuous Conversion Sequence Mode -- This bit selects whether conversion sequences are performed continuously or only once. If external trigger is enabled (ETRIGE=1) setting this bit has no effect, that means each trigger event starts a single conversion sequence. 0 Single conversion sequence 1 Continuous conversion sequences (scan mode) Multi-Channel Sample Mode -- When MULT is 0, the ATD sequence controller samples only from the specified analog input channel for an entire conversion sequence. The analog channel is selected by channel selection code (control bits CD/CC/CB/CA located in ATDCTL5). When MULT is 1, the ATD sequence controller samples across channels. The number of channels sampled is determined by the sequence length value (S8C, S4C, S2C, S1C). The first analog channel examined is determined by channel selection code (CC, CB, CA control bits); subsequent channels sampled in the sequence are determined by incrementing the channel selection code or wrapping around to AN0 (channel 0. 0 Sample only one channel 1 Sample across several channels
6 DSGN
5 SCAN
4 MULT
MC9S12HZ256 Data Sheet, Rev. 2.05 222 Freescale Semiconductor
Chapter 7 Analog-to-Digital Converter (ATD10B16CV4)
Table 7-14. ATDCTL5 Field Descriptions (continued)
Field 3:0 C[D:A} Description Analog Input Channel Select Code -- These bits select the analog input channel(s) whose signals are sampled and converted to digital codes. Table 7-17 lists the coding used to select the various analog input channels. In the case of single channel conversions (MULT = 0), this selection code specified the channel to be examined. In the case of multiple channel conversions (MULT = 1), this selection code represents the first channel to be examined in the conversion sequence. Subsequent channels are determined by incrementing the channel selection code or wrapping around to AN0 (after converting the channel defined by the Wrap Around Channel Select Bits WRAP[3:0] in ATDCTL0). In case starting with a channel number higher than the one defined by WRAP[3:0] the first wrap around will be AN15 to AN0.
Table 7-15. Available Result Data Formats.
SRES8 1 1 1 0 0 0 DJM 0 0 1 0 0 1 DSGN 0 1 X 0 1 X Result Data Formats Description and Bus Bit Mapping 8-bit / left justified / unsigned -- bits 15:8 8-bit / left justified / signed -- bits 15:8 8-bit / right justified / unsigned -- bits 7:0 10-bit / left justified / unsigned -- bits 15:6 10-bit / left justified / signed --- bits 15:6 10-bit / right justified / unsigned -- bits 9:0
Table 7-16. Left Justified, Signed and Unsigned ATD Output Codes.
Input Signal VRL = 0 Volts VRH = 5.12 Volts 5.120 Volts 5.100 5.080 2.580 2.560 2.540 0.020 0.000 Signed 8-Bit Codes 7F 7F 7E 01 00 FF 81 80 Unsigned 8-Bit Codes FF FF FE 81 80 7F 01 00 Signed 10-Bit Codes 7FC0 7F00 7E00 0100 0000 FF00 8100 8000 Unsigned 10-Bit Codes FFC0 FF00 FE00 8100 8000 7F00 0100 0000
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 223
Chapter 7 Analog-to-Digital Converter (ATD10B16CV4)
Table 7-17. Analog Input Channel Select Coding
CD 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 CC 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 CB 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 CA 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Analog Input Channel AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15
MC9S12HZ256 Data Sheet, Rev. 2.05 224 Freescale Semiconductor
Chapter 7 Analog-to-Digital Converter (ATD10B16CV4)
7.3.2.7
ATD Status Register 0 (ATDSTAT0)
This read-only register contains the Sequence Complete Flag, overrun flags for external trigger and FIFO mode, and the conversion counter.
7 6 5 4 3 2 1 0
R SCF W Reset 0
0 ETORF 0 0 FIFOR 0
CC3
CC2
CC1
CC0
0
0
0
0
= Unimplemented or Reserved
Figure 7-9. ATD Status Register 0 (ATDSTAT0)
Read: Anytime Write: Anytime (No effect on CC[3:0])
Table 7-18. ATDSTAT0 Field Descriptions
Field 7 SCF Description Sequence Complete Flag -- This flag is set upon completion of a conversion sequence. If conversion sequences are continuously performed (SCAN = 1), the flag is set after each one is completed. This flag is cleared when one of the following occurs: * Write "1" to SCF * Write to ATDCTL5 (a new conversion sequence is started) * If AFFC = 1 and read of a result register 0 Conversion sequence not completed 1 Conversion sequence has completed External Trigger Overrun Flag --While in edge trigger mode (ETRIGLE = 0), if additional active edges are detected while a conversion sequence is in process the overrun flag is set. This flag is cleared when one of the following occurs: * Write "1" to ETORF * Write to ATDCTL0,1,2,3,4 (a conversion sequence is aborted) * Write to ATDCTL5 (a new conversion sequence is started) 0 No External trigger over run error has occurred 1 External trigger over run error has occurred
5 ETORF
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 225
Chapter 7 Analog-to-Digital Converter (ATD10B16CV4)
Table 7-18. ATDSTAT0 Field Descriptions (continued)
Field 4 FIFOR Description FIFO Over Run Flag -- This bit indicates that a result register has been written to before its associated conversion complete flag (CCF) has been cleared. This flag is most useful when using the FIFO mode because the flag potentially indicates that result registers are out of sync with the input channels. However, it is also practical for non-FIFO modes, and indicates that a result register has been over written before it has been read (i.e., the old data has been lost). This flag is cleared when one of the following occurs: * Write "1" to FIFOR * Start a new conversion sequence (write to ATDCTL5 or external trigger) 0 No over run has occurred 1 Overrun condition exists (result register has been written while associated CCFx flag remained set) Conversion Counter -- These 4 read-only bits are the binary value of the conversion counter. The conversion counter points to the result register that will receive the result of the current conversion. For example, CC3 = 0, CC2 = 1, CC1 = 1, CC0 = 0 indicates that the result of the current conversion will be in ATD Result Register 6. If in non-FIFO mode (FIFO = 0) the conversion counter is initialized to zero at the begin and end of the conversion sequence. If in FIFO mode (FIFO = 1) the register counter is not initialized. The conversion counters wraps around when its maximum value is reached. Aborting a conversion or starting a new conversion by write to an ATDCTL register (ATDCTL5-0) clears the conversion counter even if FIFO=1.
3:0 CC[3:0}
MC9S12HZ256 Data Sheet, Rev. 2.05 226 Freescale Semiconductor
Chapter 7 Analog-to-Digital Converter (ATD10B16CV4)
7.3.2.8
Reserved Register 0 (ATDTEST0)
7 6 5 4 3 2 1 0
R W Reset
u
u
u
u
u
u
u
u
1
0
0
0
0
0
0
0
= Unimplemented or Reserved
u = Unaffected
Figure 7-10. Reserved Register 0 (ATDTEST0)
Read: Anytime, returns unpredictable values Write: Anytime in special modes, unimplemented in normal modes NOTE Writing to this register when in special modes can alter functionality.
7.3.2.9
ATD Test Register 1 (ATDTEST1)
This register contains the SC bit used to enable special channel conversions.
7 6 5 4 3 2 1 0
R W Reset
u
u
u
u
u
u
u SC
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
u = Unaffected
Figure 7-11. Reserved Register 1 (ATDTEST1)
Read: Anytime, returns unpredictable values for bit 7 and bit 6 Write: Anytime NOTE Writing to this register when in special modes can alter functionality.
Table 7-19. ATDTEST1 Field Descriptions
Field 0 SC Description Special Channel Conversion Bit -- If this bit is set, then special channel conversion can be selected using CC, CB, and CA of ATDCTL5. Table 7-20 lists the coding. 0 Special channel conversions disabled 1 Special channel conversions enabled
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 227
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Table 7-20. Special Channel Select Coding
SC 1 1 1 1 1 1 CD 0 0 0 0 0 1 CC 0 1 1 1 1 X CB X 0 0 1 1 X CA X 0 1 0 1 X Analog Input Channel Reserved VRH VRL (VRH+VRL) / 2 Reserved Reserved
7.3.2.10
ATD Status Register 2 (ATDSTAT2)
This read-only register contains the Conversion Complete Flags CCF15 to CCF8.
7 6 5 4 3 2 1 0
R W Reset
CCF15
CCF14
CCF13
CCF12
CCF11
CCF10
CCF9
CCF8
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 7-12. ATD Status Register 2 (ATDSTAT2)
Read: Anytime Write: Anytime, no effect
Table 7-21. ATDSTAT2 Field Descriptions
Field 7:0 CCF[15:8] Description Conversion Complete Flag Bits -- A conversion complete flag is set at the end of each conversion in a conversion sequence. The flags are associated with the conversion position in a sequence (and also the result register number). Therefore, CCF8 is set when the ninth conversion in a sequence is complete and the result is available in result register ATDDR8; CCF9 is set when the tenth conversion in a sequence is complete and the result is available in ATDDR9, and so forth. A flag CCFx (x = 15, 14, 13, 12, 11, 10, 9, 8) is cleared when one of the following occurs: * Write to ATDCTL5 (a new conversion sequence is started) * If AFFC = 0 and read of ATDSTAT2 followed by read of result register ATDDRx * If AFFC = 1 and read of result register ATDDRx In case of a concurrent set and clear on CCFx: The clearing by method A) will overwrite the set. The clearing by methods B) or C) will be overwritten by the set. 0 Conversion number x not completed 1 Conversion number x has completed, result ready in ATDDRx
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7.3.2.11
ATD Status Register 1 (ATDSTAT1)
This read-only register contains the Conversion Complete Flags CCF7 to CCF0
7 6 5 4 3 2 1 0
R W Reset
CCF7
CCF6
CCF5
CCF4
CCF3
CCF2
CCF1
CCF0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 7-13. ATD Status Register 1 (ATDSTAT1)
Read: Anytime Write: Anytime, no effect
Table 7-22. ATDSTAT1 Field Descriptions
Field 7:0 CCF[7:0] Description Conversion Complete Flag Bits -- A conversion complete flag is set at the end of each conversion in a conversion sequence. The flags are associated with the conversion position in a sequence (and also the result register number). Therefore, CCF0 is set when the first conversion in a sequence is complete and the result is available in result register ATDDR0; CCF1 is set when the second conversion in a sequence is complete and the result is available in ATDDR1, and so forth. A CCF flag is cleared when one of the following occurs: * Write to ATDCTL5 (a new conversion sequence is started) * If AFFC = 0 and read of ATDSTAT1 followed by read of result register ATDDRx * If AFFC = 1 and read of result register ATDDRx In case of a concurrent set and clear on CCFx: The clearing by method A) will overwrite the set. The clearing by methods B) or C) will be overwritten by the set. Conversion number x not completed Conversion number x has completed, result ready in ATDDRx
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7.3.2.12
ATD Input Enable Register 0 (ATDDIEN0)
7 6 5 4 3 2 1 0
R IEN15 W Reset 0 0 0 0 0 0 0 0 IEN14 IEN13 IEN12 IEN11 IEN10 IEN9 IEN8
Figure 7-14. ATD Input Enable Register 0 (ATDDIEN0)
Read: Anytime Write: anytime
Table 7-23. ATDDIEN0 Field Descriptions
Field 7:0 IEN[15:8] Description ATD Digital Input Enable on Channel Bits -- This bit controls the digital input buffer from the analog input pin (ANx) to PTADx data register. 0 Disable digital input buffer to PTADx 1 Enable digital input buffer to PTADx. Note: Setting this bit will enable the corresponding digital input buffer continuously. If this bit is set while simultaneously using it as an analog port, there is potentially increased power consumption because the digital input buffer maybe in the linear region.
7.3.2.13
ATD Input Enable Register 1 (ATDDIEN1)
7 6 5 4 3 2 1 0
R IEN7 W Reset 0 0 0 0 0 0 0 0 IEN6 IEN5 IEN4 IEN3 IEN2 IEN1 IEN0
Figure 7-15. ATD Input Enable Register 1 (ATDDIEN1)
Read: Anytime Write: Anytime
Table 7-24. ATDDIEN1 Field Descriptions
Field 7:0 IEN[7:0] Description ATD Digital Input Enable on Channel Bits -- This bit controls the digital input buffer from the analog input pin (ANx) to PTADx data register. 0 Disable digital input buffer to PTADx 1 Enable digital input buffer to PTADx. Note: Setting this bit will enable the corresponding digital input buffer continuously. If this bit is set while simultaneously using it as an analog port, there is potentially increased power consumption because the digital input buffer maybe in the linear region.
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7.3.2.14
Port Data Register 0 (PORTAD0)
The data port associated with the ATD is input-only. The port pins are shared with the analog A/D inputs AN[15:8].
7 6 5 4 3 2 1 0
R W Reset Pin Function
PTAD15
PTAD14
PTAD13
PTAD12
PTAD11
PTAD10
PTAD9
PTAD8
1 AN15
1 AN14
1 AN13
1 AN12
1 AN11
1 AN10
1 AN9
1 AN8
= Unimplemented or Reserved
Figure 7-16. Port Data Register 0 (PORTAD0)
Read: Anytime Write: Anytime, no effect The A/D input channels may be used for general-purpose digital input.
Table 7-25. PORTAD0 Field Descriptions
Field 7:0 PTAD[15:8] Description A/D Channel x (ANx) Digital Input Bits-- If the digital input buffer on the ANx pin is enabled (IENx = 1) or channel x is enabled as external trigger (ETRIGE = 1, ETRIGCH[3-0] = x, ETRIGSEL = 0) read returns the logic level on ANx pin (signal potentials not meeting VIL or VIH specifications will have an indeterminate value)). If the digital input buffers are disabled (IENx = 0) and channel x is not enabled as external trigger, read returns a "1". Reset sets all PORTAD0 bits to "1".
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7.3.2.15
Port Data Register 1 (PORTAD1)
The data port associated with the ATD is input-only. The port pins are shared with the analog A/D inputs AN7-0.
7 6 5 4 3 2 1 0
R W Reset Pin Function
PTAD7
PTAD6
PTAD5
PTAD4
PTAD3
PTAD2
PTAD1
PTAD0
1 AN 7
1 AN6
1 AN5
1 AN4
1 AN3
1 AN2
1 AN1
1 AN0
= Unimplemented or Reserved
Figure 7-17. Port Data Register 1 (PORTAD1)
Read: Anytime Write: Anytime, no effect The A/D input channels may be used for general-purpose digital input.
Table 7-26. PORTAD1 Field Descriptions
Field 7:0 PTAD[7:8] Description A/D Channel x (ANx) Digital Input Bits -- If the digital input buffer on the ANx pin is enabled (IENx=1) or channel x is enabled as external trigger (ETRIGE = 1, ETRIGCH[3-0] = x, ETRIGSEL = 0) read returns the logic level on ANx pin (signal potentials not meeting VIL or VIH specifications will have an indeterminate value)). If the digital input buffers are disabled (IENx = 0) and channel x is not enabled as external trigger, read returns a "1". Reset sets all PORTAD1 bits to "1".
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7.3.2.16
ATD Conversion Result Registers (ATDDRx)
The A/D conversion results are stored in 16 read-only result registers. The result data is formatted in the result registers bases on two criteria. First there is left and right justification; this selection is made using the DJM control bit in ATDCTL5. Second there is signed and unsigned data; this selection is made using the DSGN control bit in ATDCTL5. Signed data is stored in 2's complement format and only exists in left justified format. Signed data selected for right justified format is ignored. Read: Anytime Write: Anytime in special mode, unimplemented in normal modes 7.3.2.16.1 Left Justified Result Data
7 6 5 4 3 2 1 0
R (10-BIT) BIT 9 MSB R (8-BIT) BIT 7 MSB W Reset 0
BIT 8 BIT 6
BIT 7 BIT 5
BIT 6 BIT 4
BIT 5 BIT 3
BIT 4 BIT 2
BIT 3 BIT 1
BIT 2 BIT 0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 7-18. Left Justified, ATD Conversion Result Register x, High Byte (ATDDRxH)
7 6 5 4 3 2 1 0
R (10-BIT) R (8-BIT) W Reset
BIT 1 u
BIT 0 u
0 0
0 0
0 0
0 0
0 0
0 0
0
0
0
0
0
0 u = Unaffected
0
0
= Unimplemented or Reserved
Figure 7-19. Left Justified, ATD Conversion Result Register x, Low Byte (ATDDRxL)
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7.3.2.16.2
Right Justified Result Data
7 6 5 4 3 2 1 0
R (10-BIT) R (8-BIT) W Reset
0 0
0 0
0 0
0 0
0 0
0 0
BIT 9 MSB 0
BIT 8 0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 7-20. Right Justified, ATD Conversion Result Register x, High Byte (ATDDRxH)
7 6 5 4 3 2 1 0
R (10-BIT) BIT 7 R (8-BIT) BIT 7 MSB W Reset 0
BIT 6 BIT 6
BIT 5 BIT 5
BIT 4 BIT 4
BIT 3 BIT 3
BIT 2 BIT 2
BIT 1 BIT 1
BIT 0 BIT 0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 7-21. Right Justified, ATD Conversion Result Register x, Low Byte (ATDDRxL)
7.4
Functional Description
The ATD10B16C is structured in an analog and a digital sub-block.
7.4.1
Analog Sub-block
The analog sub-block contains all analog electronics required to perform a single conversion. Separate power supplies VDDA and VSSA allow to isolate noise of other MCU circuitry from the analog sub-block.
7.4.1.1
Sample and Hold Machine
The sample and hold (S/H) machine accepts analog signals from the external world and stores them as capacitor charge on a storage node. The sample process uses a two stage approach. During the first stage, the sample amplifier is used to quickly charge the storage node.The second stage connects the input directly to the storage node to complete the sample for high accuracy. When not sampling, the sample and hold machine disables its own clocks. The analog electronics continue drawing their quiescent current. The power down (ADPU) bit must be set to disable both the digital clocks and the analog power consumption. The input analog signals are unipolar and must fall within the potential range of VSSA to VDDA.
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7.4.1.2
Analog Input Multiplexer
The analog input multiplexer connects one of the 16 external analog input channels to the sample and hold machine.
7.4.1.3
Sample Buffer Amplifier
The sample amplifier is used to buffer the input analog signal so that the storage node can be quickly charged to the sample potential.
7.4.1.4
Analog-to-Digital (A/D) Machine
The A/D machine performs analog to digital conversions. The resolution is program selectable at either 8 or 10 bits. The A/D machine uses a successive approximation architecture. It functions by comparing the stored analog sample potential with a series of digitally generated analog potentials. By following a binary search algorithm, the A/D machine locates the approximating potential that is nearest to the sampled potential. When not converting the A/D machine disables its own clocks. The analog electronics continue drawing quiescent current. The power down (ADPU) bit must be set to disable both the digital clocks and the analog power consumption. Only analog input signals within the potential range of VRL to VRH (A/D reference potentials) will result in a non-railed digital output codes.
7.4.2
Digital Sub-Block
This subsection explains some of the digital features in more detail. See register descriptions for all details.
7.4.2.1
External Trigger Input
The external trigger feature allows the user to synchronize ATD conversions to the external environment events rather than relying on software to signal the ATD module when ATD conversions are to take place. The external trigger signal (out of reset ATD channel 15, configurable in ATDCTL1) is programmable to be edge or level sensitive with polarity control. Table 7-27 gives a brief description of the different combinations of control bits and their effect on the external trigger function.
Table 7-27. External Trigger Control Bits
ETRIGLE X X 0 0 1 1 ETRIGP X X 0 1 0 1 ETRIGE 0 0 1 1 1 1 SCAN 0 1 X X X X Description Ignores external trigger. Performs one conversion sequence and stops. Ignores external trigger. Performs continuous conversion sequences. Falling edge triggered. Performs one conversion sequence per trigger. Rising edge triggered. Performs one conversion sequence per trigger. Trigger active low. Performs continuous conversions while trigger is active. Trigger active high. Performs continuous conversions while trigger is active.
During a conversion, if additional active edges are detected the overrun error flag ETORF is set.
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In either level or edge triggered modes, the first conversion begins when the trigger is received. In both cases, the maximum latency time is one bus clock cycle plus any skew or delay introduced by the trigger circuitry. After ETRIGE is enabled, conversions cannot be started by a write to ATDCTL5, but rather must be triggered externally. If the level mode is active and the external trigger both de-asserts and re-asserts itself during a conversion sequence, this does not constitute an overrun. Therefore, the flag is not set. If the trigger remains asserted in level mode while a sequence is completing, another sequence will be triggered immediately.
7.4.2.2
General-Purpose Digital Input Port Operation
The input channel pins can be multiplexed between analog and digital data. As analog inputs, they are multiplexed and sampled to supply signals to the A/D converter. As digital inputs, they supply external input data that can be accessed through the digital port registers (PORTAD0 & PORTAD1) (input-only). The analog/digital multiplex operation is performed in the input pads. The input pad is always connected to the analog inputs of the ATD10B16C. The input pad signal is buffered to the digital port registers. This buffer can be turned on or off with the ATDDIEN0 & ATDDIEN1 register. This is important so that the buffer does not draw excess current when analog potentials are presented at its input.
7.4.3
Operation in Low Power Modes
The ATD10B16C can be configured for lower MCU power consumption in three different ways: * Stop Mode Stop Mode: This halts A/D conversion. Exit from Stop mode will resume A/D conversion, But due to the recovery time the result of this conversion should be ignored. Entering stop mode causes all clocks to halt and thus the system is placed in a minimum power standby mode. This halts any conversion sequence in progress. During recovery from stop mode, there must be a minimum delay for the stop recovery time tSR before initiating a new ATD conversion sequence. * Wait Mode Wait Mode with AWAI = 1: This halts A/D conversion. Exit from Wait mode will resume A/D conversion, but due to the recovery time the result of this conversion should be ignored. Entering wait mode, the ATD conversion either continues or halts for low power depending on the logical value of the AWAIT bit. * Freeze Mode Writing ADPU = 0 (Note that all ATD registers remain accessible.): This aborts any A/D conversion in progress. In freeze mode, the ATD10B16C will behave according to the logical values of the FRZ1 and FRZ0 bits. This is useful for debugging and emulation. NOTE The reset value for the ADPU bit is zero. Therefore, when this module is reset, it is reset into the power down state.
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7.5
Resets
At reset the ATD10B16C is in a power down state. The reset state of each individual bit is listed within Section 7.3, "Memory Map and Register Definition," which details the registers and their bit fields.
7.6
Interrupts
The interrupt requested by the ATD10B16C is listed in Table 7-28. Refer to MCU specification for related vector address and priority.
Table 7-28. ATD Interrupt Vectors
Interrupt Source Sequence Complete Interrupt CCR Mask I bit Local Enable ASCIE in ATDCTL2
See Section 7.3.2, "Register Descriptions," for further details.
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Chapter 8 Liquid Crystal Display (LCD32F4BV1)
8.1 Introduction
The LCD32F4B driver module has 32 frontplane drivers and 4 backplane drivers so that a maximum of 128 LCD segments are controllable. Each segment is controlled by a corresponding bit in the LCD RAM. Four multiplex modes (1/1, 1/2, 1/3, 1/4 duty), and three bias (1/1, 1/2, 1/3) methods are available. The V0 voltage is the lowest level of the output waveform and V3 becomes the highest level. All frontplane and backplane pins can be multiplexed with other port functions. The LCD32F4B driver system consists of five major sub-modules: * Timing and Control - consists of registers and control logic for frame clock generation, bias voltage level select, frame duty select, backplane select, and frontplane select/enable to produce the required frame frequency and voltage waveforms. * LCD RAM - contains the data to be displayed on the LCD. Data can be read from or written to the display RAM at any time. * Frontplane Drivers - consists of 32 frontplane drivers. * Backplane Drivers - consists of 4 backplane drivers. * Voltage Generator - Based on voltage applied to VLCD, it generates the voltage levels for the timing and control logic to produce the frontplane and backplane waveforms.
8.1.1
Features
The LCD32F4B includes these distinctive features: * Supports five LCD operation modes * 32 frontplane drivers * 4 backplane drivers -- Each frontplane has an enable bit respectively * Programmable frame clock generator * Programmable bias voltage level selector * On-chip generation of 4 different output voltage levels
8.1.2
Modes of Operation
The LCD32F4B module supports five operation modes with different numbers of backplanes and different biasing levels. During pseudo stop mode and wait mode the LCD operation can be suspended under
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software control. Depending on the state of internal bits, the LCD can operate normally or the LCD clock generation can be turned off and the LCD32F4B module enters a power conservation state. This is a high level description only, detailed descriptions of operating modes are contained in Section 8.4.2, "Operation in Wait Mode", Section 8.4.3, "Operation in Pseudo Stop Mode", and Section 8.4.4, "Operation in Stop Mode".
8.1.3
Block Diagram
Figure 8-1 is a block diagram of the LCD32F4B module.
Internal Address/Data/Clocks
OSCCLK
LCD RAM 16 bytes
Timing and Control Logic
Prescaler
LCD Clock
V3 V2 Frontplane Drivers V1 V0 Voltage Generator
V3 V2 V1 V0 Backplane Drivers
FP[31:0]
VLCD
BP[3:0]
Figure 8-1. LCD32F4B Block Diagram
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8.2
External Signal Description
The LCD32F4B module has a total of 37 external pins.
Table 8-1. Signal Properties
Name 4 backplane waveforms 32 frontplane waveforms LCD voltage Port BP[3:0] Function Backplane waveform signals that connect directly to the pads Reset State High impedance High impedance --
FP[31:0] Frontplane waveform signals that connect directly to the pads VLCD LCD supply voltage
8.2.1
BP[3:0] -- Analog Backplane Pins
This output signal vector represents the analog backplane waveforms of the LCD32F4B module and is connected directly to the corresponding pads.
8.2.2
FP[31:0] -- Analog Frontplane Pins
This output signal vector represents the analog frontplane waveforms of the LCD32F4B module and is connected directly to the corresponding pads.
8.2.3
VLCD -- LCD Supply Voltage Pin
Positive supply voltage for the LCD waveform generation.
8.3
Memory Map and Register Definition
This section provides a detailed description of all memory and registers.
8.3.1
Module Memory Map
The memory map for the LCD32F4B module is given in Table 8-2. The address listed for each register is the address offset. The total address for each register is the sum of the base address for the LCD32F4B module and the address offset for each register.
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Table 8-2. LCD32F4B Memory Map
Address Offset 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C 0x000D 0x000E 0x000F 0x0010 0x0011 0x0012 0x0013 0x0014 0x0015 0x0016 0x0017 Use LCD Control Register 0 (LCDCR0) LCD Control Register 1 (LCDCR1) LCD Frontplane Enable Register 0 (FPENR0) LCD Frontplane Enable Register 1 (FPENR1) LCD Frontplane Enable Register 2 (FPENR2) LCD Frontplane Enable Register 3 (FPENR3) Unimplemented Unimplemented LCDRAM (Location 0) LCDRAM (Location 1) LCDRAM (Location 2) LCDRAM (Location 3) LCDRAM (Location 4) LCDRAM (Location 5) LCDRAM (Location 6) LCDRAM (Location 7) LCDRAM (Location 8) LCDRAM (Location 9) LCDRAM (Location 10) LCDRAM (Location 11) LCDRAM (Location 12) LCDRAM (Location 13) LCDRAM (Location 14) LCDRAM (Location 15) Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Access Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write
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8.3.2
Register Descriptions
This section consists of register descriptions. Each description includes a standard register diagram. Details of register bit and field function follow the register diagrams, in bit order.
8.3.2.1
LCD Control Register 0 (LCDCR0)
7 6 0 LCDEN LCLK2 0 0 LCLK1 0 LCLK0 0 BIAS 0 DUTY1 0 DUTY0 0 5 4 3 2 1 0
R W Reset 0
= Unimplemented or Reserved
Figure 8-2. LCD Control Register 0 (LCDCR0)
Read: anytime Write: LCDEN anytime. To avoid segment flicker the clock prescaler bits, the bias select bit and the duty select bits must not be changed when the LCD is enabled.
Table 8-3. LCDCR0 Field Descriptions
Field 7 LCDEN Description LCD32F4B Driver System Enable -- The LCDEN bit starts the LCD waveform generator. 0 All frontplane and backplane pins are disabled. In addition, the LCD32F4B system is disabled and all LCD waveform generation clocks are stopped. 1 LCD driver system is enabled. All FP[31:0] pins with FP[31:0]EN set, will output an LCD driver waveform The BP[3:0] pins will output an LCD32F4B driver waveform based on the settings of DUTY0 and DUTY1. LCD Clock Prescaler -- The LCD clock prescaler bits determine the OSCCLK divider value to produce the LCD clock frequency. For detailed description of the correlation between LCD clock prescaler bits and the divider value please refer to Table 8-7. BIAS Voltage Level Select -- This bit selects the bias voltage levels during various LCD operating modes, as shown in Table 8-8. LCD Duty Select -- The DUTY1 and DUTY0 bits select the duty (multiplex mode) of the LCD32F4B driver system, as shown in Table 8-8.
5:3 LCLK[2:0] 2 BIAS 1:0 DUTY[1:0]
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8.3.2.2
LCD Control Register 1 (LCDCR1)
7 6 0 5 0 4 0 3 0 2 0 LCDSWAI LCDRPSTP 0 1 0
R W Reset
0
0
0
0
0
0
0
0
Unimplemented or Reserved
Figure 8-3. LCD Control Register 1 (LCDCR1)
Read: anytime Write: anytime
Table 8-4. LCDCR1 Field Descriptions
Field 1 LCDSWAI Description LCD Stop in Wait Mode -- This bit controls the LCD operation while in wait mode. 0 LCD operates normally in wait mode. 1 Stop LCD32F4B driver system when in wait mode.
0 LCD Run in Pseudo Stop Mode -- This bit controls the LCD operation while in pseudo stop mode. LCDRPSTP 0 Stop LCD32F4B driver system when in pseudo stop mode. 1 LCD operates normally in pseudo stop mode.
8.3.2.3
LCD Frontplane Enable Register 0-3 (FPENR0-FPENR3)
7 6 FP6EN 0 5 FP5EN 0 4 FP4EN 0 3 FP3EN 0 2 FP2EN 0 1 FP1EN 0 0 FP0EN 0
R FP7EN W Reset 0
Figure 8-4. LCD Frontplane Enable Register 0 (FPENR0)
7 R FP15EN W Reset 0 0 0 0 0 0 0 0 FP14EN FP13EN FP12EN FP11EN FP10EN FP9EN FP8EN 6 5 4 3 2 1 0
Figure 8-5. LCD Frontplane Enable Register 1 (FPENR1)
7 R FP23EN W Reset 0 0 0 0 0 0 0 0 FP22EN FP21EN FP20EN FP19EN FP18EN FP17EN FP16EN 6 5 4 3 2 1 0
Figure 8-6. LCD Frontplane Enable Register 2 (FPENR2)
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7 R FP31EN W Reset 0
6 FP30EN 0
5 FP29EN 0
4 FP28EN 0
3 FP27EN 0
2 FP26EN 0
1 FP25EN 0
0 FP24EN 0
Figure 8-7. LCD Frontplane Enable Register 3 (FPENR3)
These bits enable the frontplane output waveform on the corresponding frontplane pin when LCDEN = 1. Read: anytime Write: anytime
Table 8-5. FPENR0-FPENR3 Field Descriptions
Field Description
31:0 Frontplane Output Enable -- The FP[31:0]EN bit enables the frontplane driver outputs. If LCDEN = 0, these FP[31:0]EN bits have no effect on the state of the I/O pins. It is recommended to set FP[31:0]EN bits before LCDEN is set. 0 Frontplane driver output disabled on FP[31:0]. 1 Frontplane driver output enabled on FP[31:0].
8.3.2.4
LCD RAM (LCDRAM)
The LCD RAM consists of 16 bytes. After reset the LCD RAM contents will be indeterminate (I), as indicated by Figure 8-8.
7 R LCDRAM W Reset R LCDRAM W Reset R LCDRAM W Reset R LCDRAM W Reset R LCDRAM W Reset R LCDRAM W Reset I = Value is indeterminate FP1BP3 I FP3BP3 I FP5BP3 I FP7BP3 I FP9BP3 I FP11BP3 I 6 FP1BP2 I FP3BP2 I FP5BP2 I FP7BP2 I FP9BP2 I FP11BP2 I 5 FP1BP1 I FP3BP1 I FP5BP1 I FP7BP1 I FP9BP1 I FP11BP1 I 4 FP1BP0 I FP3BP0 I FP5BP0 I FP7BP0 I FP9BP0 I FP11BP0 I 3 FP0BP3 I FP2BP3 I FP4BP3 I FP6BP3 I FP8BP3 I FP10BP3 I 2 FP0BP2 I FP2BP2 I FP4BP2 I FP6BP2 I FP8BP2 I FP10BP2 I 1 FP0BP1 I FP2BP1 I FP4BP1 I FP6BP1 I FP8BP1 I FP10BP1 I 0 FP0BP0 I FP2BP0 I FP4BP0 I FP6BP0 I FP8BP0 I FP10BP0 I
Figure 8-8. LCD RAM (LCDRAM)
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Chapter 8 Liquid Crystal Display (LCD32F4BV1)
R LCDRAM W Reset R LCDRAM W Reset R LCDRAM W Reset R LCDRAM W Reset R LCDRAM W Reset R LCDRAM W Reset R LCDRAM W Reset R LCDRAM W Reset R LCDRAM W Reset R LCDRAM W Reset
FP13BP3 I FP15BP3 I FP17BP3 I FP19BP3 I FP21BP3 I FP23BP3 I FP25BP3 I FP27BP3 I FP29BP3 I FP31BP3 I
FP13BP2 I FP15BP2 I FP17BP2 I FP19BP2 I FP21BP2 I FP23BP2 I FP25BP2 I FP27BP2 I FP29BP2 I FP31BP2 I
FP13BP1 I FP15BP1 I FP17BP1 I FP19BP1 I FP21BP1 I FP23BP1 I FP25BP1 I FP27BP1 I FP29BP1 I FP31BP1 I
FP13BP0 I FP15BP0 I FP17BP0 I FP19BP0 I FP21BP0 I FP23BP0 I FP25BP0 I FP27BP0 I FP29BP0 I FP31BP0 I
FP12BP3 I FP14BP3 I FP16BP3 I FP18BP3 I FP20BP3 I FP22BP3 I FP24BP3 I FP26BP3 I FP28BP3 I FP30BP3 I
FP12BP2 I FP14BP2 I FP16BP2 I FP18BP2 I FP20BP2 I FP22BP2 I FP24BP2 I FP26BP2 I FP28BP2 I FP30BP2 I
FP12BP1 I FP14BP1 I FP16BP1 I FP18BP1 I FP20BP1 I FP22BP1 I FP24BP1 I FP26BP1 I FP28BP1 I FP30BP1 I
FP12BP0 I FP14BP0 I FP16BP0 I FP18BP0 I FP20BP0 I FP22BP0 I FP24BP0 I FP26BP0 I FP28BP0 I FP30BP0 I
I = Value is indeterminate
Figure 8-8. LCD RAM (LCDRAM) (continued)
Read: anytime Write: anytime
Table 8-6. LCD RAM Field Descriptions
Field 31:0 3:0 FP[31:0] BP[3:0] Description LCD Segment ON -- The FP[31:0]BP[3:0] bit displays (turns on) the LCD segment connected between FP[31:0] and BP[3:0]. 0 LCD segment OFF 1 LCD segment ON
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Chapter 8 Liquid Crystal Display (LCD32F4BV1)
8.4
Functional Description
This section provides a complete functional description of the LCD32F4B block, detailing the operation of the design from the end user perspective in a number of subsections.
8.4.1
8.4.1.1
LCD Driver Description
Frontplane, Backplane, and LCD System During Reset
During a reset the following conditions exist: * The LCD32F4B system is configured in the default mode, 1/4 duty and 1/3 bias, that means all backplanes are used. * All frontplane enable bits, FP[31:0]EN are cleared and the ON/OFF control for the display, the LCDEN bit is cleared, thereby forcing all frontplane and backplane driver outputs to the high impedance state. The MCU pin state during reset is defined by the port integration module (PIM).
8.4.1.2
LCD Clock and Frame Frequency
The frequency of the oscillator clock (OSCCLK) and divider determine the LCD clock frequency. The divider is set by the LCD clock prescaler bits, LCLK[2:0], in the LCD control register 0 (LCDCR0). Table 8-7 shows the LCD clock and frame frequency for some multiplexed mode at OSCCLK = 16 MHz, 8 MHz, 4 MHz, 2 MHz, 1 MHz, and 0.5 MHz.
Table 8-7. LCD Clock and Frame Frequency
Oscillator Frequency in MHz OSCCLK = 0.5 OSCCLK = 1.0 OSCCLK = 2.0 OSCCLK = 4.0 OSCCLK = 8.0 OSCCLK = 16.0 LCD Clock Prescaler Divider LCLK2 0 0 0 0 0 0 0 1 1 1 1 1 LCLK1 0 0 0 1 1 1 1 0 0 0 1 1 LCLK0 0 1 1 0 0 1 1 0 0 1 0 1 1024 2048 2048 4096 4096 8192 8192 16384 16384 32768 65536 131072 LCD Clock Frequency [Hz] 488 244 488 244 488 244 488 244 488 244 244 122 Frame Frequency [Hz] 1/1 Duty 488 244 488 244 488 244 488 244 488 244 244 122 1/2 Duty 244 122 244 122 244 122 244 122 244 122 122 61 1/3 Duty 163 81 163 81 163 81 163 81 163 81 81 40 1/4 Duty 122 61 122 61 122 61 122 61 122 61 61 31
For other combinations of OSCCLK and divider not shown in Table 8-7, the following formula may be used to calculate the LCD frame frequency for each multiplex mode: OSCCLK (Hz) LCD Frame Frequency (Hz) = ----------------------------------- Duty Divider The possible divider values are shown in Table 8-7.
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Chapter 8 Liquid Crystal Display (LCD32F4BV1)
8.4.1.3
LCD RAM
For a segment on the LCD to be displayed, data must be written to the LCD RAM which is shown in Section 8.3, "Memory Map and Register Definition". The 128 bits in the LCD RAM correspond to the 128 segments that are driven by the frontplane and backplane drivers. Writing a 1 to a given location will result in the corresponding display segment being driven with a differential RMS voltage necessary to turn the segment ON when the LCDEN bit is set and the corresponding FP[31:0]EN bit is set. Writing a 0 to a given location will result in the corresponding display segment being driven with a differential RMS voltage necessary to turn the segment OFF. The LCD RAM is a dual port RAM that interfaces with the internal address and data buses of the MCU. It is possible to read from LCD RAM locations for scrolling purposes. When LCDEN = 0, the LCD RAM can be used as on-chip RAM. Writing or reading of the LCDEN bit does not change the contents of the LCD RAM. After a reset, the LCD RAM contents will be indeterminate.
8.4.1.4
LCD Driver System Enable and Frontplane Enable Sequencing
If LCDEN = 0 (LCD32F4B driver system disabled) and the frontplane enable bit, FP[31:0]EN, is set, the frontplane driver waveform will not appear on the output until LCDEN is set. If LCDEN = 1 (LCD32F4B driver system enabled), the frontplane driver waveform will appear on the output as soon as the corresponding frontplane enable bit, FP[31:0]EN, in the registers FPENR0-FPENR3 is set.
8.4.1.5
LCD Bias and Modes of Operation
The LCD32F4B driver has five modes of operation: * 1/1 duty (1 backplane), 1/1 bias (2 voltage levels) * 1/2 duty (2 backplanes), 1/2 bias (3 voltage levels) * 1/2 duty (2 backplanes), 1/3 bias (4 voltage levels) * 1/3 duty (3 backplanes), 1/3 bias (4 voltage levels) * 1/4 duty (4 backplanes), 1/3 bias (4 voltage levels) The voltage levels required for the different operating modes are generated internally based on VLCD. Changing VLCD alters the differential RMS voltage across the segments in the ON and OFF states, thereby setting the display contrast. The backplane waveforms are continuous and repetitive every frame. They are fixed within each operating mode and are not affected by the data in the LCD RAM. The frontplane waveforms generated are dependent on the state (ON or OFF) of the LCD segments as defined in the LCD RAM. The LCD32F4B driver hardware uses the data in the LCD RAM to construct the frontplane waveform to create a differential RMS voltage necessary to turn the segment ON or OFF. The LCD duty is decided by the DUTY1 and DUTY0 bits in the LCD control register 0 (LCDCR0). The number of bias voltage levels is determined by the BIAS bit in LCDCR0. Table 8-8 summarizes the multiplex modes (duties) and the bias voltage levels that can be selected for each multiplex mode (duty). The backplane pins have their corresponding backplane waveform output BP[3:0] in high impedance state when in the OFF state as indicated in Table 8-8. In the OFF state the corresponding pins BP[3:0]can be used for other functionality, for example as general purpose I/O ports.
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Table 8-8. LCD Duty and Bias
LCDCR0 Register Duty DUTY1 1/1 1/2 1/3 1/4 0 1 1 0 DUTY0 1 0 1 0 BP3 OFF OFF OFF BP3 BP2 OFF OFF BP2 BP2 BP1 OFF BP1 BP1 BP1 BP0 BP0 BP0 BP0 BP0 1/1 YES NA NA NA 1/2 NA YES NA NA 1/3 NA NA YES YES 1/1 YES NA NA NA 1/2 NA NA NA NA 1/3 NA YES YES YES Backplanes Bias (BIAS = 0) Bias (BIAS = 1)
8.4.2
Operation in Wait Mode
The LCD32F4B driver system operation during wait mode is controlled by the LCD stop in wait (LCDSWAI) bit in the LCD control register 1 (LCDCR1). If LCDSWAI is reset, the LCD32F4B driver system continues to operate during wait mode. If LCDSWAI is set, the LCD32F4B driver system is turned off during wait mode. In this case, the LCD waveform generation clocks are stopped and the LCD32F4B drivers pull down to VSSX those frontplane and backplane pins that were enabled before entering wait mode. The contents of the LCD RAM and the LCD registers retain the values they had prior to entering wait mode.
8.4.3
Operation in Pseudo Stop Mode
The LCD32F4B driver system operation during pseudo stop mode is controlled by the LCD run in pseudo stop (LCDRPSTP) bit in the LCD control register 1 (LCDCR1). If LCDRPSTP is reset, the LCD32F4B driver system is turned off during pseudo stop mode. In this case, the LCD waveform generation clocks are stopped and the LCD32F4B drivers pull down to VSSX those frontplane and backplane pins that were enabled before entering pseudo stop mode. If LCDRPSTP is set, the LCD32F4B driver system continues to operate during pseudo stop mode. The contents of the LCD RAM and the LCD registers retain the values they had prior to entering pseudo stop mode.
8.4.4
Operation in Stop Mode
All LCD32F4B driver system clocks are stopped, the LCD32F4B driver system pulls down to VSSX those frontplane and backplane pins that were enabled before entering stop mode. Also, during stop mode, the contents of the LCD RAM and the LCD registers retain the values they had prior to entering stop mode. As a result, after exiting from stop mode, the LCD32F4B driver system clocks will run (if LCDEN = 1) and the frontplane and backplane pins retain the functionality they had prior to entering stop mode.
8.4.5
LCD Waveform Examples
Figure 8-9 through Figure 8-13 show the timing examples of the LCD output waveforms for the available modes of operation.
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Chapter 8 Liquid Crystal Display (LCD32F4BV1)
8.4.5.1
1/1 Duty Multiplexed with 1/1 Bias Mode
Duty = 1/1:DUTY1 = 0, DUTY0 = 1 Bias = 1/1:BIAS = 0 or BIAS = 1 V0 = V1 = VSSX, V2 = V3 = VLCD - BP1, BP2, and BP3 are not used, a maximum of 32 segments are displayed.
1 Frame VLCD BP0 VSSX VLCD FPx (xxx0) VSSX VLCD FPy (xxx1) VSSX +VLCD BP0-FPx (OFF) 0 -VLCD +VLCD BP0-FPy (ON) 0 -VLCD
Figure 8-9. 1/1 Duty and 1/1 Bias
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Chapter 8 Liquid Crystal Display (LCD32F4BV1)
8.4.5.2
1/2 Duty Multiplexed with 1/2 Bias Mode
Duty = 1/2:DUTY1 = 1, DUTY0 = 0 Bias = 1/2:BIAS = 0 V0 = VSSX, V1 = V2 = VLCD * 1/2, V3 = VLCD - BP2 and BP3 are not used, a maximum of 64 segments are displayed.
1 Frame VLCD VLCD x 1/2 VSSX VLCD VLCD x 1/2 VSSX VLCD VLCD x 1/2 VSSX VLCD VLCD x 1/2 VSSX VLCD VLCD x 1/2 VSSX +VLCD +VLCD x 1/2 0 -VLCD x 1/2 -VLCD +VLCD +VLCD x 1/2 0 -VLCD x 1/2 -VLCD +VLCD +VLCD x 1/2 0 -VLCD x 1/2 -VLCD +VLCD +VLCD x 1/2 0 -VLCD x 1/2 -VLCD
BP0
BP1
FPx (xx10)
FPy (xx00)
FPz (xx11)
BP0-FPx (OFF)
BP1-FPx (ON)
BP0-FPy (OFF)
BP0-FPz (ON)
Figure 8-10. 1/2 Duty and 1/2 Bias
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Chapter 8 Liquid Crystal Display (LCD32F4BV1)
8.4.5.3
1/2 Duty Multiplexed with 1/3 Bias Mode
Duty = 1/2:DUTY1 = 1, DUTY0 = 0 Bias = 1/3:BIAS = 1 V0 = VSSX, V1 = VLCD * 1/3, V2 = VLCD * 2/3, V3 = VLCD - BP2 and BP3 are not used, a maximum of 64 segments are displayed.
1 Frame VLCD VLCD x 2/3 VLCD x 1/3 VSSX VLCD VLCD x 2/3 VLCD x 1/3 VSSX VLCD VLCD x 2/3 VLCD x 1/3 VSSX VLCD VLCD x 2/3 VLCD x 1/3 VSSX VLCD VLCD x 2/3 VLCD x 1/3 VSSX +VLCD +VLCD x 2/3 +VLCD x 1/3 0 -VLCD x 1/3 -VLCD x 2/3 -VLCD +VLCD +VLCD x 2/3 +VLCD x 1/3 0 -VLCD x 1/3 -VLCD x 2/3 -VLCD +VLCD +VLCD x 2/3 +VLCD x 1/3 0 -VLCD x 1/3 -VLCD x 2/3 -VLCD +VLCD +VLCD x 2/3 +VLCD x 1/3 0 -VLCD x 1/3 -VLCD x 2/3 -VLCD
BP0
BP1
FPx (xx10)
FPy (xx00)
FPz (xx11)
BP0-FPx (OFF)
BP1-FPx (ON)
BP0-FPy (OFF)
BP0-FPz (ON)
Figure 8-11. 1/2 Duty and 1/3 Bias
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Chapter 8 Liquid Crystal Display (LCD32F4BV1)
8.4.5.4
1/3 Duty Multiplexed with 1/3 Bias Mode
Duty = 1/3:DUTY1 = 1, DUTY0 = 1 Bias = 1/3:BIAS = 0 or BIAS = 1 V0 = VSSX, V1 = VLCD * 1/3, V2 = VLCD * 2/3, V3 = VLCD - BP3 is not used, a maximum of 96 segments are displayed.
1 Frame VLCD VLCD x 2/3 VLCD x 1/3 VSSX VLCD VLCD x 2/3 VLCD x 1/3 VSSX VLCD VLCD x 2/3 VLCD x 1/3 VSSX VLCD VLCD x 2/3 VLCD x 1/3 VSSX +VLCD +VLCD x 2/3 +VLCD x 1/3 0 -VLCD x 1/3 -VLCD x 2/3 -VLCD +VLCD +VLCD x 2/3 +VLCD x 1/3 0 -VLCD x 1/3 -VLCD x 2/3 -VLCD
BP0
BP1
BP2
FPx (x010)
BP0-FPx (OFF)
BP1-FPx (ON)
Figure 8-12. 1/3 Duty and 1/3 Bias
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Chapter 8 Liquid Crystal Display (LCD32F4BV1)
8.4.5.5
1/4 Duty Multiplexed with 1/3 Bias Mode
Duty = 1/4:DUTY1 = 0, DUTY0 = 0 Bias = 1/3:BIAS = 0 or BIAS = 1 V0 = VSSX, V1 = VLCD * 1/3, V2 = VLCD * 2/3, V3 = VLCD - A maximum of 128 segments are displayed.
1 Frame VLCD VLCD x 2/3 VLCD x 1/3 VSSX VLCD VLCD x 2/3 VLCD x 1/3 VSSX VLCD VLCD x 2/3 VLCD x 1/3 VSSX VLCD VLCD x 2/3 VLCD x 1/3 VSSX VLCD VLCD x 2/3 VLCD x 1/3 VSSX +VLCD +VLCD x 2/3 +VLCD x 1/3 0 -VLCD x 1/3 -VLCD x 2/3 -VLCD +VLCD +VLCD x 2/3 +VLCD x 1/3 0 -VLCD x 1/3 -VLCD x 2/3 -VLCD
BP0
BP1
BP2
BP3
FPx (1001)
BP0-FPx (ON)
BP1-FPx (OFF)
Figure 8-13. 1/4 Duty and 1/3 Bias
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Chapter 8 Liquid Crystal Display (LCD32F4BV1)
8.5
Resets
The reset values of registers and signals are described in Section 8.3, "Memory Map and Register Definition". The behavior of the LCD32F4B system during reset is described in Section 8.4.1, "LCD Driver Description".
8.6
Interrupts
This module does not generate any interrupts.
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Chapter 8 Liquid Crystal Display (LCD32F4BV1)
MC9S12HZ256 Data Sheet, Rev. 2.05 258 Freescale Semiconductor
Chapter 9 Motor Controller (MC10B8CV1)
9.1 Introduction
The block MC10B8C is a PWM motor controller suitable to drive instruments in a cluster configuration or any other loads requiring a PWM signal. The motor controller has eight PWM channels associated with two pins each (16 pins in total).
9.1.1
Features
The MC10B8C includes the following features: * 10/11-bit PWM counter * 11-bit resolution with selectable PWM dithering function * 7-bit resolution mode (fast mode): duty cycle can be changed by accessing only 1 byte/output * Left, right, or center aligned PWM * Output slew rate control * This module is suited for, but not limited to, driving small stepper and air core motors used in instrumentation applications. This module can be used for other motor control or PWM applications that match the frequency, resolution, and output drive capabilities of the module.
9.1.2
9.1.2.1
9.1.2.1.1
Modes of Operation
Functional Modes
PWM Resolution
The motor controller can be configured to either 11- or 7-bits resolution mode by clearing or setting the FAST bit. This bit influences all PWM channels. For details, please refer to Section 9.3.2.5, "Motor Controller Duty Cycle Registers". 9.1.2.1.2 Dither Function
Dither function can be selected or deselected by setting or clearing the DITH bit. This bit influences all PWM channels. For details, please refer to Section 9.4.1.3.5, "Dither Bit (DITH)".
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Chapter 9 Motor Controller (MC10B8CV1)
9.1.2.2
PWM Channel Configuration Modes
The eight PWM channels can operate in three functional modes. Those modes are, with some restrictions, selectable for each channel independently. 9.1.2.2.1 Dual Full H-Bridge Mode
This mode is suitable to drive a stepper motor or a 360o air gauge instrument. For details, please refer to Section 9.4.1.1.1, "Dual Full H-Bridge Mode (MCOM = 11)". In this mode two adjacent PWM channels are combined, and two PWM channels drive four pins. 9.1.2.2.2 Full H-Bridge Mode
This mode is suitable to drive any load requiring a PWM signal in a H-bridge configuration using two pins. For details please refer to Section 9.4.1.1.2, "Full H-Bridge Mode (MCOM = 10)". 9.1.2.2.3 Half H-Bridge Mode
This mode is suitable to drive a 90o instrument driven by one pin. For details, please refer to Section 9.4.1.1.3, "Half H-Bridge Mode (MCOM = 00 or 01)".
9.1.2.3
PWM Alignment Modes
Each PWM channel can operate independently in three different alignment modes. For details, please refer to Section 9.4.1.3.1, "PWM Alignment Modes".
9.1.2.4
Low-Power Modes
The behavior of the motor controller in low-power modes is programmable. For details, please refer to Section 9.4.5, "Operation in Wait Mode" and Section 9.4.6, "Operation in Stop and Pseudo-Stop Modes".
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Chapter 9 Motor Controller (MC10B8CV1)
9.1.3
Block Diagram
Control Registers FAST DITH
Period Register
11-Bit Timer/Counter 11
PWM Channel Pair PWM Channel M0C0M M0C0P M0C1M M0C1P M1C0M M1C0P M1C1M M1C1P M2C0M M2C0P M2C1M M2C1P M3C0M M3C0P M3C1M M3C1P
Duty Register 0 Duty Register 1 Duty Register 2 Duty Register 3 Duty Register 4 Duty Register 5 Duty Register 6 Duty Register 7
Comparator Comparator Comparator Comparator Comparator Comparator Comparator Comparator
Figure 9-1. MC10B8C Block Diagram
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Chapter 9 Motor Controller (MC10B8CV1)
9.2
External Signal Description
The motor controller is associated with 16 pins. Table 9-1 lists the relationship between the PWM channels and signal pins as well as PWM channel pair (motor number), coils, and nodes they are supposed to drive if all channels are set to dual full H-bridge configuration.
Table 9-1. PWM Channel and Pin Assignment
Pin Name M0C0M M0C0P M0C1M M0C1P M1C0M M1C0P M1C1M M1C1P M2C0M M2C0P M2C1M M2C1P M3C0M M3C0P M3C1M M3C1P
1
PWM Channel 0 1 2 3 4 5 6 7
PWM Channel Pair1 0
Coil 0 1
Node Minus Plus Minus Plus Minus Plus Minus Plus Minus Plus Minus Plus Minus Plus Minus Plus
1
0 1
2
0 1
3
0 1
A PWM Channel Pair always consists of PWM channel x and PWM channel x+1 (x = 2n). The term "PWM Channel Pair" is equivalent to the term "Motor". E.g. Channel Pair 0 is equivalent to Motor 0
9.2.1
M0C0M/M0C0P/M0C1M/M0C1P -- PWM Output Pins for Motor 0
High current PWM output pins that can be used for motor drive. These pins interface to the coils of motor 0. PWM output on M0C0M results in a positive current flow through coil 0 when M0C0P is driven to a logic high state. PWM output on M0C1M results in a positive current flow through coil 1 when M0C1P is driven to a logic high state.
9.2.2
M1C0M/M1C0P/M1C1M/M1C1P -- PWM Output Pins for Motor 1
High current PWM output pins that can be used for motor drive. These pins interface to the coils of motor 1. PWM output on M1C0M results in a positive current flow through coil 0 when M1C0P is driven to a logic high state. PWM output on M1C1M results in a positive current flow through coil 1 when M1C1P is driven to a logic high state.
9.2.3
M2C0M/M2C0P/M2C1M/M2C1P -- PWM Output Pins for Motor 2
High current PWM output pins that can be used for motor drive. These pins interface to the coils of motor 2. PWM output on M2C0M results in a positive current flow through coil 0 when M2C0P is driven
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Chapter 9 Motor Controller (MC10B8CV1)
to a logic high state. PWM output on M2C1M results in a positive current flow through coil 1 when M2C1P is driven to a logic high state.
9.2.4
M3C0M/M3C0P/M3C1M/M3C1P -- PWM Output Pins for Motor 3
High current PWM output pins that can be used for motor drive. These pins interface to the coils of motor 3. PWM output on M3C0M results in a positive current flow through coil 0 when M3C0P is driven to a logic high state. PWM output on M3C1M results in a positive current flow through coil 1 when M3C1P is driven to a logic high state.
9.3
Memory Map and Register Definition
This section provides a detailed description of all registers of the 10-bit 8-channel motor controller module.
9.3.1
Module Memory Map
Figure 9-2 shows the memory map of the 10-bit 8-channel motor controller module.
Figure 9-2. MC10B8C Memory Map
Offset 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C 0x000D 0x000E 0x000F 0x0010 0x0011 0x0012 0x0013 0x0014 0x0015 Register Motor Controller Control Register 0 (MCCTL0) Motor Controller Control Register 1 (MCCTL1) Motor Controller Period Register (High Byte) Motor Controller Period Register (Low Byte) Reserved1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Motor Controller Channel Control Register 0 (MCCC0) Motor Controller Channel Control Register 1 (MCCC1) Motor Controller Channel Control Register 2 (MCCC2) Motor Controller Channel Control Register 3 (MCCC3) Motor Controller Channel Control Register 4 (MCCC4) Motor Controller Channel Control Register 5 (MCCC5) Access RW RW RW RW -- -- -- -- -- -- -- -- -- -- -- -- RW RW RW RW RW RW
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Chapter 9 Motor Controller (MC10B8CV1)
Figure 9-2. MC10B8C Memory Map (continued)
Offset 0x0016 0x0017 0x0018 0x0019 0x001A 0x001B 0x001C 0x001D 0x001E 0x001F 0x0020 0x0021 0x0022 0x0023 0x0024 0x0025 0x0026 0x0027 0x0028 0x0029 0x002A 0x002B 0x002C 0x002D 0x002E 0x002F 0x0030 0x0031 0x0032 0x0033 0x0034 0x0035 0x0036 0x0037 0x0038 0x0039 0x003A 0x003B 0x003C 0x003D Register Motor Controller Channel Control Register 6 (MCCC6) Motor Controller Channel Control Register 7 (MCCC7) Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Motor Controller Duty Cycle Register 0 (MCDC0) -- High Byte Motor Controller Duty Cycle Register 0 (MCDC0) -- Low Byte Motor Controller Duty Cycle Register 1 (MCDC1) -- High Byte Motor Controller Duty Cycle Register 1 (MCDC1) -- Low Byte Motor Controller Duty Cycle Register 2 (MCDC2) -- High Byte Motor Controller Duty Cycle Register 2 (MCDC2) -- Low Byte Motor Controller Duty Cycle Register 3 (MCDC3) -- High Byte Motor Controller Duty Cycle Register 3 (MCDC3) -- Low Byte Motor Controller Duty Cycle Register 4 (MCDC4) -- High Byte Motor Controller Duty Cycle Register 4 (MCDC4) -- Low Byte Motor Controller Duty Cycle Register 5 (MCDC5) -- High Byte Motor Controller Duty Cycle Register 5 (MCDC5) -- Low Byte Motor Controller Duty Cycle Register 6 (MCDC6) -- High Byte Motor Controller Duty Cycle Register 6 (MCDC6) -- Low Byte Motor Controller Duty Cycle Register 7 (MCDC7) -- High Byte Motor Controller Duty Cycle Register 7 (MCDC7) -- Low Byte Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved MC9S12HZ256 Data Sheet, Rev. 2.05 264 Freescale Semiconductor Access RW RW -- -- -- -- -- -- -- -- RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW -- -- -- -- -- -- -- -- -- -- -- -- -- --
Chapter 9 Motor Controller (MC10B8CV1)
Figure 9-2. MC10B8C Memory Map (continued)
Offset 0x003E 0x003F
1
Register Reserved Reserved
Access -- --
Write accesses to "Reserved" addresses have no effect. Read accesses to "Reserved" addresses provide invalid data (0x0000).
9.3.2
9.3.2.1
Register Descriptions
Motor Controller Control Register 0
This register controls the operating mode of the motor controller module.
7 R W Reset 0 0 0 0 0 0 0 0 0 MCPRE[1:0] MCSWAI FAST DITH 6 5 4 3 2 1 0 MCTOIF 0
= Unimplemented or Reserved
Figure 9-3. Motor Controller Control Register 0 (MCCTL0) Table 9-2. MCCTL0 Field Descriptions
Field 6:5 MCPRE[1:0] Description Motor Controller Prescaler Select -- MCPRE1 and MCPRE0 determine the prescaler value that sets the motor controller timer counter clock frequency (fTC). The clock source for the prescaler is the peripheral bus clock (fBUS) as shown in Figure 9-22. Writes to MCPRE1 or MCPRE0 will not affect the timer counter clock frequency fTC until the start of the next PWM period. Table 9-3 shows the prescaler values that result from the possible combinations of MCPRE1 and MCPRE0 Motor Controller Module Stop in Wait Mode 0 Entering wait mode has no effect on the motor controller module and the associated port pins maintain the functionality they had prior to entering wait mode both during wait mode and after exiting wait mode. 1 Entering wait mode will stop the clock of the module and debias the analog circuitry. The module will release the pins. Motor Controller PWM Resolution Mode 0 PWM operates in 11-bit resolution mode, duty cycle registers of all channels are switched to word mode. 1 PWM operates in 7-bit resolution (fast) mode, duty cycle registers of all channels are switched to byte mode. Motor Control/Driver Dither Feature Enable (refer to Section 9.4.1.3.5, "Dither Bit (DITH)") 0 Dither feature is disabled. 1 Dither feature is enabled. Motor Controller Timer Counter Overflow Interrupt Flag -- This bit is set when a motor controller timer counter overflow occurs. The bit is cleared by writing a 1 to the bit. 0 A motor controller timer counter overflow has not occurred since the last reset or since the bit was cleared. 1 A motor controller timer counter overflow has occurred.
4 MCSWAI
3 FAST 2 DITH 0 MCTOIF
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.
Table 9-3. Prescaler Values
MCPRE[1:0] 00 01 10 11 fTC fBus fBus/2 fBus/4 fBus/8
9.3.2.2
Motor Controller Control Register 1
This register controls the behavior of the analog section of the motor controller as well as the interrupt enables.
7 R RECIRC W Reset 0 0 0 0 0 0 0 0 6 0 5 0 4 0 3 0 2 0 1 0 MCTOIE 0
= Unimplemented or Reserved
Figure 9-4. Motor Controller Control Register 1 (MCCTL1) Table 9-4. MCCTL1 Field Descriptions
Field 7 RECIRC Description Recirculation in (Dual) Full H-Bridge Mode (refer to Section 9.4.1.3.3, "RECIRC Bit")-- RECIRC only affects the outputs in (dual) full H-bridge modes. In half H-bridge mode, the PWM output is always active low. RECIRC = 1 will also invert the effect of the S bits (refer to Section 9.4.1.3.2, "Sign Bit (S)") in (dual) full H-bridge modes. RECIRC must be changed only while no PWM channel is operating in (dual) full H-bridge mode; otherwise, erroneous output pattern may occur. 0 Recirculation on the high side transistors. Active state for PWM output is logic low, the static channel will output logic high. 1 Recirculation on the low side transistors. Active state for PWM output is logic high, the static channel will output logic low. Motor Controller Timer Counter Overflow Interrupt Enable 0 Interrupt disabled. 1 Interrupt enabled. An interrupt will be generated when the motor controller timer counter overflow interrupt flag (MCTOIF) is set.
0 MCTOIE
MC9S12HZ256 Data Sheet, Rev. 2.05 266 Freescale Semiconductor
Chapter 9 Motor Controller (MC10B8CV1)
9.3.2.3
Motor Controller Period Register
The period register defines PER, the number of motor controller timer counter clocks a PWM period lasts. The motor controller timer counter is clocked with the frequency fTC. If dither mode is enabled (DITH = 1, refer to Section 9.4.1.3.5, "Dither Bit (DITH)"), P0 is ignored and reads as a 0. In this case PER = 2 * D[10:1].
15 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14 0 13 0 12 0 11 0 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 10 9 8 7 6 5 4 3 2 1 0
= Unimplemented or Reserved
Figure 9-5. Motor Controller Period Register (MCPER) with DITH = 0
15 R W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14 0 13 0 12 0 11 0 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 10 9 8 7 6 5 4 3 2 1 0 0
= Unimplemented or Reserved
Figure 9-6. Motor Controller Period Register (MCPER) with DITH = 1
For example, programming MCPER to 0x0022 (PER = 34 decimal) will result in 34 counts for each complete PWM period. Setting MCPER to 0 will shut off all PWM channels as if MCAM[1:0] is set to 0 in all channel control registers after the next period timer counter overflow. In this case, the motor controller releases all pins. NOTE Programming MCPER to 0x0001 and setting the DITH bit will be managed as if MCPER is programmed to 0x0000. All PWM channels will be shut off after the next period timer counter overflow.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 267
Chapter 9 Motor Controller (MC10B8CV1)
9.3.2.4
Motor Controller Channel Control Registers
Each PWM channel has one associated control register to control output delay, PWM alignment, and output mode. The registers are named MCCC0... MCCC7. In the following, MCCC0 is described as a reference for all eight registers.
7 R MCOM1 W Reset 0 0 0 0 0 0 0 0 MCOM0 MCAM1 MCAM0 6 5 4 3 0 2 0 CD1 CD0 1 0
= Unimplemented or Reserved
Figure 9-7. Motor Controller Control Register Channel 0-7 (MCCC0-MCCC7) Table 9-5. MCCC0-MCCC7 Field Descriptions
Field Description
7:6 Output Mode -- MCOM1, MCOM0 control the PWM channel's output mode. See Table 9-6. MCOM[1:0] 5:4 MCAM[1:0] PWM Channel Alignment Mode -- MCAM1, MCAM0 control the PWM channel's PWM alignment mode and operation. See Table 9-7. MCAM[1:0] and MCOM[1:0] are double buffered. The values used for the generation of the output waveform will be copied to the working registers either at once (if all PWM channels are disabled or MCPER is set to 0) or if a timer counter overflow occurs. Reads of the register return the most recent written value, which are not necessarily the currently active values. 1:0 CD[1:0] PWM Channel Delay -- Each PWM channel can be individually delayed by a programmable number of PWM timer counter clocks. The delay will be n/fTC. See Table 9-8.
Table 9-6. Output Mode
MCOM[1:0] 00 01 10 11 Output Mode Half H-bridge mode, PWM on MnCxM, MnCxP is released Half H-bridge mode, PWM on MnCxP, MnCxM is released Full H-bridge mode Dual full H-bridge mode
Table 9-7. PWM Alignment Mode
MCAM[1:0] 00 01 10 11 PWM Alignment Mode Channel disabled Left aligned Right aligned Center aligned
MC9S12HZ256 Data Sheet, Rev. 2.05 268 Freescale Semiconductor
Chapter 9 Motor Controller (MC10B8CV1)
Table 9-8. Channel Delay
CD[1:0] 00 01 10 11 n [# of PWM Clocks] 0 1 2 3
NOTE The PWM motor controller will release the pins after the next PWM timer counter overflow without accommodating any channel delay if a single channel has been disabled or if the period register has been cleared or all channels have been disabled. Program one or more inactive PWM frames (duty cycle = 0) before writing a configuration that disables a single channel or the entire PWM motor controller.
9.3.2.5
Motor Controller Duty Cycle Registers
Each duty cycle register sets the sign and duty functionality for the respective PWM channel. The contents of the duty cycle registers define DUTY, the number of motor controller timer counter clocks the corresponding output is driven low (RECIRC = 0) or is driven high (RECIRC = 1). Setting all bits to 0 will give a static high output in case of RECIRC = 0; otherwise, a static low output. Values greater than or equal to the contents of the period register will generate a static low output in case of RECIRC = 0, or a static high output if RECIRC = 1. The layout of the duty cycle registers differ dependent upon the state of the FAST bit in the control register 0.
15 R S W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14 S 13 S 12 S 11 S D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 10 9 8 7 6 5 4 3 2 1 0
= Unimplemented or Reserved
Figure 9-8. Motor Controller Duty Cycle Register x (MCDCx) with FAST = 0
15 R S W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D8 D7 D6 D5 D4 D3 D2 14 13 12 11 10 9 8 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
= Unimplemented or Reserved
Figure 9-9. Motor Controller Duty Cycle Register x (MCDCx) with FAST = 1
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 269
Chapter 9 Motor Controller (MC10B8CV1)
Table 9-9. MCDCx Field Descriptions
Field 0 S Description SIGN -- The SIGN bit is used to define which output will drive the PWM signal in (dual) full-H-bridge modes. The SIGN bit has no effect in half-bridge modes. See Section 9.4.1.3.2, "Sign Bit (S)", and table Table 9-11 for detailed information about the impact of RECIRC and SIGN bit on the PWM output.
Whenever FAST = 1, the bits D10, D9, D1, and D0 will be set to 0 if the duty cycle register is written. For example setting MCDCx = 0x0158 with FAST = 0 gives the same output waveform as setting MCDCx = 0x5600 with FAST = 1 (with FAST = 1, the low byte of MCDCx needs not to be written). The state of the FAST bit has impact only during write and read operations. A change of the FAST bit (set or clear) without writing a new value does not impact the internal interpretation of the duty cycle values. To prevent the output from inconsistent signals, the duty cycle registers are double buffered. The motor controller module will use working registers to generate the output signals. The working registers are copied from the bus accessible registers at the following conditions: * MCPER is set to 0 (all channels are disabled in this case) * MCAM[1:0] of the respective channel is set to 0 (channel is disabled) * A PWM timer counter overflow occurs while in half H-bridge or full H-bridge mode * A PWM channel pair is configured to work in Dual Full H-Bridge mode and a PWM timer counter overflow occurs after the odd1 duty cycle register of the channel pair has been written. In this way, the output of the PWM will always be either the old PWM waveform or the new PWM waveform, not some variation in between. Reads of this register return the most recent value written. Reads do not necessarily return the value of the currently active sign, duty cycle, and dither functionality due to the double buffering scheme.
1. Odd duty cycle register: MCDCx+1, x = 2n MC9S12HZ256 Data Sheet, Rev. 2.05 270 Freescale Semiconductor
Chapter 9 Motor Controller (MC10B8CV1)
9.4
9.4.1
9.4.1.1
Functional Description
Modes of Operation
PWM Output Modes
The motor controller is configurable between three output modes. * Dual full H-bridge mode can be used to control either a stepper motor or a 360 air core instrument. In this case two PWM channels are combined. * In full H-bridge mode, each PWM channel is updated independently. * In half H-bridge mode, one pin of the PWM channel can generate a PWM signal to control a 90 air core instrument (or other load requiring a PWM signal) and the other pin is unused. The mode of operation for each PWM channel is determined by the corresponding MCOM[1:0] bits in channel control registers. After a reset occurs, each PWM channel will be disabled, the corresponding pins are released. Each PWM channel consists of two pins. One output pin will generate a PWM signal. The other will operate as logic high or low output depending on the state of the RECIRC bit (refer to Section 9.4.1.3.3, "RECIRC Bit"), while in (dual) full H-bridge mode, or will be released, while in half H-bridge mode. The state of the S bit in the duty cycle register determines the pin where the PWM signal is driven in full H-bridge mode. While in half H-bridge mode, the state of the released pin is determined by other modules associated with this pin. Associated with each PWM channel pair n are two PWM channels, x and x + 1, where x = 2 * n and n (0, 1, 2, 3) is the PWM channel pair number. Duty cycle register x controls the sign of the PWM signal (which pin drives the PWM signal) and the duty cycle of the PWM signal for motor controller channel x. The pins associated with PWM channel x are MnC0P and MnC0M. Similarly, duty cycle register x + 1 controls the sign of the PWM signal and the duty cycle of the PWM signal for channel x + 1. The pins associated with PWM channel x + 1 are MnC1P and MnC1M. This is summarized in Table 9-10.
Table 9-10. Corresponding Registers and Pin Names for Each PWM Channel Pair
PWM Channel Pair Number n PWM Channel Control Register MCMCx Duty Cycle Register MCDCx Channel Number PWM Channel x, x = 2n Pin Names MnC0M MnC0P MCMCx + 1 MCDCx + 1 PWM Channel x + 1, x = 2n MnC1M MnC1P 0 MCMC0 MCDC0 PWM Channel 0 M0C0M M0C0P MCMC1 MCDC1 PWM Channel 1 M0C1M M0C1P
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 271
Chapter 9 Motor Controller (MC10B8CV1)
Table 9-10. Corresponding Registers and Pin Names for Each PWM Channel Pair (continued)
PWM Channel Pair Number 1 PWM Channel Control Register MCMC2 Duty Cycle Register MCDC2 Channel Number PWM Channel 2 Pin Names M1C0M M1C0P MCMC3 MCDC3 PWM Channel 3 M1C1M M1C1P 2 MCMC4 MCDC4 PWM Channel 4 M2C0M M2C0P MCMC5 MCDC5 PWM Channel 5 M2C1M M2C1P 3 MCMC6 MCDC6 PWM Channel 6 M3C0M M3C0P MCMC7 MCDC7 PWM Channel 7 M3C1M M3C1P
9.4.1.1.1
Dual Full H-Bridge Mode (MCOM = 11)
PWM channel pairs x and x + 1 operate in dual full H-bridge mode if both channels have been enabled (MCAM[1:0]=01, 10, or 11) and both of the corresponding output mode bits MCOM[1:0] in both PWM channel control registers are set. A typical configuration in dual full H-bridge mode is shown in Figure 9-10. PWM channel x drives the PWM output signal on either MnC0P or MnC0M. If MnC0P drives the PWM signal, MnC0M will be output either high or low depending on the RECIRC bit. If MnC0M drives the PWM signal, MnC0P will be an output high or low. PWM channel x + 1 drives the PWM output signal on either MnC1P or MnC1M. If MnC1P drives the PWM signal, MnC1M will be an output high or low. If MnC1M drives the PWM signal, MnC1P will be an output high or low. This results in motor recirculation currents on the high side drivers (RECIRC = 0) while the PWM signal is at a logic high level, or motor recirculation currents on the low side drivers (RECIRC = 1) while the PWM signal is at a logic low level. The pin driving the PWM signal is determined by the S (sign) bit in the corresponding duty cycle register and the state of the RECIRC bit. The value of the PWM duty cycle is determined by the value of the D[10:0] or D[8:2] bits respectively in the duty cycle register depending on the state of the FAST bit.
MC9S12HZ256 Data Sheet, Rev. 2.05 272 Freescale Semiconductor
Chapter 9 Motor Controller (MC10B8CV1)
PWM Channel x
MnC0P MnC0M
Motor n, Coil 0 Motor n, Coil 1
PWM Channel x + 1
MnC1P MnC1M
Figure 9-10. Typical Dual Full H-Bridge Mode Configuration
Whenever FAST = 0 only 16-bit write accesses to the duty cycle registers are allowed, 8-bit write accesses can lead to unpredictable duty cycles. While fast mode is enabled (FAST = 1), 8-bit write accesses to the high byte of the duty cycle registers are allowed, because only the high byte of the duty cycle register is used to determine the duty cycle. The following sequence should be used to update the current magnitude and direction for coil 0 and coil 1 of the motor to achieve consistent PWM output: 1. Write to duty cycle register x 2. Write to duty cycle register x + 1. At the next timer counter overflow, the duty cycle registers will be copied to the working duty cycle registers. Sequential writes to the duty cycle register x will result in the previous data being overwritten. 9.4.1.1.2 Full H-Bridge Mode (MCOM = 10)
In full H-bridge mode, the PWM channels x and x + 1 operate independently. The duty cycle working registers are updated whenever a timer counter overflow occurs. 9.4.1.1.3 Half H-Bridge Mode (MCOM = 00 or 01)
In half H-bridge mode, the PWM channels x and x + 1 operate independently. In this mode, each PWM channel can be configured such that one pin is released and the other pin is a PWM output. Figure 9-11 shows a typical configuration in half H-bridge mode. The two pins associated with each channel are switchable between released mode and PWM output dependent upon the state of the MCOM[1:0] bits in the MCCCx (channel control) register. See register description in Section 9.3.2.4, "Motor Controller Channel Control Registers". In half H-bridge mode, the state of the S bit has no effect.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 273
Chapter 9 Motor Controller (MC10B8CV1)
VDDM
Released PWM Channel x MnC0P MnC0M PWM Output VDDM VSSM Released PWM Channel x + 1 MnC1P MnC1M PWM Output
VSSM
Figure 9-11. Typical Quad Half H-Bridge Mode Configuration
9.4.1.2
Relationship Between PWM Mode and PWM Channel Enable
The pair of motor controller channels cannot be placed into dual full H-bridge mode unless both motor controller channels have been enabled (MCAM[1:0] not equal to 00) and dual full H-bridge mode is selected for both PWM channels (MCOM[1:0] = 11). If only one channel is set to dual full H-bridge mode, this channel will operate in full H-bridge mode, the other as programmed.
9.4.1.3
9.4.1.3.1
Relationship Between Sign, Duty, Dither, RECIRC, Period, and PWM Mode Functions
PWM Alignment Modes
Each PWM channel can be programmed individually to three different alignment modes. The mode is determined by the MCAM[1:0] bits in the corresponding channel control register. Left aligned (MCAM[1:0] = 01): The output will start active (low if RECIRC = 0 or high if RECIRC = 1) and will turn inactive (high if RECIRC = 0 or low if RECIRC = 1) after the number of counts specified by the corresponding duty cycle register.
MC9S12HZ256 Data Sheet, Rev. 2.05 274 Freescale Semiconductor
Chapter 9 Motor Controller (MC10B8CV1)
Motor Controller Timer Counter Clock Motor Controller 0 Timer Counter PWM Output 1 Period 100 Counts 1 Period 100 Counts 15 99 0 15 99 0
DITH = 0, MCAM[1:0] = 01, MCDCx = 15, MCPER = 100, RECIRC = 0
Right aligned (MCAM[1:0] = 10): The output will start inactive (high if RECIRC = 0 and low if RECIRC = 1) and will turn active after the number of counts specified by the difference of the contents of period register and the corresponding duty cycle register.
Motor Controller Timer Counter Clock Motor Controller 0 Timer Counter PWM Output 1 Period 100 Counts 1 Period 100 Counts 85 99 0 85 99 0
DITH = 0, MCAM[1:0] = 10, MCDCx = 15, MCPER = 100, RECIRC = 0
Center aligned (MCAM[1:0] = 11): Even periods will be output left aligned, odd periods will be output right aligned. PWM operation starts with the even period after the channel has been enabled. PWM operation in center aligned mode might start with the odd period if the channel has not been disabled before changing the alignment mode to center aligned.
Motor Controller Timer Counter Clock Motor Controller 0 Timer Counter PWM Output 1 Period 100 Counts 1 Period 100 Counts 15 99 0 85 99 0
DITH = 0, MCAM[1:0] = 11, MCDCx = 15, MCPER = 100, RECIRC = 0
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 275
Chapter 9 Motor Controller (MC10B8CV1)
9.4.1.3.2
Sign Bit (S)
Assuming RECIRC = 0 (the active state of the PWM signal is low), when the S bit for the corresponding channel is cleared, MnC0P (if the PWM channel number is even, n = 0, 1, 2, 3, see Table 9-10) or MnC1P (if the PWM channel number is odd, n = 0, 1, 2, 3, see Table 9-10), outputs a logic high while in (dual) full H-bridge mode. In half H-bridge mode the state of the S bit has no effect. The PWM output signal is generated on MnC0M (if the PWM channel number is even, n = 0, 1, 2, 3, see Table 9-10) or MnC1M (if the PWM channel number is odd, n = 0, 1, 2, 3). Assuming RECIRC = 0 (the active state of the PWM signal is low), when the S bit for the corresponding channel is set, MnC0M (if the PWM channel number is even, n = 0, 1, 2, 3, see Table 9-10) or MnC1M (if the PWM channel number is odd, n = 0, 1, 2, 3, see Table 9-10), outputs a logic high while in (dual) full H-bridge mode. In half H-bridge mode the state of the S bit has no effect. The PWM output signal is generated on MnC0P (if the PWM channel number is even, n = 0, 1, 2, 3, see Table 9-10) or MnC1P (if the PWM channel number is odd, n = 0, 1, 2, 3). Setting RECIRC = 1 will also invert the effect of the S bit such that while S = 0, MnC0P or MnC1P will generate the PWM signal and MnC0M or MnC1M will be a static low output. While S = 1, MnC0M or MnC1M will generate the PWM signal and MnC0P or MnC1P will be a static low output. In this case the active state of the PWM signal will be high. See Table 9-11 for detailed information about the impact of SIGN and RECIRC bit on the PWM output.
Table 9-11. Impact of RECIRC and SIGN Bit on the PWM Output
Output Mode (Dual) Full H-Bridge (Dual) Full H-Bridge (Dual) Full H-Bridge (Dual) Full H-Bridge Half H-Bridge: PWM on MnCyM Half H-Bridge: PWM on MnCyP
1
RECIRC 0 0 1 1 Don't care Don't care
SIGN 0 1 0 1 Don't care Don't care
MnCyM PWM1 1 0 PWM PWM --
MnCyP 1 PWM PWM2 1 --3 PWM
PWM: The PWM signal is low active. e.g., the waveform starts with 0 in left aligned mode. Output M generates the PWM signal. Output P is static high. 2 PWM: The PWM signal is high active. e.g., the waveform starts with 1 in left aligned mode. output P generates the PWM signal. Output M is static low. 3 The state of the output transistors is not controlled by the motor controller.
9.4.1.3.3
RECIRC Bit
The RECIRC bit controls the flow of the recirculation current of the load. Setting RECIRC = 0 will cause recirculation current to flow through the high side transistors, and RECIRC = 1 will cause the recirculation current to flow through the low side transistors. The RECIRC bit is only active in (dual) full H-bridge modes. Effectively, RECIRC = 0 will cause a static high output on the output terminal not driven by the PWM, RECIRC = 1 will cause a static low output on the output terminals not driven by the PWM. To achieve the same current direction, the S bit behavior is inverted if RECIRC = 1. Figure 9-12, Figure 9-13, Figure 9-14, and Figure 9-15 illustrate the effect of the RECIRC bit in (dual) full H-bridge modes.
MC9S12HZ256 Data Sheet, Rev. 2.05 276 Freescale Semiconductor
Chapter 9 Motor Controller (MC10B8CV1)
RECIRC bit must be changed only while no PWM channel is operated in (dual) full H-bridge mode.
VDDM
Static 0
PWM 1
MnC0P Static 0
MnC0M PWM 1
VSSM
Figure 9-12. PWM Active Phase, RECIRC = 0, S = 0
VDDM
Static 0
PWM 0
MnC0P Static 0
MnC0M PWM 0
VSSM
Figure 9-13. PWM Passive Phase, RECIRC = 0, S = 0
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 277
Chapter 9 Motor Controller (MC10B8CV1)
VDDM
PWM 0
Static 1
MnC0P PWM 0 VSSM
MnC0M Static 1
Figure 9-14. PWM Active Phase, RECIRC = 1, S = 0
VDDM
PWM 1
Static 1
MnC0P PWM 1
MnC0M Static 1
VSSM
Figure 9-15. PWM Passive Phase, RECIRC = 1, S = 0
MC9S12HZ256 Data Sheet, Rev. 2.05 278 Freescale Semiconductor
Chapter 9 Motor Controller (MC10B8CV1)
9.4.1.3.4
Relationship Between RECIRC Bit, S Bit, MCOM Bits, PWM State, and Output Transistors
Please refer to Figure 9-16 for the output transistor assignment.
VDDM
T1
T3
MnCyP T2
MnCyM T4
VSSM
Figure 9-16. Output Transistor Assignment
Table 9-12 illustrates the state of the output transistors in different states of the PWM motor controller module. `--' means that the state of the output transistor is not controlled by the motor controller.
Table 9-12. State of Output Transistors in Various Modes
Mode Off Half H-Bridge Half H-Bridge Half H-Bridge Half H-Bridge (Dual) Full (Dual) Full (Dual) Full (Dual) Full (Dual) Full (Dual) Full (Dual) Full (Dual) Full MCOM[1:0] Don't care 00 00 01 01 10 or 11 10 or 11 10 or 11 10 or 11 10 or 11 10 or 11 10 or 11 10 or 11 PWM Duty -- Active Passive Active Passive Active Passive Active Passive Active Passive Active Passive RECIRC Don't care Don't care Don't care Don't care Don't care 0 0 0 0 1 1 1 1 S Don't care Don't care Don't care Don't care Don't care 0 0 1 1 0 0 1 1 T1 -- -- -- OFF ON ON ON OFF ON ON OFF OFF OFF T2 -- -- -- ON OFF OFF OFF ON OFF OFF ON ON ON T3 -- OFF ON -- -- OFF ON ON ON OFF OFF ON OFF T4 -- ON OFF -- -- ON OFF OFF OFF ON ON OFF ON
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 279
Chapter 9 Motor Controller (MC10B8CV1)
9.4.1.3.5
Dither Bit (DITH)
The purpose of the dither mode is to increase the minimum length of output pulses without decreasing the PWM resolution, in order to limit the pulse distortion introduced by the slew rate control of the outputs. If dither mode is selected the output pattern will repeat after two timer counter overflows. For the same output frequency, the shortest output pulse will have twice the length while dither feature is selected. To achieve the same output frame frequency, the prescaler of the MC10B8C module has to be set to twice the division rate if dither mode is selected; e.g., with the same prescaler division rate the repeat rate of the output pattern is the same as well as the shortest output pulse with or without dither mode selected. The DITH bit in control register 0 enables or disables the dither function. DITH = 0: dither function is disabled. When DITH is cleared and assuming left aligned operation and RECIRC = 0, the PWM output will start at a logic low level at the beginning of the PWM period (motor controller timer counter = 0x000). The PWM output remains low until the motor controller timer counter matches the 11-bit PWM duty cycle value, DUTY, contained in D[10:0] in MCDCx. When a match (output compare between motor controller timer counter and DUTY) occurs, the PWM output will toggle to a logic high level and will remain at a logic high level until the motor controller timer counter overflows (reaches the contents of MCPER - 1). After the motor controller timer counter resets to 0x000, the PWM output will return to a logic low level. This completes one PWM period. The PWM period repeats every P counts (as defined by the bits P[10:0] in the motor controller period register) of the motor controller timer counter. If DUTY >= P, the output will be static low. If DUTY = 0x0000, the output will be continuously at a logic high level. The relationship between the motor controller timer counter clock, motor controller timer counter value, and PWM output while DITH = 0 is shown in Figure 9-17.
Motor Controller Timer Counter Clock Motor Controller Timer Counter
0
100
199 0
100
199 0
PWM Output 1 Period 200 Counts 1 Period 200 Counts
Figure 9-17. PWM Output: DITH = 0, MCAM[1:0] = 01, MCDC = 100, MCPER = 200, RECIRC = 0
DITH = 1: dither function is enabled Please note if DITH = 1, the bit P0 in the motor controller period register will be internally forced to 0 and read always as 0. When DITH is set and assuming left aligned operation and RECIRC = 0, the PWM output will start at a logic low level at the beginning of the PWM period (when the motor controller timer counter = 0x000). The PWM output remains low until the motor controller timer counter matches the 10-bit PWM duty cycle
MC9S12HZ256 Data Sheet, Rev. 2.05 280 Freescale Semiconductor
Chapter 9 Motor Controller (MC10B8CV1)
value, DUTY, contained in D[10:1] in MCDCx. When a match (output compare between motor controller timer counter and DUTY) occurs, the PWM output will toggle to a logic high level and will remain at a logic high level until the motor controller timer counter overflows (reaches the value defined by P[10:1] - 1 in MCPER). After the motor controller timer counter resets to 0x000, the PWM output will return to a logic low level. This completes the first half of the PWM period. During the second half of the PWM period, the PWM output will remain at a logic low level until either the motor controller timer counter matches the 10-bit PWM duty cycle value, DUTY, contained in D[10:1] in MCDCx if D0 = 0, or the motor controller timer counter matches the 10-bit PWM duty cycle value + 1 (the value of D[10:1] in MCDCx is increment by 1 and is compared with the motor controller timer counter value) if D0 = 1 in the corresponding duty cycle register. When a match occurs, the PWM output will toggle to a logic high level and will remain at a logic high level until the motor controller timer counter overflows (reaches the value defined by P[10:1] - 1 in MCPER). After the motor controller timer counter resets to 0x000, the PWM output will return to a logic low level. This process will repeat every number of counts of the motor controller timer counter defined by the period register contents (P[10:0]). If the output is neither set to 0% nor to 100% there will be four edges on the PWM output per PWM period in this case. Therefore, the PWM output compare function will alternate between DUTY and DUTY + 1 every half PWM period if D0 in the corresponding duty cycle register is set to 1. The relationship between the motor controller timer counter clock (fTC), motor controller timer counter value, and left aligned PWM output if DITH = 1 is shown in Figure 9-18 and Figure 9-19. Figure 9-20 and Figure 9-21 show right aligned and center aligned PWM operation respectively, with dither feature enabled and D0 = 1. Please note: In the following examples, the MCPER value is defined by the bits P[10:0], which is, if DITH = 1, always an even number. NOTE The DITH bit must be changed only if the motor controller is disabled (all channels disabled or period register cleared) to avoid erroneous waveforms.
Motor Controller Timer Counter Clock Motor Controller 0 Timer Counter PWM Output 1 Period 100 Counts 100 Counts 15 16 99 0 15 16 99 0
Figure 9-18. PWM Output: DITH = 1, MCAM[1:0] = 01, MCDC = 31, MCPER = 200, RECIRC = 0
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 281
Chapter 9 Motor Controller (MC10B8CV1)
Motor Controller Timer Counter Clock Motor Controller Timer Counter PWM Output 1 Period 100 Counts 100 Counts 0 15 16 99 0 15 16 99 0
Figure 9-19. PWM Output: DITH = 1, MCAM[1:0] = 01, MCDC = 30, MCPER = 200, RECIRC = 0
.
Motor Controller Timer Counter Clock Motor Controller 0 Timer Counter PWM Output 1 Period 100 Counts 100 Counts 84 85 99 0 84 85 99 0
Figure 9-20. PWM Output: DITH = 1, MCAM[1:0] = 10, MCDC = 31, MCPER = 200, RECIRC = 0
Motor Controller Timer Counter Clock Motor Controller 0 Timer Counter PWM Output 1 Period 100 Counts 100 Counts 15 99 0 84 99 0
Figure 9-21. PWM Output: DITH = 1, MCAM[1:0] = 11, MCDC = 31, MCPER = 200, RECIRC = 0
MC9S12HZ256 Data Sheet, Rev. 2.05 282 Freescale Semiconductor
Chapter 9 Motor Controller (MC10B8CV1)
9.4.2
PWM Duty Cycle
The PWM duty cycle for the motor controller channel x can be determined by dividing the decimal representation of bits D[10:0] in MCDCx by the decimal representation of the bits P[10:0] in MCPER and multiplying the result by 100% as shown in the equation below: DUTY Effective PWM Channel X % Duty Cycle = --------------------- 100% MCPER NOTE x = PWM Channel Number = 0, 1, 2, 3 ... 8. This equation is only valid if DUTY <= MCPER and MCPER is not equal to 0. Whenever D[10:0] >= P[10:0], a constant low level (RECIRC = 0) or high level (RECIRC = 1) will be output.
9.4.3
Motor Controller Counter Clock Source
Figure 9-22 shows how the PWM motor controller timer counter clock source is selected.
Clock Generator CLK Peripheral Bus Clock fBUS Clocks and Reset Generator Module
Motor Controller Timer Counter Clock Prescaler Select MPPRE0, MPPRE1
1 1/2 1/4 1/8
Motor Controller Timer Counter Clock fTC
11-Bit Motor Controller Timer Counter
Motor Controller Timer Counter Prescaler
Figure 9-22. Motor Controller Counter Clock Selection
The peripheral bus clock is the source for the motor controller counter prescaler. The motor controller counter clock rate, fTC, is set by selecting the appropriate prescaler value. The prescaler is selected with the MCPRE[1:0] bits in motor controller control register 0 (MCCTL0). The motor controller channel frequency of operation can be calculated using the following formula if DITH = 0: fTC Motor Channel Frequency (Hz) = -----------------------------MCPER M
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 283
Chapter 9 Motor Controller (MC10B8CV1)
The motor controller channel frequency of operation can be calculated using the following formula if DITH = 1: fTC Motor Channel Frequency (Hz) = ------------------------------------MCPER M 2 NOTE Both equations are only valid if MCPER is not equal to 0. M = 1 for left or right aligned mode, M = 2 for center aligned mode. Table 9-13 shows examples of the motor controller channel frequencies that can be generated based on different peripheral bus clock frequencies and the prescaler value.
Table 9-13. Motor Controller Channel Frequencies (Hz), MCPER = 256, DITH = 0, MCAM = 10, 01
Peripheral Bus Clock Frequency Prescaler 1 1/2 1/4 1/8 16 MHz 62500 31250 15625 7813 10 MHz 39063 19531 9766 4883 8 MHz 31250 15625 7813 3906 5 MHz 19531 9766 4883 2441 4 MHz 15625 7813 3906 1953
NOTE Due to the selectable slew rate control of the outputs, clipping may occur on short output pulses.
9.4.4
Output Switching Delay
In order to prevent large peak current draw from the motor power supply, selectable delays can be used to stagger the high logic level to low logic level transitions on the motor controller outputs. The timing delay, td, is determined by the CD[1:0] bits in the corresponding channel control register (MCMCx) and is selectable between 0, 1, 2, or 3 motor controller timer counter clock cycles. NOTE A PWM channel gets disabled at the next timer counter overflow without notice of the switching delay.
MC9S12HZ256 Data Sheet, Rev. 2.05 284 Freescale Semiconductor
Chapter 9 Motor Controller (MC10B8CV1)
9.4.5
Operation in Wait Mode
During wait mode, the operation of the motor controller pins are selectable between the following two options: 1. MCSWAI = 1: All module clocks are stopped and the associated port pins are set to their inactive state, which is defined by the state of the RECIRC bit during wait mode. The motor controller module registers stay the same as they were prior to entering wait mode. Therefore, after exiting from wait mode, the associated port pins will resume to the same functionality they had prior to entering wait mode. 2. MCSWAI = 0: The PWM clocks continue to run and the associated port pins maintain the functionality they had prior to entering wait mode both during wait mode and after exiting wait mode.
9.4.6
Operation in Stop and Pseudo-Stop Modes
All module clocks are stopped and the associated port pins are set to their inactive state, which is defined by the state of the RECIRC bit. The motor controller module registers stay the same as they were prior to entering stop or pseudo-stop modes. Therefore, after exiting from stop or pseudo-stop modes, the associated port pins will resume to the same functionality they had prior to entering stop or pseudo-stop modes.
9.5
Reset
The motor controller is reset by system reset. All associated ports are released, all registers of the motor controller module will switch to their reset state as defined in Section 9.3.2, "Register Descriptions".
9.6
Interrupts
The motor controller has one interrupt source.
9.6.1
Timer Counter Overflow Interrupt
An interrupt will be requested when the MCTOIE bit in the motor controller control register 1 is set and the running PWM frame is finished. The interrupt is cleared by either setting the MCTOIE bit to 0 or to write a 1 to the MCTOIF bit in the motor controller control register 0.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 285
Chapter 9 Motor Controller (MC10B8CV1)
9.7
Initialization/Application Information
This section provides an example of how the PWM motor controller can be initialized and used by application software. The configuration parameters (e.g., timer settings, duty cycle values, etc.) are not guaranteed to be adequate for any real application. The example software is implemented in assembly language.
9.7.1
Code Example
One way to use the motor controller is: 1. Perform global initialization a) Set the motor controller control registers MCCTL0 and MCCTL1 to appropriate values. i) Prescaler disabled (MCPRE1 = 0, MCPRE0 = 0). ii) Fast mode and dither disabled (FAST = 0, DITH = 0). iii) Recirculation feature in dual full H-bridge mode disabled (RECIRC = 0). All other bits in MCCTL0 and MCCTL1 are set to 0. b) Configure the channel control registers for the desired mode. i) Dual full H-bridge mode (MCOM[1:0] = 11). ii) Left aligned PWM (MCAM[1:0] = 01). iii) No channel delay (MCCD[1:0] = 00). 2. Perform the startup phase a) Clear the duty cycle registers MCDC0 and MCDC1 b) Initialize the period register MCPER, which is equivalent to enabling the motor controller. c) Enable the timer which generates the timebase for the updates of the duty cycle registers. 3. Main program a) Check if pin PB0 is set to "1" and execute the sub program if a timer interrupt is pending. b) Initiate the shutdown procedure if pin PB0 is set to "0". 4. Sub program a) Update the duty cycle registers Load the duty cycle registers MCDC0 and MCDC1 with new values from the table and clear the timer interrupt flag. The sub program will initiate the shutdown procedure if pin PB0 is set to "0". b) Shutdown procedure The timer is disabled and the duty cycle registers are cleared to drive an inactive value on the PWM output as long as the motor controller is enabled. The period register is cleared after a certain time, which disables the motor controller. The table address is restored and the timer interrupt flag is cleared.
MC9S12HZ256 Data Sheet, Rev. 2.05 286 Freescale Semiconductor
Chapter 9 Motor Controller (MC10B8CV1)
;-----------------------------------------------------------------------------------------; Motor Controller (MC10B8C) setup example ;-----------------------------------------------------------------------------------------; Timer defines ;-----------------------------------------------------------------------------------------T_START EQU $0040 TSCR1 EQU T_START+$06 TFLG2 EQU T_START+$0F ;-----------------------------------------------------------------------------------------; Motor Controller defines ;-----------------------------------------------------------------------------------------MC_START EQU $0200 MCCTL0 EQU MC_START+$00 MCCTL1 EQU MC_START+$01 MCPER_HI EQU MC_START+$02 MCPER_LO EQU MC_START+$03 MCCC0 EQU MC_START+$10 MCCC1 EQU MC_START+$11 MCCC2 EQU MC_START+$12 MCCC3 EQU MC_START+$13 MCDC0_HI EQU MC_START+$20 MCDC0_LO EQU MC_START+$21 MCDC1_HI EQU MC_START+$22 MCDC1_LO EQU MC_START+$23 MCDC2_HI EQU MC_START+$24 MCDC2_LO EQU MC_START+$25 MCDC3_HI EQU MC_START+$26 MCDC3_LO EQU MC_START+$27 ;-----------------------------------------------------------------------------------------; Port defines ;-----------------------------------------------------------------------------------------DDRB EQU $0003 PORTB EQU $0001 ;-----------------------------------------------------------------------------------------; Flash defines ;-----------------------------------------------------------------------------------------FLASH_START EQU $0100 FCMD EQU FLASH_START+$06 FCLKDIV EQU FLASH_START+$00 FSTAT EQU FLASH_START+$05 FTSTMOD EQU FLASH_START+$02 ; Variables CODE_START EQU $1000 ; start of program code DTYDAT EQU $1500 ; start of motor controller duty cycle data TEMP_X EQU $1700 ; save location for IX reg in ISR TABLESIZE EQU $1704 ; number of config entries in the table MCPERIOD EQU $0250 ; motor controller period ;-----------------------------------------------------------------------------------------;-----------------------------------------------------------------------------------------ORG CODE_START ; start of code LDS #$1FFF ; set stack pointer MOVW #$000A,TABLESIZE ; number of configurations in the table MOVW TABLESIZE,TEMP_X
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 287
Chapter 9 Motor Controller (MC10B8CV1)
;-----------------------------------------------------------------------------------------;global motor controller init ;-----------------------------------------------------------------------------------------GLB_INIT: MOVB #$0000,MCCTL0 ; fMC = fBUS, FAST=0, DITH=0 MOVB #$0000,MCCTL1 ; RECIRC=0, MCTOIE=0 MOVW #$D0D0,MCCC0 ; dual full h-bridge mode, left aligned, ; no channel delay MOVW #$0000,MCPER_HI ; disable motor controller ;-----------------------------------------------------------------------------------------;motor controller startup ;-----------------------------------------------------------------------------------------STARTUP: MOVW #$0000,MCDC0_HI ; define startup duty cycles MOVW #$0000,MCDC1_HI MOVW #MCPERIOD,MCPER_HI ; define PWM period MOVB #$80,TSCR1 ; enable timer MAIN: LDAA PORTB ; if PB=0, activate shutdown ANDA #$01 BEQ MN0 JSR TIM_SR MN0: TST TFLG2 ; poll for timer counter overflow flag BEQ MAIN ; TOF set? JSR TIM_SR ; yes, go to TIM_SR BRA MAIN TIM_SR: LDX TEMP_X ; restore index register X LDAA PORTB ; if PB=0, enter shutdown routine ANDA #$01 BNE SHUTDOWN LDX TEMP_X ; restore index register X BEQ NEW_SEQ ; all mc configurations done? NEW_CFG: LDD DTYDAT,X ; load new config's STD MCDC0_HI DEX DEX LDD DTYDAT,X STD MCDC1_HI BRA END_SR ; leave sub-routine SHUTDOWN: MOVB #$00,TSCR1 ; disable timer MOVW #$0000,MCDC0_HI ; define startup duty cycle MOVW #$0000,MCDC1_HI ; define startup duty cycle LDAA #$0000 ; ensure that duty cycle registers are ; cleared for some time before disabling ; the motor controller LOOP DECA BNE LOOP MOVW #$0000,MCPER_HI ; define pwm period NEW_SEQ: MOVW TABLESIZE,TEMP_X ; start new tx loop LDX TEMP_X END_SR: STX TEMP_X ; save byte counter MOVB #$80,TFLG2 ; clear TOF RTS ; wait for new timer overflow
MC9S12HZ256 Data Sheet, Rev. 2.05 288 Freescale Semiconductor
Chapter 9 Motor Controller (MC10B8CV1)
;-----------------------------------------------------------------------------------------; motor controller duty cycles ;-----------------------------------------------------------------------------------------org DTYDAT DC.B $02, $FF1; MCDC1_HI, MCDC1_LO DC.B $02, $D0 ; MCDC0_HI, MCDC0_LO DC.B $02, $A0 ; MCDC1_HI, MCDC1_LO DC.B $02, $90 ; MCDC0_HI, MCDC0_LO DC.B $02, $60 ; MCDC1_HI, MCDC1_LO DC.B $02, $25 ; MCDC0_HI, MCDC0_LO
1. The values for the duty cycle table have to be defined for the needs of the target application. MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 289
Chapter 9 Motor Controller (MC10B8CV1)
MC9S12HZ256 Data Sheet, Rev. 2.05 290 Freescale Semiconductor
Chapter 10 Stepper Stall Detector (SSDV1)
10.1 Introduction
The stepper stall detector (SSD) block provides a circuit to measure and integrate the induced voltage on the non-driven coil of a stepper motor using full steps when the gauge pointer is returning to zero (RTZ). During the RTZ event, the pointer is returned to zero using full steps in either clockwise or counter clockwise direction, where only one coil is driven at any point in time. The back electromotive force (EMF) signal present on the non-driven coil is integrated after a blanking time, and its results stored in a 16-bit accumulator. The 16-bit modulus down counter can be used to monitor the blanking time and the integration time. The value in the accumulator represents the change in linked flux (magnetic flux times the number of turns in the coil) and can be compared to a stored threshold. Values above the threshold indicate a moving motor, in which case the pointer can be advanced another full step in the same direction and integration be repeated. Values below the threshold indicate a stalled motor, thereby marking the cessation of the RTZ event. The SSD is capable of multiplexing two stepper motors.
10.1.1
*
Modes of Operation
*
Return to zero modes -- Blanking with no drive -- Blanking with drive -- Conversion -- Integration Low-power modes
10.1.2
* * * * * *
Features
Programmable full step state Programmable integration polarity Blanking (recirculation) state 16-bit integration accumulator register 16-bit modulus down counter with interrupt Multiplex two stepper motors
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 291
Chapter 10 Stepper Stall Detector (SSDV1)
10.1.3
Block Diagram
Coil COSx x = A or B Coil SINx
VDDM
VDDM
VDDM
VDDM
T1
COSxP COSxM
T3
T5
SINxP SINxM
T7
P A D
T2
S1 S2
S3 S4 T4
P A D
P A D
T6
S5 S6
S7 S8 T8
P A D
VSSM
VSSM
VSSM
VSSM
reference integrator
DAC C1
R1
- +
VDDM
-
DFF
+
16-bit accumulator register 16-bit load register 16-bit modulus down counter
R2
R2
sigma-delta converter (analog)
VSSM
4:1 MUX
2:1 MUX
Bus Clock
1/8
1/2
1/2
1/2
1/8
Figure 10-1. SSD Block Diagram
MC9S12HZ256 Data Sheet, Rev. 2.05 292 Freescale Semiconductor
Chapter 10 Stepper Stall Detector (SSDV1)
10.2
External Signal Description
Each SSD signal is the output pin of a half bridge, designed to source or sink current. The H-bridge pins drive the sine and cosine coils of a stepper motor to provide four-quadrant operation. The SSD is capable of multiplexing between stepper motor A and stepper motor B if two motors are connected.
Table 10-1. Pin Table1
Pin Name COSxM COSxP SINxM SINxP
1
Node Minus Plus Minus Plus
Coil COSx
SINx
x = A or B indicating motor A or motor B
10.2.1
COSxM/COSxP -- Cosine Coil Pins for Motor x
These pins interface to the cosine coils of a stepper motor to measure the back EMF for calibration of the pointer reset position.
10.2.2
SINxM/SINxP -- Sine Coil Pins for Motor x
These pins interface to the sine coils of a stepper motor to measure the back EMF for calibration of the pointer reset position.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 293
Chapter 10 Stepper Stall Detector (SSDV1)
10.3
Memory Map and Register Definition
This section provides a detailed description of all registers of the stepper stall detector (SSD) block.
10.3.1
Module Memory Map
Table 10-2 gives an overview of all registers in the SSD memory map. The SSD occupies eight bytes in the memory space. The register address results from the addition of base address and address offset. The base address is determined at the MCU level and is given in the Device Overview chapter. The address offset is defined at the block level and is given here.
Table 10-2. SSD Memory Map
Address Offset 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 RTZCTL MDCCTL SSDCTL SSDFLG MDCCNT (High) MDCCNT (Low) ITGACC (High) ITGACC (Low) Use Access R/W R/W R/W R/W R/W R/W R R
10.3.2
Register Descriptions
This section describes in detail all the registers and register bits in the SSD block. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order.
MC9S12HZ256 Data Sheet, Rev. 2.05 294 Freescale Semiconductor
Chapter 10 Stepper Stall Detector (SSDV1)
10.3.2.1
Return-to-Zero Control Register (RTZCTL)
7 6 5 4 3 2 1 0
R ITG W Reset 0 0 0 0 DCOIL RCIR POL
0 SMS 0 0 0 STEP 0
= Unimplemented or Reserved
Figure 10-2. Return-to-Zero Control Register (RTZCTL)
Read: anytime Write: anytime
Table 10-3. RTZCTL Field Descriptions
Field 7 ITG Description Integration -- During return to zero (RTZE = 1), one of the coils must be recirculated or non-driven determined by the STEP field. If the ITG bit is set, the coil is non-driven, and if the ITG bit is clear, the coil is being recirculated. Table 10-4 shows the condition state of each transistor from Figure 10-1 based on the STEP, ITG, DCOIL and RCIR bits. Regardless of the RTZE bit value, if the ITG bit is set, one end of the non-driven coil connects to the (non-zero) reference input and the other end connects to the integrator input of the sigma-delta converter. Regardless of the RTZE bit value, if the ITG bit is clear, the non-driven coil is in a blanking state, the converter is in a reset state, and the accumulator is initialized to zero. Table 10-5 shows the condition state of each switch from Figure 10-1 based on the ITG, STEP and POL bits. 0 Blanking 1 Integration Drive Coil -- During return to zero (RTZE=1), one of the coils must be driven determined by the STEP field. If the DCOIL bit is set, this coil is driven. If the DCOIL bit is clear, this coil is disconnected or drivers turned off. Table 10-4 shows the condition state of each transistor from Figure 10-1 based on the STEP, ITG, DCOIL and RCIR bits. 0 Disconnect Coil 1 Drive Coil Recirculation in Blanking Mode -- During return to zero (RTZE = 1), one of the coils is recirculated prior to integration during the blanking period. This bit determines if the coil is recirculated via VDDM or via VSSM. Table 10-4 shows the condition state of each transistor from Figure 10-1 based on the STEP, ITG, DCOIL and RCIR bits. 0 Recirculation on the high side transistors 1 Recirculation on the low side transistors Polarity -- This bit determines which end of the non-driven coil is routed to the sigma-delta converter during conversion or integration mode. Table 10-5 shows the condition state of each switch from Figure 10-1 based on the ITG, STEP and POL bits. Stepper Motor Select -- This bit selects one of two possible stepper motors to be used for stall detection. See top level chip description for the stepper motor assignments to the SSD. 0 Stepper Motor A is selected for stall detection 1 Stepper Motor B is selected for stall detection Full Step State -- This field indicates one of the four possible full step states. Step 0 is considered the east pole or 0 angle, step 1 is the north Pole or 90 angle, step 2 is the west pole or 180 angle, and step 3 is the south pole or 270 angle. For each full step state, Table 10-6 shows the current through each of the two coils, and the coil nodes that are multiplexed to the sigma-delta converter during conversion or integration mode.
6 DCOIL
5 RCIR
4 POL 2 SMS
1:0 STEP
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 295
Chapter 10 Stepper Stall Detector (SSDV1)
Table 10-4. Transistor Condition States (RTZE = 1)
STEP xx 00 00 00 00 00 01 01 01 01 01 10 10 10 10 10 11 11 11 11 11 ITG 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 DCOIL 0 0 0 1 1 1 0 0 1 1 1 0 0 1 1 1 0 0 1 1 1 RCIR x 0 1 0 1 x 0 1 0 1 x 0 1 0 1 x 0 1 0 1 x T1 OFF OFF OFF ON ON ON ON OFF ON OFF OFF OFF OFF OFF OFF OFF ON OFF ON OFF OFF T2 OFF OFF OFF OFF OFF OFF OFF ON OFF ON OFF OFF OFF ON ON ON OFF ON OFF ON OFF T3 OFF OFF OFF OFF OFF OFF ON OFF ON OFF OFF OFF OFF ON ON ON ON OFF ON OFF OFF T4 OFF OFF OFF ON ON ON OFF ON OFF ON OFF OFF OFF OFF OFF OFF OFF ON OFF ON OFF T5 OFF ON OFF ON OFF OFF OFF OFF ON ON ON ON OFF ON OFF OFF OFF OFF OFF OFF OFF T6 OFF OFF ON OFF ON OFF OFF OFF OFF OFF OFF OFF ON OFF ON OFF OFF OFF ON ON ON T7 OFF ON OFF ON OFF OFF OFF OFF OFF OFF OFF ON OFF ON OFF OFF OFF OFF ON ON ON T8 OFF OFF ON OFF ON OFF OFF OFF ON ON ON OFF ON OFF ON OFF OFF OFF OFF OFF OFF
Table 10-5. Switch Condition States (RTZE = 1 or 0)
ITG 0 1 1 1 1 1 1 1 1 STEP xx 00 00 01 01 10 10 11 11 POL x 0 1 0 1 0 1 0 1 S1 Open Open Open Open Close Open Open Close Open S2 Open Open Open Close Open Open Open Open Close S3 Open Open Open Close Open Open Open Open Close S4 Open Open Open Open Close Open Open Close Open S5 Open Close Open Open Open Open Close Open Open S6 Open Open Close Open Open Close Open Open Open S7 Open Open Close Open Open Close Open Open Open S8 Open Close Open Open Open Open Close Open Open
MC9S12HZ256 Data Sheet, Rev. 2.05 296 Freescale Semiconductor
Chapter 10 Stepper Stall Detector (SSDV1)
Table 10-6. Full Step States
COSINE Coil Current STEP Pole Angle DCOIL = 0 DCOIL = 1 DCOIL = 0 DCOIL = 1 0 1 2 3 East North West South 0 90 180 270 0 0 0 0 + I max 0 - I max 0 0 0 0 0 0 + I max 0 - I max SINE Coil Current Coil Node to Integrator input (Close Switch) ITG = 1 POL = 0 SINxM (S8) ITG = 1 POL = 1 SINxP (S6) Coil Node to Reference input (Close Switch) ITG = 1 POL = 0 SINxP (S5) ITG = 1 POL = 1 SINxM (S7)
COSxP (S2) COSxM (S4) COSxM (S3) COSxP (S1) SINxP (S6) SINxM (S8) SINxM (S7) SINxP (S5)
COSxM (S4) COSxP (S2) COSxP (S1) COSxM (S3)
10.3.2.2
Modulus Down Counter Control Register (MDCCTL)
7 6 5 4 3 2 1 0
R MCZIE W Reset 0 0 0 0 MODMC RDMCL PRE
0 MCEN FLMC 0 0
0 AOVIE 0 0
= Unimplemented or Reserved
Figure 10-3. Modulus Down Counter Control Register (MDCCTL)
Read: anytime Write: anytime.
l
Table 10-7. MDCCTL Field Descriptions
Field 7 MCZIE Description Modulus Counter Underflow Interrupt Enable 0 Interrupt disabled. 1 Interrupt enabled. An interrupt will be generated when the modulus counter underflow interrupt flag (MCZIF) is set. Modulus Mode Enable 0 The modulus counter counts down from the value in the counter register and will stop at 0x0000. 1 Modulus mode is enabled. When the counter reaches 0x0000, the counter is loaded with the latest value written to the modulus counter register. Note: For proper operation, the MCEN bit should be cleared before modifying the MODMC bit in order to reset the modulus counter to 0xFFFF. Read Modulus Down-Counter Load 0 Reads of the modulus count register (MDCCNT) will return the present value of the count register. 1 Reads of the modulus count register (MDCCNT) will return the contents of the load register. Prescaler 0 The modulus down counter clock frequency is the bus frequency divided by 64. 1 The modulus down counter clock frequency is the bus frequency divided by 512. Note: A change in the prescaler division rate will not be effective until a load of the load register into the modulus counter count register occurs.
6 MODMC
5 RDMCL 4 PRE
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 297
Chapter 10 Stepper Stall Detector (SSDV1)
Table 10-7. MDCCTL Field Descriptions (continued)
Field 3 FLMC 2 MCEN Description Force Load Register into the Modulus Counter Count Register -- This bit always reads zero. 0 Write zero to this bit has no effect. 1 Write one into this bit loads the load register into the modulus counter count register. Modulus Down-Counter Enable 0 Modulus down-counter is disabled. The modulus counter (MDCCNT) is preset to 0xFFFF. This will prevent an early interrupt flag when the modulus down-counter is enabled. 1 Modulus down-counter is enabled. Accumulator Overflow Interrupt Enable 0 Interrupt disabled. 1 Interrupt enabled. An interrupt will be generated when the accumulator overflow interrupt flag (AOVIF) is set.
0 AOVIE
10.3.2.3
Stepper Stall Detector Control Register (SSDCTL)
7 6 5 4 3 2 1 0
R RTZE W Reset 0 0 0 0 SDCPU SSDWAI FTST
0
0 ACLKS
0
0
0
0
= Unimplemented or Reserved
Figure 10-4. Stepper Stall Detector Control Register (SSDCTL)
Read: anytime Write: anytime
l
Table 10-8. SSDCTL Field Descriptions
Field 7 RTZE Description Return to Zero Enable -- If this bit is set, the coils are controlled by the SSD and are configured into one of the four full step states as shown in Table 10-6. If this bit is cleared, the coils are not controlled by the SSD. 0 RTZ is disabled. 1 RTZ is enabled. Sigma-Delta Converter Power Up -- This bit provides on/off control for the sigma-delta converter allowing reduced MCU power consumption. Because the analog circuit is turned off when powered down, the sigma-delta converter requires a recovery time after it is powered up. 0 Sigma-delta converter is powered down. 1 Sigma-delta converter is powered up. SSD Disabled during Wait Mode -- When entering Wait Mode, this bit provides on/off control over the SSD allowing reduced MCU power consumption. Because the analog circuit is turned off when powered down, the sigma-delta converter requires a recovery time after exit from Wait Mode. 0 SSD continues to run in WAIT mode. 1 Entering WAIT mode freezes the clock to the prescaler divider, powers down the sigma-delta converter, and if RTZE bit is set, the sine and cosine coils are recirculated via VSSM.
6 SDCPU
5 SSDWAI
MC9S12HZ256 Data Sheet, Rev. 2.05 298 Freescale Semiconductor
Chapter 10 Stepper Stall Detector (SSDV1)
Table 10-8. SSDCTL Field Descriptions (continued)
Field 4 FTST 1:0 ACLKS Description Factory Test -- This bit is reserved for factory test and reads zero in user mode. Accumulator Sample Frequency Select -- This field sets the accumulator sample frequency by pre-scaling the bus frequency by a factor of 8, 16, 32, or 64. A faster sample frequency can provide more accurate results but cause the accumulator to overflow. Best results are achieved with a frequency between 500 kHz and 2 MHz. Accumulator Sample Frequency = fBUS / (8 x 2ACLKS)
Table 10-9. Accumulator Sample Frequency
ACLKS 0 1 2 3 Frequency fBUS / 8 fBUS / 16 fBUS / 32 fBUS / 64 fBUS = 40 MHz 5.00 MHz 2.50 MHz 1.25 MHz 625 kHz fBUS = 25 MHz 3.12 MHz 1.56 MHz 781 kHz 391 kHz fBUS = 16 MHz 2.00 MHz 1.00 MHz 500 kHz 250 kHz
NOTE
A change in the accumulator sample frequency will not be effective until the ITG bit is cleared.
10.3.2.4
Stepper Stall Detector Flag Register (SSDFLG)
7 6 5 4 3 2 1 0
R MCZIF W Reset 0
0
0
0
0
0
0 AOVIF
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 10-5. Stepper Stall Detector Flag Register (SSDFLG)
Read: anytime Write: anytime.
l
Table 10-10. SSDFLG Field Descriptions
Field 7 MCZIF 0 AOVIF Description Modulus Counter Underflow Interrupt Flag -- This flag is set when the modulus down-counter reaches 0x0000. If not masked (MCZIE = 1), a modulus counter underflow interrupt is pending while this flag is set. This flag is cleared by writing a `1' to the bit. A write of `0' has no effect. Accumulator Overflow Interrupt Flag -- This flag is set when the Integration Accumulator has a positive or negative overflow. If not masked (AOVIE = 1), an accumulator overflow interrupt is pending while this flag is set. This flag is cleared by writing a `1' to the bit. A write of `0' has no effect.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 299
Chapter 10 Stepper Stall Detector (SSDV1)
10.3.2.5
Modulus Down-Counter Count Register (MDCCNT)
15 14 13 12 11 10 9 8
R MDCCNT W Reset 1 1 1 1 1 1 1 1
Figure 10-6. Modulus Down-Counter Count Register High (MDCCNT)
7 6 5 4 3 2 1 0
R MDCCNT W Reset 1 1 1 1 1 1 1 1
Figure 10-7. Modulus Down-Counter Count Register Low (MDCCNT)
Read: anytime Write: anytime.
NOTE
A separate read/write for high byte and low byte gives a different result than accessing the register as a word. If the RDMCL bit in the MDCCTL register is cleared, reads of the MDCCNT register will return the present value of the count register. If the RDMCL bit is set, reads of the MDCCNT register will return the contents of the load register. With a 0x0000 write to the MDCCNT register, the modulus counter stays at zero and does not set the MCZIF flag in the SSDFLG register. If modulus mode is not enabled (MODMC = 0), a write to the MDCCNT register immediately updates the load register and the counter register with the value written to it. The modulus counter will count down from this value and will stop at 0x0000. If modulus mode is enabled (MODMC = 1), a write to the MDCCNT register updates the load register with the value written to it. The count register will not be updated with the new value until the next counter underflow. The FLMC bit in the MDCCTL register can be used to immediately update the count register with the new value if an immediate load is desired. The modulus down counter clock frequency is the bus frequency divided by 64 or 512.
MC9S12HZ256 Data Sheet, Rev. 2.05 300 Freescale Semiconductor
Chapter 10 Stepper Stall Detector (SSDV1)
10.3.2.6
Integration Accumulator Register (ITGACC)
15 14 13 12 11 10 9 8
R W Reset 0 0 0 0
ITGACC
0
0
0
0
Figure 10-8. Integration Accumulator Register High (ITGACC)
7 6 5 4 3 2 1 0
R W Reset 0 0 0 0
ITGACC
0
0
0
0
Figure 10-9. Integration Accumulator Register Low (ITGACC)
Read: anytime. Write: Never.
NOTE
A separate read for high byte and low byte gives a different result than accessing the register as a word. This 16-bit field is signed and is represented in two's complement. It indicates the change in flux while integrating the back EMF present in the non-driven coil during a return to zero event. When ITG is zero, the accumulator is initialized to 0x0000 and the sigma-delta converter is in a reset state. When ITG is one, the accumulator increments or decrements depending on the sigma-delta conversion sample. The accumulator sample frequency is determined by the ACLKS field. The accumulator freezes at 0x7FFF on a positive overflow and freezes at 0x8000 on a negative overflow.
10.4
Functional Description
The stepper stall detector (SSD) has a simple control block to configure the H-bridge drivers of a stepper motor in four different full step states with four available modes during a return to zero event. The SSD has a detect circuit using a sigma-delta converter to measure and integrate changes in flux of the de-energized winding in the stepping motor and the conversion result is accumulated in a 16-bit signed register. The SSD also has a 16-bit modulus down counter to monitor blanking and integration times. DC offset compensation is implemented when using the modulus down counter to monitor integration times.
10.4.1
Return to Zero Modes
Table 10-11. Return to Zero Modes
ITG DCOIL Mode
There are four return to zero modes as shown in Table 10-11.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 301
Chapter 10 Stepper Stall Detector (SSDV1)
Table 10-11. Return to Zero Modes
0 0 1 1 0 1 0 1 Blanking with no drive Blanking with drive Conversion Integration
10.4.1.1
Blanking with No Drive
In blanking mode with no drive, one of the coils is masked from the sigma-delta converter, and if RTZ is enabled (RTZE = 1), it is set up to recirculate its current. If RTZ is enabled (RTZE = 1), the other coil is disconnected to prevent any loss of flux change that would occur when the motor starts moving before the end of recirculation and start of integration. In blanking mode with no drive, the accumulator is initialized to 0x0000 and the converter is in a reset state.
10.4.1.2
Blanking with Drive
In blanking mode with drive, one of the coils is masked from the sigma-delta converter, and if RTZ is enabled (RTZE = 1), it is set up to recirculate its current. If RTZ is enabled (RTZE = 1), the other coil is driven. In blanking mode with drive, the accumulator is initialized to 0x0000 and the converter is in a reset state.
10.4.1.3
Conversion
In conversion mode, one of the coils is routed for integration with one end connected to the (non-zero) reference input and the other end connected to the integrator input of the sigma-delta converter. If RTZ is enabled (RTZE=1), both coils are disconnected. This mode is not useful for stall detection.
10.4.1.4
Integration
In integration mode, one of the coils is routed for integration with one end connected to the (non-zero) reference input and the other end connected to the integrator input of the sigma-delta converter. If RTZ is enabled (RTZE = 1), the other coil is driven. This mode is used to rectify and integrate the back EMF produced by the coils to detect stepped rotary motion. DC offset compensation is implemented when using the modulus down counter to monitor integration time.
10.4.2
Full Step States
During a return to zero (RTZ) event, the stepper motor pointer requires a 90 full motor electrical step with full amplitude pulses applied to each phase in turn. For counter clockwise rotation (CCW), the STEP value is incremented 0, 1, 2, 3, 0 and so on, and for a clockwise rotation the STEP value is decremented 3, 2, 1, 0 and so on. Figure 10-10 shows the current level through each coil for each full step in CCW rotation when DCOIL is set.
MC9S12HZ256 Data Sheet, Rev. 2.05 302 Freescale Semiconductor
Chapter 10 Stepper Stall Detector (SSDV1)
+ Imax SINE COIL CURRENT 0 _ Imax
Recirculation + Imax COSINE COIL CURRENT 0 _ Imax 0 1 2 3
Figure 10-10. Full Steps (CCW)
Figure 10-11 shows the current flow in the SINx and COSx H-bridges when STEP = 0, DCOIL = 1, ITG = 0 and RCIR = 0.
VDDM VDDM
T1
T3
T5
T7
COSxP
COSxM
SINxP
SINxM
T2
T4
VSSM
T6
T8
VSSM
Figure 10-11. Current Flow when STEP = 0, DCOIL = 1, ITG = 0, RCIR = 0
Figure 10-12 shows the current flow in the SINx and COSx H-bridges when STEP = 1, DCOIL = 1, ITG = 0 and RCIR = 1.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 303
Chapter 10 Stepper Stall Detector (SSDV1)
VDDM
VDDM
T1
T3
T5
T7
COSxP
COSxM
SINxP
SINxM
T2
T4
VSSM
T6
T8
VSSM
Figure 10-12. Current Flow when STEP = 1, DCOIL = 1, ITG = 0, RCIR = 1
Figure 10-13 shows the current flow in the SINx and COSx H-bridges when STEP = 2, DCOIL = 1 and ITG = 1.
VDDM VDDM
T1
T3
T5
T7
COSxP
COSxM
SINxP
SINxM
T2
T4
VSSM
T6
T8
VSSM
Figure 10-13. Current flow when STEP = 2, DCOIL = 1, ITG = 1
Figure 10-14 shows the current flow in the SINx and COSx H-bridges when STEP = 3, DCOIL = 1 and ITG = 1.
MC9S12HZ256 Data Sheet, Rev. 2.05 304 Freescale Semiconductor
Chapter 10 Stepper Stall Detector (SSDV1)
VDDM
VDDM
T1
T3
T5
T7
COSxP
COSxM
SINxP
SINxM
T2
T4
VSSM
T6
T8
VSSM
Figure 10-14. Current flow when STEP = 3, DCOIL = 1, ITG = 1
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 305
Chapter 10 Stepper Stall Detector (SSDV1)
10.4.3
Operation in Low Power Modes
The SSD block can be configured for lower MCU power consumption in three different ways. * Stop mode powers down the sigma-delta converter and halts clock to the modulus counter. Exit from Stop enables the sigma-delta converter and the clock to the modulus counter but due to the converter recovery time, the integration result should be ignored. * Wait mode with SSDWAI bit set powers down the sigma-delta converter and halts the clock to the modulus counter. Exit from Wait enables the sigma-delta converter and clock to the modulus counter but due to the converter recovery time, the integration result should be ignored. * Clearing SDCPU bit powers down the sigma-delta converter.
10.4.4
Stall Detection Flow
Figure 10-15 shows a flowchart and software setup for stall detection of a stepper motor. To control a second stepper motor, the SMS bit must be toggled during the SSD initialization.
MC9S12HZ256 Data Sheet, Rev. 2.05 306 Freescale Semiconductor
Chapter 10 Stepper Stall Detector (SSDV1)
Advance Pointer
Using Motor Control module, drive pointer to within 3 full steps of calibrated zero position.
Initialize SSD
1. Clear (or set) RCIR; clear (or set) POL; clear (or set) SMS; 2. Set MCZIE; clear MODMC; clear (or set) PRE; set MCEN. 3. Set RTZE; set SDCPU; write ACLKS (select sample frequency). 4. Store threshold value in RAM.
Start Blanking
1. Clear MCZIF. 2. Write MDCCNT with blanking time value. 3. Clear ITG; clear (or set) DCOIL; increment (or decrement) STEP for CCW (or CW) motion.
End of Blanking? Yes Start Integration
MDCCNT = 0x0000? or MCZIF = 1? No
1. Clear MCZIF. 2. Write MDCCNT with integration time value. 3. Set ITG; set DCOIL.
End of Integration? Yes
MDCCNT = 0x0000? or MCZIF = 1? No
No
Stall Detection? Yes Disable SSD
ITGACC < Threshold (RAM value)?
1. Clear MCZIF. 2. Clear MCEN. 3. Clear ITG. 4. Clear RTZE; clear SDCPU.
Figure 10-15. Return-to-Zero Flowchart
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 307
Chapter 10 Stepper Stall Detector (SSDV1)
MC9S12HZ256 Data Sheet, Rev. 2.05 308 Freescale Semiconductor
Chapter 11 Inter-Integrated Circuit (IICV2)
11.1 Introduction
The inter-IC bus (IIC) is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange between devices. Being a two-wire device, the IIC bus minimizes the need for large numbers of connections between devices, and eliminates the need for an address decoder. This bus is suitable for applications requiring occasional communications over a short distance between a number of devices. It also provides flexibility, allowing additional devices to be connected to the bus for further expansion and system development. The interface is designed to operate up to 100 kbps with maximum bus loading and timing. The device is capable of operating at higher baud rates, up to a maximum of clock/20, with reduced bus loading. The maximum communication length and the number of devices that can be connected are limited by a maximum bus capacitance of 400 pF.
11.1.1
Features
The IIC module has the following key features: * Compatible with I2C bus standard * Multi-master operation * Software programmable for one of 256 different serial clock frequencies * Software selectable acknowledge bit * Interrupt driven byte-by-byte data transfer * Arbitration lost interrupt with automatic mode switching from master to slave * Calling address identification interrupt * Start and stop signal generation/detection * Repeated start signal generation * Acknowledge bit generation/detection * Bus busy detection
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 309
Chapter 11 Inter-Integrated Circuit (IICV2)
11.1.2
Modes of Operation
The IIC functions the same in normal, special, and emulation modes. It has two low power modes: wait and stop modes.
11.1.3
Block Diagram
The block diagram of the IIC module is shown in Figure 11-1.
IIC Start Stop Arbitration Control
Registers
Interrupt Clock Control
bus_clock
In/Out Data Shift Register
SCL
SDA
Address Compare
Figure 11-1. IIC Block Diagram
MC9S12HZ256 Data Sheet, Rev. 2.05 310 Freescale Semiconductor
Chapter 11 Inter-Integrated Circuit (IICV2)
11.2
External Signal Description
The IIC module has two external pins.
11.2.1
IIC_SCL -- Serial Clock Line Pin
This is the bidirectional serial clock line (SCL) of the module, compatible to the IIC bus specification.
11.2.2
IIC_SDA -- Serial Data Line Pin
This is the bidirectional serial data line (SDA) of the module, compatible to the IIC bus specification.
11.3
Memory Map and Register Definition
This section provides a detailed description of all memory and registers for the IIC module.
11.3.1
Module Memory Map
The memory map for the IIC module is given below in Table 11-1. The address listed for each register is the address offset.The total address for each register is the sum of the base address for the IIC module and the address offset for each register.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 311
Chapter 11 Inter-Integrated Circuit (IICV2)
11.3.2
Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order.
Register Name IBAD R W IBFD R W IBCR R W IBSR R W IBDR R W D7 D6 D5 Bit 7 ADR7 6 ADR6 5 ADR5 4 ADR4 3 ADR3 2 ADR2 1 ADR1 Bit 0 0
IBC7
IBC6
IBC5
IBC4
IBC3
IBC2 0
IBC1 0
IBC0
IBEN TCF
IBIE IAAS
MS/SL IBB
Tx/Rx
TXAK 0
RSTA
SRW IBIF
IBSWAI RXAK
IBAL
D4
D3
D2
D1
D0
= Unimplemented or Reserved
Table 11-1. IIC Register Summary
11.3.2.1
IIC Address Register (IBAD)
7 6 5 4 3 2 1 0
R ADR7 W Reset 0 0 0 0 0 0 0 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1
0
0
= Unimplemented or Reserved
Figure 11-2. IIC Bus Address Register (IBAD)
Read and write anytime This register contains the address the IIC bus will respond to when addressed as a slave; note that it is not the address sent on the bus during the address transfer.
Table 11-2. IBAD Field Descriptions
Field 7:1 ADR[7:1] 0 Reserved Description Slave Address -- Bit 1 to bit 7 contain the specific slave address to be used by the IIC bus module.The default mode of IIC bus is slave mode for an address match on the bus. Reserved -- Bit 0 of the IBAD is reserved for future compatibility. This bit will always read 0.
MC9S12HZ256 Data Sheet, Rev. 2.05 312 Freescale Semiconductor
Chapter 11 Inter-Integrated Circuit (IICV2)
11.3.2.2
IIC Frequency Divider Register (IBFD)
7 6 5 4 3 2 1 0
R IBC7 W Reset 0 0 0 0 0 0 0 0 IBC6 IBC5 IBC4 IBC3 IBC2 IBC1 IBC0
= Unimplemented or Reserved
Figure 11-3. IIC Bus Frequency Divider Register (IBFD)
Read and write anytime
Table 11-3. IBFD Field Descriptions
Field 7:0 IBC[7:0] Description I Bus Clock Rate 7:0 -- This field is used to prescale the clock for bit rate selection. The bit clock generator is implemented as a prescale divider -- IBC7:6, prescaled shift register -- IBC5:3 select the prescaler divider and IBC2-0 select the shift register tap point. The IBC bits are decoded to give the tap and prescale values as shown in Table 11-4.
Table 11-4. I-Bus Tap and Prescale Values
IBC2-0 (bin) 000 001 010 011 100 101 110 111 IBC5-3 (bin) 000 001 010 011 100 101 110 111 scl2start (clocks) 2 2 2 6 14 30 62 126 SCL Tap (clocks) 5 6 7 8 9 10 12 15 scl2stop (clocks) 7 7 9 9 17 33 65 129 SDA Tap (clocks) 1 1 2 2 3 3 4 4 scl2tap (clocks) 4 4 6 6 14 30 62 126 tap2tap (clocks) 1 2 4 8 16 32 64 128
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 313
Chapter 11 Inter-Integrated Circuit (IICV2)
Table 11-5. Multiplier Factor
IBC7-6 00 01 10 11 MUL 01 02 04 RESERVED
The number of clocks from the falling edge of SCL to the first tap (Tap[1]) is defined by the values shown in the scl2tap column of Table 11-4, all subsequent tap points are separated by 2IBC5-3 as shown in the tap2tap column in Table 11-4. The SCL Tap is used to generated the SCL period and the SDA Tap is used to determine the delay from the falling edge of SCL to SDA changing, the SDA hold time. IBC7-6 defines the multiplier factor MUL. The values of MUL are shown in the Table 11-5.
SCL Divider
SCL
SDA
SDA Hold
SDA
SCL Hold(start)
SCL Hold(stop)
SCL
START condition
STOP condition
Figure 11-4. SCL Divider and SDA Hold
The equation used to generate the divider values from the IBFD bits is: SCL Divider = MUL x {2 x (scl2tap + [(SCL_Tap -1) x tap2tap] + 2)}
MC9S12HZ256 Data Sheet, Rev. 2.05 314 Freescale Semiconductor
Chapter 11 Inter-Integrated Circuit (IICV2)
The SDA hold delay is equal to the CPU clock period multiplied by the SDA Hold value shown in Table 11-6. The equation used to generate the SDA Hold value from the IBFD bits is: SDA Hold = MUL x {scl2tap + [(SDA_Tap - 1) x tap2tap] + 3} The equation for SCL Hold values to generate the start and stop conditions from the IBFD bits is: SCL Hold(start) = MUL x [scl2start + (SCL_Tap - 1) x tap2tap] SCL Hold(stop) = MUL x [scl2stop + (SCL_Tap - 1) x tap2tap]
Table 11-6. IIC Divider and Hold Values (Sheet 1 of 5)
IBC[7:0] (hex) SCL Divider (clocks) 20 22 24 26 28 30 34 40 28 32 36 40 44 48 56 68 48 56 64 72 80 88 104 128 80 96 112 128 144 160 192 240 160 192 224 SDA Hold (clocks) 7 7 8 8 9 9 10 10 7 7 9 9 11 11 13 13 9 9 13 13 17 17 21 21 9 9 17 17 25 25 33 33 17 17 33 SCL Hold (start) 6 7 8 9 10 11 13 16 10 12 14 16 18 20 24 30 18 22 26 30 34 38 46 58 38 46 54 62 70 78 94 118 78 94 110 SCL Hold (stop) 11 12 13 14 15 16 18 21 15 17 19 21 23 25 29 35 25 29 33 37 41 45 53 65 41 49 57 65 73 81 97 121 81 97 113
MUL=1
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 315
Chapter 11 Inter-Integrated Circuit (IICV2)
Table 11-6. IIC Divider and Hold Values (Sheet 2 of 5)
IBC[7:0] (hex) 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F SCL Divider (clocks) 256 288 320 384 480 320 384 448 512 576 640 768 960 640 768 896 1024 1152 1280 1536 1920 1280 1536 1792 2048 2304 2560 3072 3840 40 44 48 52 56 60 68 80 56 64 72 80 88 96 112 SDA Hold (clocks) 33 49 49 65 65 33 33 65 65 97 97 129 129 65 65 129 129 193 193 257 257 129 129 257 257 385 385 513 513 14 14 16 16 18 18 20 20 14 14 18 18 22 22 26 SCL Hold (start) 126 142 158 190 238 158 190 222 254 286 318 382 478 318 382 446 510 574 638 766 958 638 766 894 1022 1150 1278 1534 1918 12 14 16 18 20 22 26 32 20 24 28 32 36 40 48 SCL Hold (stop) 129 145 161 193 241 161 193 225 257 289 321 385 481 321 385 449 513 577 641 769 961 641 769 897 1025 1153 1281 1537 1921 22 24 26 28 30 32 36 42 30 34 38 42 46 50 58
MUL=2
40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E
MC9S12HZ256 Data Sheet, Rev. 2.05 316 Freescale Semiconductor
Chapter 11 Inter-Integrated Circuit (IICV2)
Table 11-6. IIC Divider and Hold Values (Sheet 3 of 5)
IBC[7:0] (hex) 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B SCL Divider (clocks) 136 96 112 128 144 160 176 208 256 160 192 224 256 288 320 384 480 320 384 448 512 576 640 768 960 640 768 896 1024 1152 1280 1536 1920 1280 1536 1792 2048 2304 2560 3072 3840 2560 3072 3584 4096 SDA Hold (clocks) 26 18 18 26 26 34 34 42 42 18 18 34 34 50 50 66 66 34 34 66 66 98 98 130 130 66 66 130 130 194 194 258 258 130 130 258 258 386 386 514 514 258 258 514 514 SCL Hold (start) 60 36 44 52 60 68 76 92 116 76 92 108 124 140 156 188 236 156 188 220 252 284 316 380 476 316 380 444 508 572 636 764 956 636 764 892 1020 1148 1276 1532 1916 1276 1532 1788 2044 SCL Hold (stop) 70 50 58 66 74 82 90 106 130 82 98 114 130 146 162 194 242 162 194 226 258 290 322 386 482 322 386 450 514 578 642 770 962 642 770 898 1026 1154 1282 1538 1922 1282 1538 1794 2050
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 317
Chapter 11 Inter-Integrated Circuit (IICV2)
Table 11-6. IIC Divider and Hold Values (Sheet 4 of 5)
IBC[7:0] (hex) 7C 7D 7E 7F SCL Divider (clocks) 4608 5120 6144 7680 80 88 96 104 112 120 136 160 112 128 144 160 176 192 224 272 192 224 256 288 320 352 416 512 320 384 448 512 576 640 768 960 640 768 896 1024 1152 1280 1536 1920 SDA Hold (clocks) 770 770 1026 1026 28 28 32 32 36 36 40 40 28 28 36 36 44 44 52 52 36 36 52 52 68 68 84 84 36 36 68 68 100 100 132 132 68 68 132 132 196 196 260 260 SCL Hold (start) 2300 2556 3068 3836 24 28 32 36 40 44 52 64 40 48 56 64 72 80 96 120 72 88 104 120 136 152 184 232 152 184 216 248 280 312 376 472 312 376 440 504 568 632 760 952 SCL Hold (stop) 2306 2562 3074 3842 44 48 52 56 60 64 72 84 60 68 76 84 92 100 116 140 100 116 132 148 164 180 212 260 164 196 228 260 292 324 388 484 324 388 452 516 580 644 772 964
MUL=4
80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7
MC9S12HZ256 Data Sheet, Rev. 2.05 318 Freescale Semiconductor
Chapter 11 Inter-Integrated Circuit (IICV2)
Table 11-6. IIC Divider and Hold Values (Sheet 5 of 5)
IBC[7:0] (hex) A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF SCL Divider (clocks) 1280 1536 1792 2048 2304 2560 3072 3840 2560 3072 3584 4096 4608 5120 6144 7680 5120 6144 7168 8192 9216 10240 12288 15360 SDA Hold (clocks) 132 132 260 260 388 388 516 516 260 260 516 516 772 772 1028 1028 516 516 1028 1028 1540 1540 2052 2052 SCL Hold (start) 632 760 888 1016 1144 1272 1528 1912 1272 1528 1784 2040 2296 2552 3064 3832 2552 3064 3576 4088 4600 5112 6136 7672 SCL Hold (stop) 644 772 900 1028 1156 1284 1540 1924 1284 1540 1796 2052 2308 2564 3076 3844 2564 3076 3588 4100 4612 5124 6148 7684
11.3.2.3
IIC Control Register (IBCR)
7 6 5 4 3 2 1 0
R IBEN W Reset 0 0 0 0 0 IBIE MS/SL Tx/Rx TXAK
0
0 IBSWAI
RSTA
0 0 0
= Unimplemented or Reserved
Figure 11-5. IIC Bus Control Register (IBCR)
Read and write anytime
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 319
Chapter 11 Inter-Integrated Circuit (IICV2)
Table 11-7. IBCR Field Descriptions
Field 7 IBEN Description I-Bus Enable -- This bit controls the software reset of the entire IIC bus module. 0 The module is reset and disabled. This is the power-on reset situation. When low the interface is held in reset but registers can be accessed 1 The IIC bus module is enabled.This bit must be set before any other IBCR bits have any effect If the IIC bus module is enabled in the middle of a byte transfer the interface behaves as follows: slave mode ignores the current transfer on the bus and starts operating whenever a subsequent start condition is detected. Master mode will not be aware that the bus is busy, hence if a start cycle is initiated then the current bus cycle may become corrupt. This would ultimately result in either the current bus master or the IIC bus module losing arbitration, after which bus operation would return to normal. I-Bus Interrupt Enable 0 Interrupts from the IIC bus module are disabled. Note that this does not clear any currently pending interrupt condition 1 Interrupts from the IIC bus module are enabled. An IIC bus interrupt occurs provided the IBIF bit in the status register is also set. Master/Slave Mode Select Bit -- Upon reset, this bit is cleared. When this bit is changed from 0 to 1, a START signal is generated on the bus, and the master mode is selected. When this bit is changed from 1 to 0, a STOP signal is generated and the operation mode changes from master to slave.A STOP signal should only be generated if the IBIF flag is set. MS/SL is cleared without generating a STOP signal when the master loses arbitration. 0 Slave Mode 1 Master Mode Transmit/Receive Mode Select Bit -- This bit selects the direction of master and slave transfers. When addressed as a slave this bit should be set by software according to the SRW bit in the status register. In master mode this bit should be set according to the type of transfer required. Therefore, for address cycles, this bit will always be high. 0 Receive 1 Transmit Transmit Acknowledge Enable -- This bit specifies the value driven onto SDA during data acknowledge cycles for both master and slave receivers. The IIC module will always acknowledge address matches, provided it is enabled, regardless of the value of TXAK. Note that values written to this bit are only used when the IIC bus is a receiver, not a transmitter. 0 An acknowledge signal will be sent out to the bus at the 9th clock bit after receiving one byte data 1 No acknowledge signal response is sent (i.e., acknowledge bit = 1) Repeat Start -- Writing a 1 to this bit will generate a repeated START condition on the bus, provided it is the current bus master. This bit will always be read as a low. Attempting a repeated start at the wrong time, if the bus is owned by another master, will result in loss of arbitration. 1 Generate repeat start cycle
6 IBIE
5 MS/SL
4 Tx/Rx
3 TXAK
2 RSTA
1 Reserved -- Bit 1 of the IBCR is reserved for future compatibility. This bit will always read 0. RESERVED 0 IBSWAI I Bus Interface Stop in Wait Mode 0 IIC bus module clock operates normally 1 Halt IIC bus module clock generation in wait mode
Wait mode is entered via execution of a CPU WAI instruction. In the event that the IBSWAI bit is set, all clocks internal to the IIC will be stopped and any transmission currently in progress will halt.If the CPU were woken up by a source other than the IIC module, then clocks would restart and the IIC would resume
MC9S12HZ256 Data Sheet, Rev. 2.05 320 Freescale Semiconductor
Chapter 11 Inter-Integrated Circuit (IICV2)
from where was during the previous transmission. It is not possible for the IIC to wake up the CPU when its internal clocks are stopped. If it were the case that the IBSWAI bit was cleared when the WAI instruction was executed, the IIC internal clocks and interface would remain alive, continuing the operation which was currently underway. It is also possible to configure the IIC such that it will wake up the CPU via an interrupt at the conclusion of the current operation. See the discussion on the IBIF and IBIE bits in the IBSR and IBCR, respectively.
11.3.2.4
IIC Status Register (IBSR)
7 6 5 4 3 2 1 0
R W Reset
TCF
IAAS
IBB IBAL
0
SRW IBIF
RXAK
1
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 11-6. IIC Bus Status Register (IBSR)
This status register is read-only with exception of bit 1 (IBIF) and bit 4 (IBAL), which are software clearable.
Table 11-8. IBSR Field Descriptions
Field 7 TCF Description Data Transferring Bit -- While one byte of data is being transferred, this bit is cleared. It is set by the falling edge of the 9th clock of a byte transfer. Note that this bit is only valid during or immediately following a transfer to the IIC module or from the IIC module. 0 Transfer in progress 1 Transfer complete Addressed as a Slave Bit -- When its own specific address (I-bus address register) is matched with the calling address, this bit is set.The CPU is interrupted provided the IBIE is set.Then the CPU needs to check the SRW bit and set its Tx/Rx mode accordingly.Writing to the I-bus control register clears this bit. 0 Not addressed 1 Addressed as a slave Bus Busy Bit 0 This bit indicates the status of the bus. When a START signal is detected, the IBB is set. If a STOP signal is detected, IBB is cleared and the bus enters idle state. 1 Bus is busy Arbitration Lost -- The arbitration lost bit (IBAL) is set by hardware when the arbitration procedure is lost. Arbitration is lost in the following circumstances: 1. SDA sampled low when the master drives a high during an address or data transmit cycle. 2. SDA sampled low when the master drives a high during the acknowledge bit of a data receive cycle. 3. A start cycle is attempted when the bus is busy. 4. A repeated start cycle is requested in slave mode. 5. A stop condition is detected when the master did not request it. This bit must be cleared by software, by writing a one to it. A write of 0 has no effect on this bit.
6 IAAS
5 IBB
4 IBAL
3 Reserved -- Bit 3 of IBSR is reserved for future use. A read operation on this bit will return 0. RESERVED
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 321
Chapter 11 Inter-Integrated Circuit (IICV2)
Table 11-8. IBSR Field Descriptions (continued)
Field 2 SRW Description Slave Read/Write -- When IAAS is set this bit indicates the value of the R/W command bit of the calling address sent from the master This bit is only valid when the I-bus is in slave mode, a complete address transfer has occurred with an address match and no other transfers have been initiated. Checking this bit, the CPU can select slave transmit/receive mode according to the command of the master. 0 Slave receive, master writing to slave 1 Slave transmit, master reading from slave I-Bus Interrupt -- The IBIF bit is set when one of the following conditions occurs: -- Arbitration lost (IBAL bit set) -- Byte transfer complete (TCF bit set) -- Addressed as slave (IAAS bit set) It will cause a processor interrupt request if the IBIE bit is set. This bit must be cleared by software, writing a one to it. A write of 0 has no effect on this bit. Received Acknowledge -- The value of SDA during the acknowledge bit of a bus cycle. If the received acknowledge bit (RXAK) is low, it indicates an acknowledge signal has been received after the completion of 8 bits data transmission on the bus. If RXAK is high, it means no acknowledge signal is detected at the 9th clock. 0 Acknowledge received 1 No acknowledge received
1 IBIF
0 RXAK
11.3.2.5
IIC Data I/O Register (IBDR)
7 6 5 4 3 2 1 0
R D7 W Reset 0 0 0 0 0 0 0 0 D6 D5 D4 D3 D2 D1 D0
Figure 11-7. IIC Bus Data I/O Register (IBDR)
In master transmit mode, when data is written to the IBDR a data transfer is initiated. The most significant bit is sent first. In master receive mode, reading this register initiates next byte data receiving. In slave mode, the same functions are available after an address match has occurred.Note that the Tx/Rx bit in the IBCR must correctly reflect the desired direction of transfer in master and slave modes for the transmission to begin. For instance, if the IIC is configured for master transmit but a master receive is desired, then reading the IBDR will not initiate the receive. Reading the IBDR will return the last byte received while the IIC is configured in either master receive or slave receive modes. The IBDR does not reflect every byte that is transmitted on the IIC bus, nor can software verify that a byte has been written to the IBDR correctly by reading it back. In master transmit mode, the first byte of data written to IBDR following assertion of MS/SL is used for the address transfer and should com.prise of the calling address (in position D7:D1) concatenated with the required R/W bit (in position D0).
MC9S12HZ256 Data Sheet, Rev. 2.05 322 Freescale Semiconductor
Chapter 11 Inter-Integrated Circuit (IICV2)
11.4
Functional Description
This section provides a complete functional description of the IIC.
11.4.1
I-Bus Protocol
The IIC bus system uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. All devices connected to it must have open drain or open collector outputs. Logic AND function is exercised on both lines with external pull-up resistors. The value of these resistors is system dependent. Normally, a standard communication is composed of four parts: START signal, slave address transmission, data transfer and STOP signal. They are described briefly in the following sections and illustrated in Figure 11-8.
MSB SCL 1 2 3 4 5 6 7 LSB 8 9 MSB 1 2 3 4 5 6 7 LSB 8 9
SDA
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
XXX
D7
D6
D5
D4
D3
D2
D1
D0
Start Signal
Calling Address
Read/ Write
Ack Bit
Data Byte
No Stop Ack Signal Bit LSB
MSB SCL 1 2 3 4 5 6 7
LSB 8 9
MSB 1 2 3 4 5 6 7
8
9
SDA
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
XX
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
Start Signal
Calling Address
Read/ Write
Ack Bit
Repeated Start Signal
New Calling Address
Read/ Write
No Stop Ack Signal Bit
Figure 11-8. IIC-Bus Transmission Signals
11.4.1.1
START Signal
When the bus is free, i.e. no master device is engaging the bus (both SCL and SDA lines are at logical high), a master may initiate communication by sending a START signal.As shown in Figure 11-8, a START signal is defined as a high-to-low transition of SDA while SCL is high. This signal denotes the beginning of a new data transfer (each data transfer may contain several bytes of data) and brings all slaves out of their idle states.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 323
Chapter 11 Inter-Integrated Circuit (IICV2)
SDA
SCL
START Condition
STOP Condition
Figure 11-9. Start and Stop Conditions
11.4.1.2
Slave Address Transmission
The first byte of data transfer immediately after the START signal is the slave address transmitted by the master. This is a seven-bit calling address followed by a R/W bit. The R/W bit tells the slave the desired direction of data transfer. 1 = Read transfer, the slave transmits data to the master. 0 = Write transfer, the master transmits data to the slave. Only the slave with a calling address that matches the one transmitted by the master will respond by sending back an acknowledge bit. This is done by pulling the SDA low at the 9th clock (see Figure 11-8). No two slaves in the system may have the same address. If the IIC bus is master, it must not transmit an address that is equal to its own slave address. The IIC bus cannot be master and slave at the same time.However, if arbitration is lost during an address cycle the IIC bus will revert to slave mode and operate correctly even if it is being addressed by another master.
11.4.1.3
Data Transfer
As soon as successful slave addressing is achieved, the data transfer can proceed byte-by-byte in a direction specified by the R/W bit sent by the calling master All transfers that come after an address cycle are referred to as data transfers, even if they carry sub-address information for the slave device. Each data byte is 8 bits long. Data may be changed only while SCL is low and must be held stable while SCL is high as shown in Figure 11-8. There is one clock pulse on SCL for each data bit, the MSB being transferred first. Each data byte has to be followed by an acknowledge bit, which is signalled from the receiving device by pulling the SDA low at the ninth clock. So one complete data byte transfer needs nine clock pulses. If the slave receiver does not acknowledge the master, the SDA line must be left high by the slave. The master can then generate a stop signal to abort the data transfer or a start signal (repeated start) to commence a new calling.
MC9S12HZ256 Data Sheet, Rev. 2.05 324 Freescale Semiconductor
Chapter 11 Inter-Integrated Circuit (IICV2)
If the master receiver does not acknowledge the slave transmitter after a byte transmission, it means 'end of data' to the slave, so the slave releases the SDA line for the master to generate STOP or START signal.
11.4.1.4
STOP Signal
The master can terminate the communication by generating a STOP signal to free the bus. However, the master may generate a START signal followed by a calling command without generating a STOP signal first. This is called repeated START. A STOP signal is defined as a low-to-high transition of SDA while SCL at logical 1 (see Figure 11-8). The master can generate a STOP even if the slave has generated an acknowledge at which point the slave must release the bus.
11.4.1.5
Repeated START Signal
As shown in Figure 11-8, a repeated START signal is a START signal generated without first generating a STOP signal to terminate the communication. This is used by the master to communicate with another slave or with the same slave in different mode (transmit/receive mode) without releasing the bus.
11.4.1.6
Arbitration Procedure
The Inter-IC bus is a true multi-master bus that allows more than one master to be connected on it. If two or more masters try to control the bus at the same time, a clock synchronization procedure determines the bus clock, for which the low period is equal to the longest clock low period and the high is equal to the shortest one among the masters. The relative priority of the contending masters is determined by a data arbitration procedure, a bus master loses arbitration if it transmits logic 1 while another master transmits logic 0. The losing masters immediately switch over to slave receive mode and stop driving SDA output. In this case the transition from master to slave mode does not generate a STOP condition. Meanwhile, a status bit is set by hardware to indicate loss of arbitration.
11.4.1.7
Clock Synchronization
Because wire-AND logic is performed on SCL line, a high-to-low transition on SCL line affects all the devices connected on the bus. The devices start counting their low period and as soon as a device's clock has gone low, it holds the SCL line low until the clock high state is reached.However, the change of low to high in this device clock may not change the state of the SCL line if another device clock is within its low period. Therefore, synchronized clock SCL is held low by the device with the longest low period. Devices with shorter low periods enter a high wait state during this time (see Figure 11-9). When all devices concerned have counted off their low period, the synchronized clock SCL line is released and pulled high. There is then no difference between the device clocks and the state of the SCL line and all the devices start counting their high periods.The first device to complete its high period pulls the SCL line low again.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 325
Chapter 11 Inter-Integrated Circuit (IICV2) Start Counting High Period
WAIT SCL1
SCL2
SCL
Internal Counter Reset
Figure 11-10. IIC-Bus Clock Synchronization
11.4.1.8
Handshaking
The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices may hold the SCL low after completion of one byte transfer (9 bits). In such case, it halts the bus clock and forces the master clock into wait states until the slave releases the SCL line.
11.4.1.9
Clock Stretching
The clock synchronization mechanism can be used by slaves to slow down the bit rate of a transfer. After the master has driven SCL low the slave can drive SCL low for the required period and then release it.If the slave SCL low period is greater than the master SCL low period then the resulting SCL bus signal low period is stretched.
11.4.2
Operation in Run Mode
This is the basic mode of operation.
11.4.3
Operation in Wait Mode
IIC operation in wait mode can be configured. Depending on the state of internal bits, the IIC can operate normally when the CPU is in wait mode or the IIC clock generation can be turned off and the IIC module enters a power conservation state during wait mode. In the later case, any transmission or reception in progress stops at wait mode entry.
11.4.4
Operation in Stop Mode
The IIC is inactive in stop mode for reduced power consumption. The STOP instruction does not affect IIC register states.
MC9S12HZ256 Data Sheet, Rev. 2.05 326 Freescale Semiconductor
Chapter 11 Inter-Integrated Circuit (IICV2)
11.5
Resets
The reset state of each individual bit is listed in Section 11.3, "Memory Map and Register Definition," which details the registers and their bit-fields.
11.6
Interrupts
Table 11-9. Interrupt Summary
Interrupt IIC Interrupt Offset -- Vector -- Priority -- Source Description
IIC uses only one interrupt vector.
IBAL, TCF, IAAS When either of IBAL, TCF or IAAS bits is set bits in IBSR may cause an interrupt based on arbitration register lost, transfer complete or address detect conditions
Internally there are three types of interrupts in IIC. The interrupt service routine can determine the interrupt type by reading the status register. IIC Interrupt can be generated on 1. Arbitration lost condition (IBAL bit set) 2. Byte transfer condition (TCF bit set) 3. Address detect condition (IAAS bit set) The IIC interrupt is enabled by the IBIE bit in the IIC control register. It must be cleared by writing 0 to the IBF bit in the interrupt service routine.
11.7
11.7.1
Initialization/Application Information
IIC Programming Examples
Initialization Sequence
11.7.1.1
Reset will put the IIC bus control register to its default status. Before the interface can be used to transfer serial data, an initialization procedure must be carried out, as follows: 1. Update the frequency divider register (IBFD) and select the required division ratio to obtain SCL frequency from system clock. 2. Update the IIC bus address register (IBAD) to define its slave address. 3. Set the IBEN bit of the IIC bus control register (IBCR) to enable the IIC interface system. 4. Modify the bits of the IIC bus control register (IBCR) to select master/slave mode, transmit/receive mode and interrupt enable or not.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 327
Chapter 11 Inter-Integrated Circuit (IICV2)
11.7.1.2
Generation of START
After completion of the initialization procedure, serial data can be transmitted by selecting the 'master transmitter' mode. If the device is connected to a multi-master bus system, the state of the IIC bus busy bit (IBB) must be tested to check whether the serial bus is free. If the bus is free (IBB=0), the start condition and the first byte (the slave address) can be sent. The data written to the data register comprises the slave calling address and the LSB set to indicate the direction of transfer required from the slave. The bus free time (i.e., the time between a STOP condition and the following START condition) is built into the hardware that generates the START cycle. Depending on the relative frequencies of the system clock and the SCL period it may be necessary to wait until the IIC is busy after writing the calling address to the IBDR before proceeding with the following instructions. This is illustrated in the following example. An example of a program which generates the START signal and transmits the first byte of data (slave address) is shown below:
CHFLAG TXSTART IBFREE BRSET BSET MOVB BRCLR IBSR,#$20,* IBCR,#$30 CALLING,IBDR IBSR,#$20,* ;WAIT FOR IBB FLAG TO CLEAR ;SET TRANSMIT AND MASTER MODE;i.e. GENERATE START CONDITION ;TRANSMIT THE CALLING ADDRESS, D0=R/W ;WAIT FOR IBB FLAG TO SET
11.7.1.3
Post-Transfer Software Response
Transmission or reception of a byte will set the data transferring bit (TCF) to 1, which indicates one byte communication is finished. The IIC bus interrupt bit (IBIF) is set also; an interrupt will be generated if the interrupt function is enabled during initialization by setting the IBIE bit. Software must clear the IBIF bit in the interrupt routine first. The TCF bit will be cleared by reading from the IIC bus data I/O register (IBDR) in receive mode or writing to IBDR in transmit mode. Software may service the IIC I/O in the main program by monitoring the IBIF bit if the interrupt function is disabled. Note that polling should monitor the IBIF bit rather than the TCF bit because their operation is different when arbitration is lost. Note that when an interrupt occurs at the end of the address cycle the master will always be in transmit mode, i.e. the address is transmitted. If master receive mode is required, indicated by R/W bit in IBDR, then the Tx/Rx bit should be toggled at this stage. During slave mode address cycles (IAAS=1), the SRW bit in the status register is read to determine the direction of the subsequent transfer and the Tx/Rx bit is programmed accordingly. For slave mode data cycles (IAAS=0) the SRW bit is not valid, the Tx/Rx bit in the control register should be read to determine the direction of the current transfer. The following is an example of a software response by a 'master transmitter' in the interrupt routine.
ISR BCLR BRCLR BRCLR BRSET MOVB IBSR,#$02 IBCR,#$20,SLAVE IBCR,#$10,RECEIVE IBSR,#$01,END DATABUF,IBDR ;CLEAR THE IBIF FLAG ;BRANCH IF IN SLAVE MODE ;BRANCH IF IN RECEIVE MODE ;IF NO ACK, END OF TRANSMISSION ;TRANSMIT NEXT BYTE OF DATA
TRANSMIT
MC9S12HZ256 Data Sheet, Rev. 2.05 328 Freescale Semiconductor
Chapter 11 Inter-Integrated Circuit (IICV2)
11.7.1.4
Generation of STOP
A data transfer ends with a STOP signal generated by the 'master' device. A master transmitter can simply generate a STOP signal after all the data has been transmitted. The following is an example showing how a stop condition is generated by a master transmitter.
MASTX TST BEQ BRSET MOVB DEC BRA BCLR RTI TXCNT END IBSR,#$01,END DATABUF,IBDR TXCNT EMASTX IBCR,#$20 ;GET VALUE FROM THE TRANSMITING COUNTER ;END IF NO MORE DATA ;END IF NO ACK ;TRANSMIT NEXT BYTE OF DATA ;DECREASE THE TXCNT ;EXIT ;GENERATE A STOP CONDITION ;RETURN FROM INTERRUPT
END EMASTX
If a master receiver wants to terminate a data transfer, it must inform the slave transmitter by not acknowledging the last byte of data which can be done by setting the transmit acknowledge bit (TXAK) before reading the 2nd last byte of data. Before reading the last byte of data, a STOP signal must be generated first. The following is an example showing how a STOP signal is generated by a master receiver.
MASR DEC BEQ MOVB DEC BNE BSET BRA BCLR MOVB RTI RXCNT ENMASR RXCNT,D1 D1 NXMAR IBCR,#$08 NXMAR IBCR,#$20 IBDR,RXBUF ;DECREASE THE RXCNT ;LAST BYTE TO BE READ ;CHECK SECOND LAST BYTE ;TO BE READ ;NOT LAST OR SECOND LAST ;SECOND LAST, DISABLE ACK ;TRANSMITTING ;LAST ONE, GENERATE `STOP' SIGNAL ;READ DATA AND STORE
LAMAR
ENMASR NXMAR
11.7.1.5
Generation of Repeated START
At the end of data transfer, if the master continues to want to communicate on the bus, it can generate another START signal followed by another slave address without first generating a STOP signal. A program example is as shown.
RESTART BSET MOVB IBCR,#$04 CALLING,IBDR ;ANOTHER START (RESTART) ;TRANSMIT THE CALLING ADDRESS;D0=R/W
11.7.1.6
Slave Mode
In the slave interrupt service routine, the module addressed as slave bit (IAAS) should be tested to check if a calling of its own address has just been received. If IAAS is set, software should set the transmit/receive mode select bit (Tx/Rx bit of IBCR) according to the R/W command bit (SRW). Writing to the IBCR clears the IAAS automatically. Note that the only time IAAS is read as set is from the interrupt at the end of the address cycle where an address match occurred, interrupts resulting from subsequent data transfers will have IAAS cleared. A data transfer may now be initiated by writing information to IBDR, for slave transmits, or dummy reading from IBDR, in slave receive mode. The slave will drive SCL low in-between byte transfers, SCL is released when the IBDR is accessed in the required mode.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 329
Chapter 11 Inter-Integrated Circuit (IICV2)
In slave transmitter routine, the received acknowledge bit (RXAK) must be tested before transmitting the next byte of data. Setting RXAK means an 'end of data' signal from the master receiver, after which it must be switched from transmitter mode to receiver mode by software. A dummy read then releases the SCL line so that the master can generate a STOP signal.
11.7.1.7
Arbitration Lost
If several masters try to engage the bus simultaneously, only one master wins and the others lose arbitration. The devices which lost arbitration are immediately switched to slave receive mode by the hardware. Their data output to the SDA line is stopped, but SCL continues to be generated until the end of the byte during which arbitration was lost. An interrupt occurs at the falling edge of the ninth clock of this transfer with IBAL=1 and MS/SL=0. If one master attempts to start transmission while the bus is being engaged by another master, the hardware will inhibit the transmission; switch the MS/SL bit from 1 to 0 without generating STOP condition; generate an interrupt to CPU and set the IBAL to indicate that the attempt to engage the bus is failed. When considering these cases, the slave service routine should test the IBAL first and the software should clear the IBAL bit if it is set.
MC9S12HZ256 Data Sheet, Rev. 2.05 330 Freescale Semiconductor
Chapter 11 Inter-Integrated Circuit (IICV2)
Clear IBIF
Y
Master Mode ?
N
TX
Tx/Rx ?
RX
Y
Arbitration Lost ? N
Last Byte Transmitted ? N
Y
Clear IBAL
RXAK=0 ? Y End Of Addr Cycle (Master Rx) ? N
N
Last Byte To Be Read ? N
Y
N
IAAS=1 ? Y
Y
IAAS=1 ? N
Address Transfer Y Y 2nd Last Byte To Be Read ? N Y (Read) SRW=1 ? N (Write) Y
Data Transfer TX/RX ? TX ACK From Receiver ? N Read Data From IBDR And Store RX
Write Next Byte To IBDR
Set TXAK =1
Generate Stop Signal
Set TX Mode
Write Data To IBDR
Tx Next Byte
Switch To Rx Mode
Set RX Mode
Switch To Rx Mode
Dummy Read From IBDR
Generate Stop Signal
Read Data From IBDR And Store
Dummy Read From IBDR
Dummy Read From IBDR
RTI
Figure 11-11. Flow-Chart of Typical IIC Interrupt Routine
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 331
Chapter 11 Inter-Integrated Circuit (IICV2)
MC9S12HZ256 Data Sheet, Rev. 2.05 332 Freescale Semiconductor
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
12.1 Introduction
Freescale's scalable controller area network (MSCAN) definition is based on the MSCAN12 definition, which is the specific implementation of the MSCAN concept targeted for the M68HC12 microcontroller family. The module is a communication controller implementing the CAN 2.0A/B protocol as defined in the Bosch specification dated September 1991. For users to fully understand the MSCAN specification, it is recommended that the Bosch specification be read first to familiarize the reader with the terms and concepts contained within this document. Though not exclusively intended for automotive applications, CAN protocol is designed to meet the specific requirements of a vehicle serial data bus: real-time processing, reliable operation in the EMI environment of a vehicle, cost-effectiveness, and required bandwidth. MSCAN uses an advanced buffer arrangement resulting in predictable real-time behavior and simplified application software.
12.1.1
Block Diagram MSCAN
Oscillator Clock Bus Clock
CANCLK
MUX
Presc.
Tq Clk
Receive/ Transmit Engine
RXCAN TXCAN
Transmit Interrupt Req. Receive Interrupt Req. Errors Interrupt Req. Wake-Up Interrupt Req.
Control and Status
Message Filtering and Buffering
Configuration Registers
Wake-Up
Low Pass Filter
Figure 12-1. MSCAN Block Diagram
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 333
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
12.1.2
Features
The basic features of the MSCAN are as follows: * Implementation of the CAN protocol -- Version 2.0A/B -- Standard and extended data frames -- Zero to eight bytes data length -- Programmable bit rate up to 1 Mbps1 -- Support for remote frames * Five receive buffers with FIFO storage scheme * Three transmit buffers with internal prioritization using a "local priority" concept * Flexible maskable identifier filter supports two full-size (32-bit) extended identifier filters, or four 16-bit filters, or eight 8-bit filters * Programmable wakeup functionality with integrated low-pass filter * Programmable loopback mode supports self-test operation * Programmable listen-only mode for monitoring of CAN bus * Separate signalling and interrupt capabilities for all CAN receiver and transmitter error states (warning, error passive, bus-off) * Programmable MSCAN clock source either bus clock or oscillator clock * Internal timer for time-stamping of received and transmitted messages * Three low-power modes: sleep, power down, and MSCAN enable * Global initialization of configuration registers
12.1.3
Modes of Operation
The following modes of operation are specific to the MSCAN. See Section 12.4, "Functional Description," for details. * Listen-Only Mode * MSCAN Sleep Mode * MSCAN Initialization Mode * MSCAN Power Down Mode
12.2
External Signal Description
The MSCAN uses two external pins:
12.2.1
RXCAN -- CAN Receiver Input Pin
RXCAN is the MSCAN receiver input pin.
1. Depending on the actual bit timing and the clock jitter of the PLL. MC9S12HZ256 Data Sheet, Rev. 2.05 334 Freescale Semiconductor
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
12.2.2
TXCAN -- CAN Transmitter Output Pin
TXCAN is the MSCAN transmitter output pin. The TXCAN output pin represents the logic level on the CAN bus: 0 = Dominant state 1 = Recessive state
12.2.3
CAN System
A typical CAN system with MSCAN is shown in Figure 12-2. Each CAN station is connected physically to the CAN bus lines through a transceiver device. The transceiver is capable of driving the large current needed for the CAN bus and has current protection against defective CAN or defective stations.
CAN node 1 MCU CAN Controller (MSCAN) CAN node 2 CAN node n
TXCAN
RXCAN
Transceiver CAN_H CAN_L CAN Bus
Figure 12-2. CAN System
12.3
Memory Map and Register Definition
This section provides a detailed description of all registers accessible in the MSCAN.
12.3.1
Module Memory Map
Table 12-1 gives an overview on all registers and their individual bits in the MSCAN memory map. The register address results from the addition of base address and address offset. The base address is determined at the MCU level and can be found in the Memory block description chapter. The address offset is defined at the module level. The MSCAN occupies 64 bytes in the memory space. The base address of the MSCAN module is determined at the MCU level when the MCU is defined. The register decode map is fixed and begins at the first address of the module address offset. Table 12-1 shows the individual registers associated with the MSCAN and their relative offset from the base address. The detailed register descriptions follow in the order they appear in the register map.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 335
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
Table 12-1. MSCAN Memory Map
Address Offset 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C 0x000D 0x000E 0x000F 0x0010 0x0011 0x0012 0x0013 0x0014 0x0015 0x0016 0x0017 0x0018 0x0019 0x001A 0x001B 0x001C 0x001D 0x001E 0x001F 0x0020 -0x002F 0x0030 -0x003F
1 2
Register MSCAN Control Register 0 (CANCTL0) MSCAN Control Register 1 (CANCTL1) MSCAN Bus Timing Register 0 (CANBTR0) MSCAN Bus Timing Register 1 (CANBTR1) MSCAN Receiver Flag Register (CANRFLG) MSCAN Receiver Interrupt Enable Register (CANRIER) MSCAN Transmitter Flag Register (CANTFLG) MSCAN Transmitter Interrupt Enable Register (CANTIER) MSCAN Transmitter Message Abort Request Register (CANTARQ) MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK) MSCAN Transmit Buffer Selection Register (CANTBSEL) MSCAN Identifier Acceptance Control Register (CANIDAC) RESERVED RESERVED MSCAN Receive Error Counter (CANRXERR) MSCAN Transmit Error Counter (CANTXERR) MSCAN Identifier Acceptance Register 0(CANIDAR0) MSCAN Identifier Acceptance Register 1(CANIDAR1) MSCAN Identifier Acceptance Register 2 (CANIDAR2) MSCAN Identifier Acceptance Register 3 (CANIDAR3) MSCAN Identifier Mask Register 0 (CANIDMR0) MSCAN Identifier Mask Register 1 (CANIDMR1) MSCAN Identifier Mask Register 2 (CANIDMR2) MSCAN Identifier Mask Register 3 (CANIDMR3) MSCAN Identifier Acceptance Register 4 (CANIDAR4) MSCAN Identifier Acceptance Register 5 (CANIDAR5) MSCAN Identifier Acceptance Register 6 (CANIDAR6) MSCAN Identifier Acceptance Register 7 (CANIDAR7) MSCAN Identifier Mask Register 4 (CANIDMR4) MSCAN Identifier Mask Register 5 (CANIDMR5) MSCAN Identifier Mask Register 6 (CANIDMR6) MSCAN Identifier Mask Register 7 (CANIDMR7) Foreground Receive Buffer (CANRXFG) Foreground Transmit Buffer (CANTXFG)
Access R/W1 R/W1 R/W R/W R/W1 R/W R/W1 R/W1 R/W1 R R/W1 R/W1
R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R2 R2/W
Refer to detailed register description for write access restrictions on per bit basis. Reserved bits and unused bits within the TX- and RX-buffers (CANTXFG, CANRXFG) will be read as "X", because of RAM-based implementation.
MC9S12HZ256 Data Sheet, Rev. 2.05 336 Freescale Semiconductor
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
Table 12-2. MSCAN Memory Map
Offset Address 0x0000 Register This section describes in detail all the registers and register bits in the MSCAN module. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order. All bits of all registers in this module are completely synchronous to internal clocks during a register read. MSCAN Control Register 1 (CANCTL1) MSCAN Bus Timing Register 0 (CANBTR0) MSCAN Bus Timing Register 1 (CANBTR1) MSCAN Receiver Flag Register (CANRFLG) MSCAN Receiver Interrupt Enable Register (CANRIER) MSCAN Transmitter Flag Register (CANTFLG) MSCAN Transmitter Interrupt Enable Register (CANTIER) MSCAN Transmitter Message Abort Request Register (CANTARQ) MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK) MSCAN Transmit Buffer Selection Register (CANTBSEL) MSCAN Identifier Acceptance Control Register (CANIDAC) RESERVED RESERVED MSCAN Receive Error Counter (CANRXERR) MSCAN Transmit Error Counter (CANTXERR) MSCAN Identifier Acceptance Register 0(CANIDAR0) MSCAN Identifier Acceptance Register 1(CANIDAR1) MSCAN Identifier Acceptance Register 2 (CANIDAR2) MSCAN Identifier Acceptance Register 3 (CANIDAR3) MSCAN Identifier Mask Register 0 (CANIDMR0) MSCAN Identifier Mask Register 1 (CANIDMR1) MSCAN Identifier Mask Register 2 (CANIDMR2) MSCAN Identifier Mask Register 3 (CANIDMR3) MSCAN Identifier Acceptance Register 4 (CANIDAR4) MSCAN Identifier Acceptance Register 5 (CANIDAR5) MSCAN Identifier Acceptance Register 6 (CANIDAR6) MSCAN Identifier Acceptance Register 7 (CANIDAR7) MSCAN Identifier Mask Register 4 (CANIDMR4) MSCAN Identifier Mask Register 5 (CANIDMR5) MSCAN Identifier Mask Register 6 (CANIDMR6) MSCAN Identifier Mask Register 7 (CANIDMR7) Foreground Receive Buffer (CANRXFG) Foreground Transmit Buffer (CANTXFG) R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R2 R2/W Access R/W1
0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C 0x000D 0x000E 0x000F 0x0010 0x0011 0x0012 0x0013 0x0014 0x0015 0x0016 0x0017 0x0018 0x0019 0x001A 0x001B 0x001C 0x001D 0x001E 0x001F 0x0020 -0x002F 0x0030 -0x003F
1
R/W1 R/W R/W R/W1 R/W R/W1 R/W1 R/W1 R R/W1 R/W1
Refer to detailed register description for write access restrictions on per bit basis.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 337
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2
Reserved bits and unused bits within the TX- and RX-buffers (CANTXFG, CANRXFG) will be read as "x", because of RAM-based implementation.
12.3.2
Register Descriptions
This section describes in detail all the registers and register bits in the MSCAN module. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order. All bits of all registers in this module are completely synchronous to internal clocks during a register read.
12.3.2.1
MSCAN Control Register 0 (CANCTL0)
The CANCTL0 register provides various control bits of the MSCAN module as described below.
7 6 5 4 3 2 1 0
R RXFRM W Reset: 0
RXACT CSWAI 0 = Unimplemented 0
SYNCH TIME 0 0 WUPE 0 SLPRQ 0 INITRQ 1
Figure 12-3. MSCAN Control Register 0 (CANCTL0)
NOTE The CANCTL0 register, except WUPE, INITRQ, and SLPRQ, is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is writable again as soon as the initialization mode is exited (INITRQ = 0 and INITAK = 0). Read: Anytime Write: Anytime when out of initialization mode; exceptions are read-only RXACT and SYNCH, RXFRM (which is set by the module only), and INITRQ (which is also writable in initialization mode).
Table 12-3. CANCTL0 Register Field Descriptions
Field 7 RXFRM1 Description Received Frame Flag -- This bit is read and clear only. It is set when a receiver has received a valid message correctly, independently of the filter configuration. After it is set, it remains set until cleared by software or reset. Clearing is done by writing a 1. Writing a 0 is ignored. This bit is not valid in loopback mode. 0 No valid message was received since last clearing this flag 1 A valid message was received since last clearing of this flag Receiver Active Status -- This read-only flag indicates the MSCAN is receiving a message. The flag is controlled by the receiver front end. This bit is not valid in loopback mode. 0 MSCAN is transmitting or idle2 1 MSCAN is receiving a message (including when arbitration is lost)2 CAN Stops in Wait Mode -- Enabling this bit allows for lower power consumption in wait mode by disabling all the clocks at the CPU bus interface to the MSCAN module. 0 The module is not affected during wait mode 1 The module ceases to be clocked during wait mode
6 RXACT
5 CSWAI3
MC9S12HZ256 Data Sheet, Rev. 2.05 338 Freescale Semiconductor
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
Table 12-3. CANCTL0 Register Field Descriptions (continued)
Field 4 SYNCH Description Synchronized Status -- This read-only flag indicates whether the MSCAN is synchronized to the CAN bus and able to participate in the communication process. It is set and cleared by the MSCAN. 0 MSCAN is not synchronized to the CAN bus 1 MSCAN is synchronized to the CAN bus Timer Enable -- This bit activates an internal 16-bit wide free running timer which is clocked by the bit clock rate. If the timer is enabled, a 16-bit time stamp will be assigned to each transmitted/received message within the active TX/RX buffer. As soon as a message is acknowledged on the CAN bus, the time stamp will be written to the highest bytes (0x000E, 0x000F) in the appropriate buffer (see Section 12.3.3, "Programmer's Model of Message Storage"). The internal timer is reset (all bits set to 0) when disabled. This bit is held low in initialization mode. 0 Disable internal MSCAN timer 1 Enable internal MSCAN timer Wake-Up Enable -- This configuration bit allows the MSCAN to restart from sleep mode when traffic on CAN is detected (see Section 12.4.6.4, "MSCAN Sleep Mode"). 0 Wake-up disabled -- The MSCAN ignores traffic on CAN 1 Wake-up enabled -- The MSCAN is able to restart Sleep Mode Request -- This bit requests the MSCAN to enter sleep mode, which is an internal power saving mode (see Section 12.4.6.4, "MSCAN Sleep Mode"). The sleep mode request is serviced when the CAN bus is idle, i.e., the module is not receiving a message and all transmit buffers are empty. The module indicates entry to sleep mode by setting SLPAK = 1 (see Section 12.3.2.2, "MSCAN Control Register 1 (CANCTL1)"). Sleep mode will be active until SLPRQ is cleared by the CPU or, depending on the setting of WUPE, the MSCAN detects activity on the CAN bus and clears SLPRQ itself. 0 Running -- The MSCAN functions normally 1 Sleep mode request -- The MSCAN enters sleep mode when CAN bus idle Initialization Mode Request -- When this bit is set by the CPU, the MSCAN skips to initialization mode (see Section 12.4.6.5, "MSCAN Initialization Mode"). Any ongoing transmission or reception is aborted and synchronization to the CAN bus is lost. The module indicates entry to initialization mode by setting INITAK = 1 (Section 12.3.2.2, "MSCAN Control Register 1 (CANCTL1)"). The following registers enter their hard reset state and restore their default values: CANCTL08, CANRFLG9, CANRIER10, CANTFLG, CANTIER, CANTARQ, CANTAAK, and CANTBSEL. The registers CANCTL1, CANBTR0, CANBTR1, CANIDAC, CANIDAR0-7, and CANIDMR0-7 can only be written by the CPU when the MSCAN is in initialization mode (INITRQ = 1 and INITAK = 1). The values of the error counters are not affected by initialization mode. When this bit is cleared by the CPU, the MSCAN restarts and then tries to synchronize to the CAN bus. If the MSCAN is not in bus-off state, it synchronizes after 11 consecutive recessive bits on the CAN bus; if the MSCAN is in bus-off state, it continues to wait for 128 occurrences of 11 consecutive recessive bits. Writing to other bits in CANCTL0, CANRFLG, CANRIER, CANTFLG, or CANTIER must be done only after initialization mode is exited, which is INITRQ = 0 and INITAK = 0. 0 Normal operation 1 MSCAN in initialization mode
3 TIME
2 WUPE4
1 SLPRQ5
0 INITRQ6,7
1 2 3
4 5 6 7
The MSCAN must be in normal mode for this bit to become set. See the Bosch CAN 2.0A/B specification for a detailed definition of transmitter and receiver states. In order to protect from accidentally violating the CAN protocol, the TXCAN pin is immediately forced to a recessive state when the CPU enters wait (CSWAI = 1) or stop mode (see Section 12.4.6.2, "Operation in Wait Mode" and Section 12.4.6.3, "Operation in Stop Mode"). The CPU has to make sure that the WUPE register and the WUPIE wake-up interrupt enable register (see Section 12.3.2.6, "MSCAN Receiver Interrupt Enable Register (CANRIER)) is enabled, if the recovery mechanism from stop or wait is required. The CPU cannot clear SLPRQ before the MSCAN has entered sleep mode (SLPRQ = 1 and SLPAK = 1). The CPU cannot clear INITRQ before the MSCAN has entered initialization mode (INITRQ = 1 and INITAK = 1). In order to protect from accidentally violating the CAN protocol, the TXCAN pin is immediately forced to a recessive state when the initialization mode is requested by the CPU. Thus, the recommended procedure is to bring the MSCAN into sleep mode (SLPRQ = 1 and SLPAK = 1) before requesting initialization mode.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 339
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8 9
Not including WUPE, INITRQ, and SLPRQ. TSTAT1 and TSTAT0 are not affected by initialization mode. 10 RSTAT1 and RSTAT0 are not affected by initialization mode.
12.3.2.2
MSCAN Control Register 1 (CANCTL1)
The CANCTL1 register provides various control bits and handshake status information of the MSCAN module as described below. Read: Anytime Write: Anytime when INITRQ = 1 and INITAK = 1, except CANE which is write once in normal and anytime in special system operation modes when the MSCAN is in initialization mode (INITRQ = 1 and INITAK = 1).
Table 12-4. CANCTL1 Register Field Descriptions
Field 7 CANE 6 CLKSRC MSCAN Enable 0 MSCAN module is disabled 1 MSCAN module is enabled MSCAN Clock Source -- This bit defines the clock source for the MSCAN module (only for systems with a clock generation module; Section 12.4.3.2, "Clock System," and Section Figure 12-40., "MSCAN Clocking Scheme,"). 0 MSCAN clock source is the oscillator clock 1 MSCAN clock source is the bus clock Loopback Self Test Mode -- When this bit is set, the MSCAN performs an internal loopback which can be used for self test operation. The bit stream output of the transmitter is fed back to the receiver internally. The RXCAN input pin is ignored and the TXCAN output goes to the recessive state (logic 1). The MSCAN behaves as it does normally when transmitting and treats its own transmitted message as a message received from a remote node. In this state, the MSCAN ignores the bit sent during the ACK slot in the CAN frame acknowledge field to ensure proper reception of its own message. Both transmit and receive interrupts are generated. 0 Loopback self test disabled 1 Loopback self test enabled Listen Only Mode -- This bit configures the MSCAN as a CAN bus monitor. When LISTEN is set, all valid CAN messages with matching ID are received, but no acknowledgement or error frames are sent out (see Section 12.4.5.4, "Listen-Only Mode"). In addition, the error counters are frozen. Listen only mode supports applications which require "hot plugging" or throughput analysis. The MSCAN is unable to transmit any messages when listen only mode is active. 0 Normal operation 1 Listen only mode activated Wake-Up Mode -- If WUPE in CANCTL0 is enabled, this bit defines whether the integrated low-pass filter is applied to protect the MSCAN from spurious wake-up (see Section 12.4.6.4, "MSCAN Sleep Mode"). 0 MSCAN wakes up the CPU after any recessive to dominant edge on the CAN bus 1 MSCAN wakes up the CPU only in case of a dominant pulse on the CAN bus that has a length of Twup Description
5 LOOPB
4 LISTEN
2 WUPM
MC9S12HZ256 Data Sheet, Rev. 2.05 340 Freescale Semiconductor
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
Table 12-4. CANCTL1 Register Field Descriptions (continued)
Field 1 SLPAK Description Sleep Mode Acknowledge -- This flag indicates whether the MSCAN module has entered sleep mode (see Section 12.4.6.4, "MSCAN Sleep Mode"). It is used as a handshake flag for the SLPRQ sleep mode request. Sleep mode is active when SLPRQ = 1 and SLPAK = 1. Depending on the setting of WUPE, the MSCAN will clear the flag if it detects activity on the CAN bus while in sleep mode. 0 Running -- The MSCAN operates normally 1 Sleep mode active -- The MSCAN has entered sleep mode Initialization Mode Acknowledge -- This flag indicates whether the MSCAN module is in initialization mode (see Section 12.4.6.5, "MSCAN Initialization Mode"). It is used as a handshake flag for the INITRQ initialization mode request. Initialization mode is active when INITRQ = 1 and INITAK = 1. The registers CANCTL1, CANBTR0, CANBTR1, CANIDAC, CANIDAR0-CANIDAR7, and CANIDMR0-CANIDMR7 can be written only by the CPU when the MSCAN is in initialization mode. 0 Running -- The MSCAN operates normally 1 Initialization mode active -- The MSCAN has entered initialization mode
0 INITAK
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 341
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
12.3.2.3
MSCAN Bus Timing Register 0 (CANBTR0)
The CANBTR0 register configures various CAN bus timing parameters of the MSCAN module.
7 6 5 4 3 2 1 0
R SJW1 W Reset: 0 0 0 0 0 0 0 0 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0
Figure 12-4. MSCAN Bus Timing Register 0 (CANBTR0)
Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
Table 12-5. CANBTR0 Register Field Descriptions
Field 7:6 SJW[1:0] 5:0 BRP[5:0] Description Synchronization Jump Width -- The synchronization jump width defines the maximum number of time quanta (Tq) clock cycles a bit can be shortened or lengthened to achieve resynchronization to data transitions on the CAN bus (see Table 12-6). Baud Rate Prescaler -- These bits determine the time quanta (Tq) clock which is used to build up the bit timing (see Table 12-7).
Table 12-6. Synchronization Jump Width
SJW1 0 0 1 1 SJW0 0 1 0 1 Synchronization Jump Width 1 Tq clock cycle 2 Tq clock cycles 3 Tq clock cycles 4 Tq clock cycles
Table 12-7. Baud Rate Prescaler
BRP5 0 0 0 0 : 1 BRP4 0 0 0 0 : 1 BRP3 0 0 0 0 : 1 BRP2 0 0 0 0 : 1 BRP1 0 0 1 1 : 1 BRP0 0 1 0 1 : 1 Prescaler value (P) 1 2 3 4 : 64
MC9S12HZ256 Data Sheet, Rev. 2.05 342 Freescale Semiconductor
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
12.3.2.4
MSCAN Bus Timing Register 1 (CANBTR1)
The CANBTR1 register configures various CAN bus timing parameters of the MSCAN module.
7 6 5 4 3 2 1 0
R SAMP W Reset: 0 0 0 0 0 0 0 0 TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10
Figure 12-5. MSCAN Bus Timing Register 1 (CANBTR1)
Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
Table 12-8. CANBTR1 Register Field Descriptions
Field 7 SAMP Description Sampling -- This bit determines the number of CAN bus samples taken per bit time. 0 One sample per bit. 1 Three samples per bit1. If SAMP = 0, the resulting bit value is equal to the value of the single bit positioned at the sample point. If SAMP = 1, the resulting bit value is determined by using majority rule on the three total samples. For higher bit rates, it is recommended that only one sample is taken per bit time (SAMP = 0).
6:4 Time Segment 2 -- Time segments within the bit time fix the number of clock cycles per bit time and the location TSEG2[2:0] of the sample point (see Figure 12-41). Time segment 2 (TSEG2) values are programmable as shown in Table 12-9. 3:0 Time Segment 1 -- Time segments within the bit time fix the number of clock cycles per bit time and the location TSEG1[3:0] of the sample point (see Figure 12-41). Time segment 1 (TSEG1) values are programmable as shown in Table 12-10.
1
In this case, PHASE_SEG1 must be at least 2 time quanta (Tq).
Table 12-9. Time Segment 2 Values
TSEG22 0 0 : 1 1
1
TSEG21 0 0 : 1 1
TSEG20 0 1 : 0 1
Time Segment 2 1 Tq clock cycle1 2 Tq clock cycles : 7 Tq clock cycles 8 Tq clock cycles
This setting is not valid. Please refer to Table 12-36 for valid settings.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 343
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
Table 12-10. Time Segment 1 Values
TSEG13 0 0 0 0 : 1 1
1
TSEG12 0 0 0 0 : 1 1
TSEG11 0 0 1 1 : 1 1
TSEG10 0 1 0 1 : 0 1
Time segment 1 1 Tq clock cycle1 2 Tq clock cycles1 3 Tq clock cycles1 4 Tq clock cycles : 15 Tq clock cycles 16 Tq clock cycles
This setting is not valid. Please refer to Table 12-36 for valid settings.
The bit time is determined by the oscillator frequency, the baud rate prescaler, and the number of time quanta (Tq) clock cycles per bit (as shown in Table 12-9 and Table 12-10).
Eqn. 12-1
( Prescaler value ) Bit Time = ----------------------------------------------------- * ( 1 + TimeSegment1 + TimeSegment2 ) f CANCLK
12.3.2.5
MSCAN Receiver Flag Register (CANRFLG)
A flag can be cleared only by software (writing a 1 to the corresponding bit position) when the condition which caused the setting is no longer valid. Every flag has an associated interrupt enable bit in the CANRIER register.
7 6 5 4 3 2 1 0
R WUPIF W Reset: 0 0 CSCIF
RSTAT1
RSTAT0
TSTAT1
TSTAT0 OVRIF RXF 0
0
0
0
0
0
= Unimplemented
Figure 12-6. MSCAN Receiver Flag Register (CANRFLG)
NOTE The CANRFLG register is held in the reset state1 when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is writable again as soon as the initialization mode is exited (INITRQ = 0 and INITAK = 0). Read: Anytime Write: Anytime when out of initialization mode, except RSTAT[1:0] and TSTAT[1:0] flags which are read-only; write of 1 clears flag; write of 0 is ignored.
1. The RSTAT[1:0], TSTAT[1:0] bits are not affected by initialization mode. MC9S12HZ256 Data Sheet, Rev. 2.05 344 Freescale Semiconductor
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
Table 12-11. CANRFLG Register Field Descriptions
Field 7 WUPIF Description Wake-Up Interrupt Flag -- If the MSCAN detects CAN bus activity while in sleep mode (see Section 12.4.6.4, "MSCAN Sleep Mode,") and WUPE = 1 in CANTCTL0 (see Section 12.3.2.1, "MSCAN Control Register 0 (CANCTL0)"), the module will set WUPIF. If not masked, a wake-up interrupt is pending while this flag is set. 0 No wake-up activity observed while in sleep mode 1 MSCAN detected activity on the CAN bus and requested wake-up CAN Status Change Interrupt Flag -- This flag is set when the MSCAN changes its current CAN bus status due to the actual value of the transmit error counter (TEC) and the receive error counter (REC). An additional 4-bit (RSTAT[1:0], TSTAT[1:0]) status register, which is split into separate sections for TEC/REC, informs the system on the actual CAN bus status (see Section 12.3.2.6, "MSCAN Receiver Interrupt Enable Register (CANRIER)"). If not masked, an error interrupt is pending while this flag is set. CSCIF provides a blocking interrupt. That guarantees that the receiver/transmitter status bits (RSTAT/TSTAT) are only updated when no CAN status change interrupt is pending. If the TECs/RECs change their current value after the CSCIF is asserted, which would cause an additional state change in the RSTAT/TSTAT bits, these bits keep their status until the current CSCIF interrupt is cleared again. 0 No change in CAN bus status occurred since last interrupt 1 MSCAN changed current CAN bus status
6 CSCIF
5:4 Receiver Status Bits -- The values of the error counters control the actual CAN bus status of the MSCAN. As RSTAT[1:0] soon as the status change interrupt flag (CSCIF) is set, these bits indicate the appropriate receiver related CAN bus status of the MSCAN. The coding for the bits RSTAT1, RSTAT0 is: 00 RxOK: 0 receive error counter 96 01 RxWRN: 96 < receive error counter 127 10 RxERR: 127 < receive error counter 11 Bus-off1: transmit error counter > 255 3:2 Transmitter Status Bits -- The values of the error counters control the actual CAN bus status of the MSCAN. TSTAT[1:0] As soon as the status change interrupt flag (CSCIF) is set, these bits indicate the appropriate transmitter related CAN bus status of the MSCAN. The coding for the bits TSTAT1, TSTAT0 is: 00 TxOK: 0 transmit error counter 96 01 TxWRN: 96 < transmit error counter 127 10 TxERR: 127 < transmit error counter 255 11 Bus-Off: transmit error counter > 255 1 OVRIF Overrun Interrupt Flag -- This flag is set when a data overrun condition occurs. If not masked, an error interrupt is pending while this flag is set. 0 No data overrun condition 1 A data overrun detected Receive Buffer Full Flag -- RXF is set by the MSCAN when a new message is shifted in the receiver FIFO. This flag indicates whether the shifted buffer is loaded with a correctly received message (matching identifier, matching cyclic redundancy code (CRC) and no other errors detected). After the CPU has read that message from the RxFG buffer in the receiver FIFO, the RXF flag must be cleared to release the buffer. A set RXF flag prohibits the shifting of the next FIFO entry into the foreground buffer (RxFG). If not masked, a receive interrupt is pending while this flag is set. 0 No new message available within the RxFG 1 The receiver FIFO is not empty. A new message is available in the RxFG
0 RXF2
1
Redundant Information for the most critical CAN bus status which is "bus-off". This only occurs if the Tx error counter exceeds a number of 255 errors. Bus-off affects the receiver state. As soon as the transmitter leaves its bus-off state the receiver state skips to RxOK too. Refer also to TSTAT[1:0] coding in this register. 2 To ensure data integrity, do not read the receive buffer registers while the RXF flag is cleared. For MCUs with dual CPUs, reading the receive buffer registers while the RXF flag is cleared may result in a CPU fault condition.
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12.3.2.6
MSCAN Receiver Interrupt Enable Register (CANRIER)
This register contains the interrupt enable bits for the interrupt flags described in the CANRFLG register.
7 6 5 4 3 2 1 0
R WUPIE W Reset: 0 0 0 0 0 0 0 0 CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE RXFIE
Figure 12-7. MSCAN Receiver Interrupt Enable Register (CANRIER)
NOTE The CANRIER register is held in the reset state when the initialization mode is active (INITRQ=1 and INITAK=1). This register is writable when not in initialization mode (INITRQ=0 and INITAK=0). The RSTATE[1:0], TSTATE[1:0] bits are not affected by initialization mode. Read: Anytime Write: Anytime when not in initialization mode
Table 12-12. CANRIER Register Field Descriptions
Field 7 WUPIE1 6 CSCIE Description Wake-Up Interrupt Enable 0 No interrupt request is generated from this event. 1 A wake-up event causes a Wake-Up interrupt request. CAN Status Change Interrupt Enable 0 No interrupt request is generated from this event. 1 A CAN Status Change event causes an error interrupt request.
5:4 Receiver Status Change Enable -- These RSTAT enable bits control the sensitivity level in which receiver state RSTATE[1:0] changes are causing CSCIF interrupts. Independent of the chosen sensitivity level the RSTAT flags continue to indicate the actual receiver state and are only updated if no CSCIF interrupt is pending. 00 Do not generate any CSCIF interrupt caused by receiver state changes. 01 Generate CSCIF interrupt only if the receiver enters or leaves "bus-off" state. Discard other receiver state changes for generating CSCIF interrupt. 10 Generate CSCIF interrupt only if the receiver enters or leaves "RxErr" or "bus-off"2 state. Discard other receiver state changes for generating CSCIF interrupt. 11 Generate CSCIF interrupt on all state changes. 3:2 Transmitter Status Change Enable -- These TSTAT enable bits control the sensitivity level in which transmitter TSTATE[1:0] state changes are causing CSCIF interrupts. Independent of the chosen sensitivity level, the TSTAT flags continue to indicate the actual transmitter state and are only updated if no CSCIF interrupt is pending. 00 Do not generate any CSCIF interrupt caused by transmitter state changes. 01 Generate CSCIF interrupt only if the transmitter enters or leaves "bus-off" state. Discard other transmitter state changes for generating CSCIF interrupt. 10 Generate CSCIF interrupt only if the transmitter enters or leaves "TxErr" or "bus-off" state. Discard other transmitter state changes for generating CSCIF interrupt. 11 Generate CSCIF interrupt on all state changes.
MC9S12HZ256 Data Sheet, Rev. 2.05 346 Freescale Semiconductor
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
Table 12-12. CANRIER Register Field Descriptions (continued)
Field 1 OVRIE 0 RXFIE
1
Description Overrun Interrupt Enable 0 No interrupt request is generated from this event. 1 An overrun event causes an error interrupt request. Receiver Full Interrupt Enable 0 No interrupt request is generated from this event. 1 A receive buffer full (successful message reception) event causes a receiver interrupt request.
WUPIE and WUPE (see Section 12.3.2.1, "MSCAN Control Register 0 (CANCTL0)") must both be enabled if the recovery mechanism from stop or wait is required. 2 Bus-off state is defined by the CAN standard (see Bosch CAN 2.0A/B protocol specification: for only transmitters. Because the only possible state change for the transmitter from bus-off to TxOK also forces the receiver to skip its current state to RxOK, the coding of the RXSTAT[1:0] flags define an additional bus-off state for the receiver (see Section 12.3.2.5, "MSCAN Receiver Flag Register (CANRFLG)").
12.3.2.7
MSCAN Transmitter Flag Register (CANTFLG)
The transmit buffer empty flags each have an associated interrupt enable bit in the CANTIER register.
7 6 5 4 3 2 1 0
R W Reset:
0
0
0
0
0 TXE2 TXE1 1 TXE0 1
0
0
0
0
0
1
= Unimplemented
Figure 12-8. MSCAN Transmitter Flag Register (CANTFLG)
NOTE The CANTFLG register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is writable when not in initialization mode (INITRQ = 0 and INITAK = 0). Read: Anytime Write: Anytime for TXEx flags when not in initialization mode; write of 1 clears flag, write of 0 is ignored
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 347
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
Table 12-13. CANTFLG Register Field Descriptions
Field 2:0 TXE[2:0] Description Transmitter Buffer Empty -- This flag indicates that the associated transmit message buffer is empty, and thus not scheduled for transmission. The CPU must clear the flag after a message is set up in the transmit buffer and is due for transmission. The MSCAN sets the flag after the message is sent successfully. The flag is also set by the MSCAN when the transmission request is successfully aborted due to a pending abort request (see Section 12.3.2.9, "MSCAN Transmitter Message Abort Request Register (CANTARQ)"). If not masked, a transmit interrupt is pending while this flag is set. Clearing a TXEx flag also clears the corresponding ABTAKx (see Section 12.3.2.10, "MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK)"). When a TXEx flag is set, the corresponding ABTRQx bit is cleared (see Section 12.3.2.9, "MSCAN Transmitter Message Abort Request Register (CANTARQ)"). When listen-mode is active (see Section 12.3.2.2, "MSCAN Control Register 1 (CANCTL1)") the TXEx flags cannot be cleared and no transmission is started. Read and write accesses to the transmit buffer will be blocked, if the corresponding TXEx bit is cleared (TXEx = 0) and the buffer is scheduled for transmission. 0 The associated message buffer is full (loaded with a message due for transmission) 1 The associated message buffer is empty (not scheduled)
12.3.2.8
MSCAN Transmitter Interrupt Enable Register (CANTIER)
This register contains the interrupt enable bits for the transmit buffer empty interrupt flags.
7 6 5 4 3 2 1 0
R W Reset:
0
0
0
0
0 TXEIE2 TXEIE1 0 TXEIE0 0
0
0
0
0
0
0
= Unimplemented
Figure 12-9. MSCAN Transmitter Interrupt Enable Register (CANTIER)
NOTE The CANTIER register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is writable when not in initialization mode (INITRQ = 0 and INITAK = 0). Read: Anytime Write: Anytime when not in initialization mode
Table 12-14. CANTIER Register Field Descriptions
Field 2:0 TXEIE[2:0] Description Transmitter Empty Interrupt Enable 0 No interrupt request is generated from this event. 1 A transmitter empty (transmit buffer available for transmission) event causes a transmitter empty interrupt request.
MC9S12HZ256 Data Sheet, Rev. 2.05 348 Freescale Semiconductor
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
12.3.2.9
MSCAN Transmitter Message Abort Request Register (CANTARQ)
The CANTARQ register allows abort request of queued messages as described below.
7 6 5 4 3 2 1 0
R W Reset:
0
0
0
0
0 ABTRQ2 ABTRQ1 0 ABTRQ0 0
0
0
0
0
0
0
= Unimplemented
Figure 12-10. MSCAN Transmitter Message Abort Request Register (CANTARQ)
NOTE The CANTARQ register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is writable when not in initialization mode (INITRQ = 0 and INITAK = 0). Read: Anytime Write: Anytime when not in initialization mode
Table 12-15. CANTARQ Register Field Descriptions
Field Description
2:0 Abort Request -- The CPU sets the ABTRQx bit to request that a scheduled message buffer (TXEx = 0) be ABTRQ[2:0] aborted. The MSCAN grants the request if the message has not already started transmission, or if the transmission is not successful (lost arbitration or error). When a message is aborted, the associated TXE (see Section 12.3.2.7, "MSCAN Transmitter Flag Register (CANTFLG)") and abort acknowledge flags (ABTAK, see Section 12.3.2.10, "MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK)") are set and a transmit interrupt occurs if enabled. The CPU cannot reset ABTRQx. ABTRQx is reset whenever the associated TXE flag is set. 0 No abort request 1 Abort request pending
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12.3.2.10 MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK)
The CANTAAK register indicates the successful abort of a queued message, if requested by the appropriate bits in the CANTARQ register.
7 6 5 4 3 2 1 0
R W Reset:
0
0
0
0
0
ABTAK2
ABTAK1
ABTAK0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 12-11. MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK)
NOTE The CANTAAK register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1). Read: Anytime Write: Unimplemented for ABTAKx flags
Table 12-16. CANTAAK Register Field Descriptions
Field Description
2:0 Abort Acknowledge -- This flag acknowledges that a message was aborted due to a pending abort request ABTAK[2:0] from the CPU. After a particular message buffer is flagged empty, this flag can be used by the application software to identify whether the message was aborted successfully or was sent anyway. The ABTAKx flag is cleared whenever the corresponding TXE flag is cleared. 0 The message was not aborted. 1 The message was aborted.
MC9S12HZ256 Data Sheet, Rev. 2.05 350 Freescale Semiconductor
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
12.3.2.11 MSCAN Transmit Buffer Selection Register (CANTBSEL)
The CANTBSEL register allows the selection of the actual transmit message buffer, which then will be accessible in the CANTXFG register space.
7 6 5 4 3 2 1 0
R W Reset:
0
0
0
0
0 TX2 TX1 0 TX0 0
0
0
0
0
0
0
= Unimplemented
Figure 12-12. MSCAN Transmit Buffer Selection Register (CANTBSEL)
NOTE The CANTBSEL register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK=1). This register is writable when not in initialization mode (INITRQ = 0 and INITAK = 0). Read: Find the lowest ordered bit set to 1, all other bits will be read as 0 Write: Anytime when not in initialization mode
Table 12-17. CANTBSEL Register Field Descriptions
Field 2:0 TX[2:0] Description Transmit Buffer Select -- The lowest numbered bit places the respective transmit buffer in the CANTXFG register space (e.g., TX1 = 1 and TX0 = 1 selects transmit buffer TX0; TX1 = 1 and TX0 = 0 selects transmit buffer TX1). Read and write accesses to the selected transmit buffer will be blocked, if the corresponding TXEx bit is cleared and the buffer is scheduled for transmission (see Section 12.3.2.7, "MSCAN Transmitter Flag Register (CANTFLG)"). 0 The associated message buffer is deselected 1 The associated message buffer is selected, if lowest numbered bit
The following gives a short programming example of the usage of the CANTBSEL register: To get the next available transmit buffer, application software must read the CANTFLG register and write this value back into the CANTBSEL register. In this example Tx buffers TX1 and TX2 are available. The value read from CANTFLG is therefore 0b0000_0110. When writing this value back to CANTBSEL, the Tx buffer TX1 is selected in the CANTXFG because the lowest numbered bit set to 1 is at bit position 1. Reading back this value out of CANTBSEL results in 0b0000_0010, because only the lowest numbered bit position set to 1 is presented. This mechanism eases the application software the selection of the next available Tx buffer. * * * LDD CANTFLG; value read is 0b0000_0110 STD CANTBSEL; value written is 0b0000_0110 LDD CANTBSEL; value read is 0b0000_0010
If all transmit message buffers are deselected, no accesses are allowed to the CANTXFG registers.
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12.3.2.12 MSCAN Identifier Acceptance Control Register (CANIDAC)
The CANIDAC register is used for identifier acceptance control as described below.
7 6 5 4 3 2 1 0
R W Reset:
0
0 IDAM1 IDAM0 0
0
IDHIT2
IDHIT1
IDHIT0
0
0
0
0
0
0
0
= Unimplemented
Figure 12-13. MSCAN Identifier Acceptance Control Register (CANIDAC)
Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1), except bits IDHITx, which are read-only
Table 12-18. CANIDAC Register Field Descriptions
Field 5:4 IDAM[1:0] 2:0 IDHIT[2:0] Description Identifier Acceptance Mode -- The CPU sets these flags to define the identifier acceptance filter organization (see Section 12.4.3, "Identifier Acceptance Filter"). Table 12-19 summarizes the different settings. In filter closed mode, no message is accepted such that the foreground buffer is never reloaded. Identifier Acceptance Hit Indicator -- The MSCAN sets these flags to indicate an identifier acceptance hit (see Section 12.4.3, "Identifier Acceptance Filter"). Table 12-20 summarizes the different settings.
Table 12-19. Identifier Acceptance Mode Settings
IDAM1 0 0 1 1 IDAM0 0 1 0 1 Identifier Acceptance Mode Two 32-bit acceptance filters Four 16-bit acceptance filters Eight 8-bit acceptance filters Filter closed
Table 12-20. Identifier Acceptance Hit Indication
IDHIT2 0 0 0 0 1 1 1 1 IDHIT1 0 0 1 1 0 0 1 1 IDHIT0 0 1 0 1 0 1 0 1 Identifier Acceptance Hit Filter 0 hit Filter 1 hit Filter 2 hit Filter 3 hit Filter 4 hit Filter 5 hit Filter 6 hit Filter 7 hit
The IDHITx indicators are always related to the message in the foreground buffer (RxFG). When a message gets shifted into the foreground buffer of the receiver FIFO the indicators are updated as well.
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12.3.2.13 MSCAN Reserved Register
reserved for factory testing of the MSCAN module and is not available in normal system operation modes.
7 6 5 4 3 2 1 0
R W Reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 12-14. MSCAN Reserved Register
Read: Always read 0x0000 in normal system operation modes Write: Unimplemented in normal system operation modes NOTE Writing to this register when in special modes can alter the MSCAN functionality.
12.3.2.14 MSCAN Receive Error Counter (CANRXERR)
This register reflects the status of the MSCAN receive error counter.
7 6 5 4 3 2 1 0
R W Reset:
RXERR7
RXERR6
RXERR5
RXERR4
RXERR3
RXERR2
RXERR1
RXERR0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 12-15. MSCAN Receive Error Counter (CANRXERR)
Read: Only when in sleep mode (SLPRQ = 1 and SLPAK = 1) or initialization mode (INITRQ = 1 and INITAK = 1) Write: Unimplemented NOTE Reading this register when in any other mode other than sleep or initialization mode may return an incorrect value. For MCUs with dual CPUs, this may result in a CPU fault condition. Writing to this register when in special modes can alter the MSCAN functionality.
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12.3.2.15 MSCAN Transmit Error Counter (CANTXERR)
This register reflects the status of the MSCAN transmit error counter.
7 6 5 4 3 2 1 0
R W Reset:
TXERR7
TXERR6
TXERR5
TXERR4
TXERR3
TXERR2
TXERR1
TXERR0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 12-16. MSCAN Transmit Error Counter (CANTXERR)
Read: Only when in sleep mode (SLPRQ = 1 and SLPAK = 1) or initialization mode (INITRQ = 1 and INITAK = 1) Write: Unimplemented NOTE Reading this register when in any other mode other than sleep or initialization mode, may return an incorrect value. For MCUs with dual CPUs, this may result in a CPU fault condition. Writing to this register when in special modes can alter the MSCAN functionality.
MC9S12HZ256 Data Sheet, Rev. 2.05 354 Freescale Semiconductor
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12.3.2.16 MSCAN Identifier Acceptance Registers (CANIDAR0-7)
On reception, each message is written into the background receive buffer. The CPU is only signalled to read the message if it passes the criteria in the identifier acceptance and identifier mask registers (accepted); otherwise, the message is overwritten by the next message (dropped). The acceptance registers of the MSCAN are applied on the IDR0-IDR3 registers (see Section 12.3.3.1, "Identifier Registers (IDR0-IDR3)") of incoming messages in a bit by bit manner (see Section 12.4.3, "Identifier Acceptance Filter"). For extended identifiers, all four acceptance and mask registers are applied. For standard identifiers, only the first two (CANIDAR0/1, CANIDMR0/1) are applied.
Module Base + 0x0010 (CANIDAR0) 0x0011 (CANIDAR1) 0x0012 (CANIDAR2) 0x0013 (CANIDAR3)
7 6 5 4 3 2 1 0
R W Reset
AC7 0
7
AC6 0
6
AC5 0
5
AC4 0
4
AC3 0
3
AC2 0
2
AC1 0
1
AC0 0
0
R W Reset
AC7 0
7
AC6 0
6
AC5 0
5
AC4 0
4
AC3 0
3
AC2 0
2
AC1 0
1
AC0 0
0
R W Reset
AC7 0
7
AC6 0
6
AC5 0
5
AC4 0
4
AC3 0
3
AC2 0
2
AC1 0
1
AC0 0
0
R W Reset
AC7 0
AC6 0
AC5 0
AC4 0
AC3 0
AC2 0
AC1 0
AC0 0
Figure 12-17. MSCAN Identifier Acceptance Registers (First Bank) -- CANIDAR0-CANIDAR3
Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
Table 12-21. CANIDAR0-CANIDAR3 Register Field Descriptions
Field 7:0 AC[7:0] Description Acceptance Code Bits -- AC[7:0] comprise a user-defined sequence of bits with which the corresponding bits of the related identifier register (IDRn) of the receive message buffer are compared. The result of this comparison is then masked with the corresponding identifier mask register.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 355
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Module Base + 0x0018 (CANIDAR4) 0x0019 (CANIDAR5) 0x001A (CANIDAR6) 0x001B (CANIDAR7)
7 6 5 4 3 2 1 0
R W Reset
AC7 0
7
AC6 0
6
AC5 0
5
AC4 0
4
AC3 0
3
AC2 0
2
AC1 0
1
AC0 0
0
R W Reset
AC7 0
7
AC6 0
6
AC5 0
5
AC4 0
4
AC3 0
3
AC2 0
2
AC1 0
1
AC0 0
0
R W Reset
AC7 0
7
AC6 0
6
AC5 0
5
AC4 0
4
AC3 0
3
AC2 0
2
AC1 0
1
AC0 0
0
R W Reset
AC7 0
AC6 0
AC5 0
AC4 0
AC3 0
AC2 0
AC1 0
AC0 0
Figure 12-18. MSCAN Identifier Acceptance Registers (Second Bank) -- CANIDAR4-CANIDAR7
Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
Table 12-22. CANIDAR4-CANIDAR7 Register Field Descriptions
Field 7:0 AC[7:0] Description Acceptance Code Bits -- AC[7:0] comprise a user-defined sequence of bits with which the corresponding bits of the related identifier register (IDRn) of the receive message buffer are compared. The result of this comparison is then masked with the corresponding identifier mask register.
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Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
12.3.2.17 MSCAN Identifier Mask Registers (CANIDMR0-CANIDMR7)
The identifier mask register specifies which of the corresponding bits in the identifier acceptance register are relevant for acceptance filtering. To receive standard identifiers in 32 bit filter mode, it is required to program the last three bits (AM[2:0]) in the mask registers CANIDMR1 and CANIDMR5 to "don't care." To receive standard identifiers in 16 bit filter mode, it is required to program the last three bits (AM[2:0]) in the mask registers CANIDMR1, CANIDMR3, CANIDMR5, and CANIDMR7 to "don't care."
Module Base + 0x0014 (CANIDMR0) 0x0015 (CANIDMR1) 0x0016 (CANIDMR2) 0x0017 (CANIDMR3)
7 6 5 4 3 2 1 0
R W Reset
AM7 0
7
AM6 0
6
AM5 0
5
AM4 0
4
AM3 0
3
AM2 0
2
AM1 0
1
AM0 0
0
R W Reset
AM7 0
7
AM6 0
6
AM5 0
5
AM4 0
4
AM3 0
3
AM2 0
2
AM1 0
1
AM0 0
0
R W Reset
AM7 0
7
AM6 0
6
AM5 0
5
AM4 0
4
AM3 0
3
AM2 0
2
AM1 0
1
AM0 0
0
R W Reset
AM7 0
AM6 0
AM5 0
AM4 0
AM3 0
AM2 0
AM1 0
AM0 0
Figure 12-19. MSCAN Identifier Mask Registers (First Bank) -- CANIDMR0-CANIDMR3
Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
Table 12-23. CANIDMR0-CANIDMR3 Register Field Descriptions
Field 7:0 AM[7:0] Description Acceptance Mask Bits -- If a particular bit in this register is cleared, this indicates that the corresponding bit in the identifier acceptance register must be the same as its identifier bit before a match is detected. The message is accepted if all such bits match. If a bit is set, it indicates that the state of the corresponding bit in the identifier acceptance register does not affect whether or not the message is accepted. 0 Match corresponding acceptance code register and identifier bits 1 Ignore corresponding acceptance code register bit
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Module Base + 0x001C (CANIDMR4) 0x001D (CANIDMR5) 0x001E (CANIDMR6) 0x001F (CANIDMR7)
7 6 5 4 3 2 1 0
R W Reset
AM7 0
7
AM6 0
6
AM5 0
5
AM4 0
4
AM3 0
3
AM2 0
2
AM1 0
1
AM0 0
0
R W Reset
AM7 0
7
AM6 0
6
AM5 0
5
AM4 0
4
AM3 0
3
AM2 0
2
AM1 0
1
AM0 0
0
R W Reset
AM7 0
7
AM6 0
6
AM5 0
5
AM4 0
4
AM3 0
3
AM2 0
2
AM1 0
1
AM0 0
0
R W Reset
AM7 0
AM6 0
AM5 0
AM4 0
AM3 0
AM2 0
AM1 0
AM0 0
Figure 12-20. MSCAN Identifier Mask Registers (Second Bank) -- CANIDMR4-CANIDMR7
Read: Anytime Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
Table 12-24. CANIDMR4-CANIDMR7 Register Field Descriptions
Field 7:0 AM[7:0] Description Acceptance Mask Bits -- If a particular bit in this register is cleared, this indicates that the corresponding bit in the identifier acceptance register must be the same as its identifier bit before a match is detected. The message is accepted if all such bits match. If a bit is set, it indicates that the state of the corresponding bit in the identifier acceptance register does not affect whether or not the message is accepted. 0 Match corresponding acceptance code register and identifier bits 1 Ignore corresponding acceptance code register bit
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Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
12.3.3
Programmer's Model of Message Storage
The following section details the organization of the receive and transmit message buffers and the associated control registers. To simplify the programmer interface, the receive and transmit message buffers have the same outline. Each message buffer allocates 16 bytes in the memory map containing a 13 byte data structure. An additional transmit buffer priority register (TBPR) is defined for the transmit buffers. Within the last two bytes of this memory map, the MSCAN stores a special 16-bit time stamp, which is sampled from an internal timer after successful transmission or reception of a message. This feature is only available for transmit and receiver buffers, if the TIME bit is set (see Section 12.3.2.1, "MSCAN Control Register 0 (CANCTL0)"). The time stamp register is written by the MSCAN. The CPU can only read these registers.
Table 12-25. Message Buffer Organization
Offset Address 0x00X0 0x00X1 0x00X2 0x00X3 0x00X4 0x00X5 0x00X6 0x00X7 0x00X8 0x00X9 0x00XA 0x00XB 0x00XC 0x00XD 0x00XE 0x00XF
1 2
Register Identifier Register 0 Identifier Register 1 Identifier Register 2 Identifier Register 3 Data Segment Register 0 Data Segment Register 1 Data Segment Register 2 Data Segment Register 3 Data Segment Register 4 Data Segment Register 5 Data Segment Register 6 Data Segment Register 7 Data Length Register Transmit Buffer Priority Register1 Time Stamp Register (High Byte)2 Time Stamp Register (Low Byte)3
Access
Not applicable for receive buffers Read-only for CPU 3 Read-only for CPU
Figure 12-21 shows the common 13-byte data structure of receive and transmit buffers for extended identifiers. The mapping of standard identifiers into the IDR registers is shown in Figure 12-22. All bits of the receive and transmit buffers are `x' out of reset because of RAM-based implementation1. All reserved or unused bits of the receive and transmit buffers always read `x'.
1. Exception: The transmit priority registers are 0 out of reset. MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 359
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Register Name IDR0 R W R W R IDR2 W R IDR3 W R DSR0 W R DSR1 W R DSR2 W R DSR3 W R DSR4 W R DSR5 W R DSR6 W R DSR7 W R DLR W
Bit 7 ID28
6 ID27
5 ID26
4 ID25
3 ID24
2 ID23
1 ID22
Bit0 ID21
IDR1
ID20
ID19
ID18
SRR (=1)
IDE (=1)
ID17
ID16
ID15
ID14
ID13
ID12
ID11
ID10
ID9
ID8
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
RTR
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DLC3
DLC2
DLC1
DLC0
= Unused, always read `x'
Figure 12-21. Receive/Transmit Message Buffer -- Extended Identifier Mapping
Read: For transmit buffers, anytime when TXEx flag is set (see Section 12.3.2.7, "MSCAN Transmitter Flag Register (CANTFLG)") and the corresponding transmit buffer is selected in CANTBSEL (see Section 12.3.2.11, "MSCAN Transmit Buffer Selection Register (CANTBSEL)"). For receive buffers, only when RXF flag is set (see Section 12.3.2.5, "MSCAN Receiver Flag Register (CANRFLG)").
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Write: For transmit buffers, anytime when TXEx flag is set (see Section 12.3.2.7, "MSCAN Transmitter Flag Register (CANTFLG)") and the corresponding transmit buffer is selected in CANTBSEL (see Section 12.3.2.11, "MSCAN Transmit Buffer Selection Register (CANTBSEL)"). Unimplemented for receive buffers. Reset: Undefined (0x00XX) because of RAM-based implementation
Register Name IDR0 R W R W R W R W Bit 7 ID10 6 ID9 5 ID8 4 ID7 3 ID6 2 ID5 1 ID4 Bit 0 ID3
IDR1
ID2
ID1
ID0
RTR
IDE (=0)
IDR2
IDR3
= Unused, always read `x'
Figure 12-22. Receive/Transmit Message Buffer -- Standard Identifier Mapping
12.3.3.1
Identifier Registers (IDR0-IDR3)
The identifier registers for an extended format identifier consist of a total of 32 bits; ID[28:0], SRR, IDE, and RTR bits. The identifier registers for a standard format identifier consist of a total of 13 bits; ID[10:0], RTR, and IDE bits. 12.3.3.1.1 IDR0-IDR3 for Extended Identifier Mapping
7 6 5 4 3 2 1 0
R ID28 W Reset: x x x x x x x x ID27 ID26 ID25 ID24 ID23 ID22 ID21
Figure 12-23. Identifier Register 0 (IDR0) -- Extended Identifier Mapping Table 12-26. IDR0 Register Field Descriptions -- Extended
Field 7:0 ID[28:21] Description Extended Format Identifier -- The identifiers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number.
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7
6
5
4
3
2
1
0
R ID20 W Reset: x x x x x x x x ID19 ID18 SRR (=1) IDE (=1) ID17 ID16 ID15
Figure 12-24. Identifier Register 1 (IDR1) -- Extended Identifier Mapping Table 12-27. IDR1 Register Field Descriptions -- Extended
Field 7:5 ID[20:18] 4 SRR 3 IDE Description Extended Format Identifier -- The identifiers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number. Substitute Remote Request -- This fixed recessive bit is used only in extended format. It must be set to 1 by the user for transmission buffers and is stored as received on the CAN bus for receive buffers. ID Extended -- This flag indicates whether the extended or standard identifier format is applied in this buffer. In the case of a receive buffer, the flag is set as received and indicates to the CPU how to process the buffer identifier registers. In the case of a transmit buffer, the flag indicates to the MSCAN what type of identifier to send. 0 Standard format (11 bit) 1 Extended format (29 bit) Extended Format Identifier -- The identifiers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number.
2:0 ID[17:15]
7
6
5
4
3
2
1
0
R ID14 W Reset: x x x x x x x x ID13 ID12 ID11 ID10 ID9 ID8 ID7
Figure 12-25. Identifier Register 2 (IDR2) -- Extended Identifier Mapping Table 12-28. IDR2 Register Field Descriptions -- Extended
Field 7:0 ID[14:7] Description Extended Format Identifier -- The identifiers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number.
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7
6
5
4
3
2
1
0
R ID6 W Reset: x x x x x x x x ID5 ID4 ID3 ID2 ID1 ID0 RTR
Figure 12-26. Identifier Register 3 (IDR3) -- Extended Identifier Mapping Table 12-29. IDR3 Register Field Descriptions -- Extended
Field 7:1 ID[6:0] 0 RTR Description Extended Format Identifier -- The identifiers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number. Remote Transmission Request -- This flag reflects the status of the remote transmission request bit in the CAN frame. In the case of a receive buffer, it indicates the status of the received frame and supports the transmission of an answering frame in software. In the case of a transmit buffer, this flag defines the setting of the RTR bit to be sent. 0 Data frame 1 Remote frame
12.3.3.1.2
IDR0-IDR3 for Standard Identifier Mapping
7 6 5 4 3 2 1 0
R ID10 W Reset: x x x x x x x x ID9 ID8 ID7 ID6 ID5 ID4 ID3
Figure 12-27. Identifier Register 0 -- Standard Mapping Table 12-30. IDR0 Register Field Descriptions -- Standard
Field 7:0 ID[10:3] Description Standard Format Identifier -- The identifiers consist of 11 bits (ID[10:0]) for the standard format. ID10 is the most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number. See also ID bits in Table 12-31.
7
6
5
4
3
2
1
0
R ID2 W Reset: x x x x x x x x ID1 ID0 RTR IDE (=0)
= Unused; always read `x'
Figure 12-28. Identifier Register 1 -- Standard Mapping
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Table 12-31. IDR1 Register Field Descriptions
Field 7:5 ID[2:0] 4 RTR Description Standard Format Identifier -- The identifiers consist of 11 bits (ID[10:0]) for the standard format. ID10 is the most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number. See also ID bits in Table 12-30. Remote Transmission Request -- This flag reflects the status of the Remote Transmission Request bit in the CAN frame. In the case of a receive buffer, it indicates the status of the received frame and supports the transmission of an answering frame in software. In the case of a transmit buffer, this flag defines the setting of the RTR bit to be sent. 0 Data frame 1 Remote frame ID Extended -- This flag indicates whether the extended or standard identifier format is applied in this buffer. In the case of a receive buffer, the flag is set as received and indicates to the CPU how to process the buffer identifier registers. In the case of a transmit buffer, the flag indicates to the MSCAN what type of identifier to send. 0 Standard format (11 bit) 1 Extended format (29 bit)
3 IDE
7
6
5
4
3
2
1
0
R W Reset: x x x x x x x x
= Unused; always read `x'
Figure 12-29. Identifier Register 2 -- Standard Mapping
7 6 5 4 3 2 1 0
R W Reset: x x x x x x x x
= Unused; always read `x'
Figure 12-30. Identifier Register 3 -- Standard Mapping
12.3.3.2
Data Segment Registers (DSR0-7)
The eight data segment registers, each with bits DB[7:0], contain the data to be transmitted or received. The number of bytes to be transmitted or received is determined by the data length code in the corresponding DLR register.
MC9S12HZ256 Data Sheet, Rev. 2.05 364 Freescale Semiconductor
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
Module Base + 0x0004 (DSR0) 0x0005 (DSR1) 0x0006 (DSR2) 0x0007 (DSR3) 0x0008 (DSR4) 0x0009 (DSR5) 0x000A (DSR6) 0x000B (DSR7)
7 6 5 4 3 2 1 0
R DB7 W Reset: x x x x x x x x DB6 DB5 DB4 DB3 DB2 DB1 DB0
Figure 12-31. Data Segment Registers (DSR0-DSR7) -- Extended Identifier Mapping
Table 12-32. DSR0-DSR7 Register Field Descriptions
Field 7:0 DB[7:0] Data bits 7:0 Description
12.3.3.3
Data Length Register (DLR)
This register keeps the data length field of the CAN frame.
7 6 5 4 3 2 1 0
R DLC3 W Reset: x x x x x x x x DLC2 DLC1 DLC0
= Unused; always read "x"
Figure 12-32. Data Length Register (DLR) -- Extended Identifier Mapping
Table 12-33. DLR Register Field Descriptions
Field 3:0 DLC[3:0] Description Data Length Code Bits -- The data length code contains the number of bytes (data byte count) of the respective message. During the transmission of a remote frame, the data length code is transmitted as programmed while the number of transmitted data bytes is always 0. The data byte count ranges from 0 to 8 for a data frame. Table 12-34 shows the effect of setting the DLC bits.
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Table 12-34. Data Length Codes
Data Length Code DLC3 0 0 0 0 0 0 0 0 1 DLC2 0 0 0 0 1 1 1 1 0 DLC1 0 0 1 1 0 0 1 1 0 DLC0 0 1 0 1 0 1 0 1 0 Data Byte Count 0 1 2 3 4 5 6 7 8
12.3.3.4
Transmit Buffer Priority Register (TBPR)
This register defines the local priority of the associated message buffer. The local priority is used for the internal prioritization process of the MSCAN and is defined to be highest for the smallest binary number. The MSCAN implements the following internal prioritization mechanisms: * All transmission buffers with a cleared TXEx flag participate in the prioritization immediately before the SOF (start of frame) is sent. * The transmission buffer with the lowest local priority field wins the prioritization. In cases of more than one buffer having the same lowest priority, the message buffer with the lower index number wins.
7 6 5 4 3 2 1 0
R PRIO7 W Reset: 0 0 0 0 0 0 0 0 PRIO6 PRIO5 PRIO4 PRIO3 PRIO2 PRIO1 PRIO0
Figure 12-33. Transmit Buffer Priority Register (TBPR)
Read: Anytime when TXEx flag is set (see Section 12.3.2.7, "MSCAN Transmitter Flag Register (CANTFLG)") and the corresponding transmit buffer is selected in CANTBSEL (see Section 12.3.2.11, "MSCAN Transmit Buffer Selection Register (CANTBSEL)"). Write: Anytime when TXEx flag is set (see Section 12.3.2.7, "MSCAN Transmitter Flag Register (CANTFLG)") and the corresponding transmit buffer is selected in CANTBSEL (see Section 12.3.2.11, "MSCAN Transmit Buffer Selection Register (CANTBSEL)").
12.3.3.5
Time Stamp Register (TSRH-TSRL)
If the TIME bit is enabled, the MSCAN will write a special time stamp to the respective registers in the active transmit or receive buffer as soon as a message has been acknowledged on the CAN bus (see
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Section 12.3.2.1, "MSCAN Control Register 0 (CANCTL0)"). The time stamp is written on the bit sample point for the recessive bit of the ACK delimiter in the CAN frame. In case of a transmission, the CPU can only read the time stamp after the respective transmit buffer has been flagged empty. The timer value, which is used for stamping, is taken from a free running internal CAN bit clock. A timer overrun is not indicated by the MSCAN. The timer is reset (all bits set to 0) during initialization mode. The CPU can only read the time stamp registers.
7 6 5 4 3 2 1 0
R W Reset:
TSR15
TSR14
TSR13
TSR12
TSR11
TSR10
TSR9
TSR8
x
x
x
x
x
x
x
x
Figure 12-34. Time Stamp Register -- High Byte (TSRH)
7 6 5 4 3 2 1 0
R W Reset:
TSR7
TSR6
TSR5
TSR4
TSR3
TSR2
TSR1
TSR0
x
x
x
x
x
x
x
x
Figure 12-35. Time Stamp Register -- Low Byte (TSRL)
Read: Anytime when TXEx flag is set (see Section 12.3.2.7, "MSCAN Transmitter Flag Register (CANTFLG)") and the corresponding transmit buffer is selected in CANTBSEL (see Section 12.3.2.11, "MSCAN Transmit Buffer Selection Register (CANTBSEL)"). Write: Unimplemented
12.4
12.4.1
Functional Description
General
This section provides a complete functional description of the MSCAN. It describes each of the features and modes listed in the introduction.
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12.4.2
Message Storage
CAN Receive / Transmit Engine CPU12 Memory Mapped I/O
Rx0
Rx1 Rx2 Rx3 Rx4
RXF
RxBG
MSCAN
Receiver
Tx0
RxFG
CPU bus
TXE0
TxBG
Tx1
PRIO
TXE1
TxFG
MSCAN
CPU bus
PRIO
Tx2
TXE2
Transmitter
TxBG
PRIO
Figure 12-36. User Model for Message Buffer Organization
MSCAN facilitates a sophisticated message storage system which addresses the requirements of a broad range of network applications.
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12.4.2.1
Message Transmit Background
Modern application layer software is built upon two fundamental assumptions: * Any CAN node is able to send out a stream of scheduled messages without releasing the CAN bus between the two messages. Such nodes arbitrate for the CAN bus immediately after sending the previous message and only release the CAN bus in case of lost arbitration. * The internal message queue within any CAN node is organized such that the highest priority message is sent out first, if more than one message is ready to be sent. The behavior described in the bullets above cannot be achieved with a single transmit buffer. That buffer must be reloaded immediately after the previous message is sent. This loading process lasts a finite amount of time and must be completed within the inter-frame sequence (IFS) to be able to send an uninterrupted stream of messages. Even if this is feasible for limited CAN bus speeds, it requires that the CPU reacts with short latencies to the transmit interrupt. A double buffer scheme de-couples the reloading of the transmit buffer from the actual message sending and, therefore, reduces the reactiveness requirements of the CPU. Problems can arise if the sending of a message is finished while the CPU re-loads the second buffer. No buffer would then be ready for transmission, and the CAN bus would be released. At least three transmit buffers are required to meet the first of the above requirements under all circumstances. The MSCAN has three transmit buffers. The second requirement calls for some sort of internal prioritization which the MSCAN implements with the "local priority" concept described in Section 12.4.2.2, "Transmit Structures."
12.4.2.2
Transmit Structures
The MSCAN triple transmit buffer scheme optimizes real-time performance by allowing multiple messages to be set up in advance. The three buffers are arranged as shown in Figure 12-36. All three buffers have a 13-byte data structure similar to the outline of the receive buffers (see Section 12.3.3, "Programmer's Model of Message Storage"). An additional Section 12.3.3.4, "Transmit Buffer Priority Register (TBPR) contains an 8-bit local priority field (PRIO) (see Section 12.3.3.4, "Transmit Buffer Priority Register (TBPR)"). The remaining two bytes are used for time stamping of a message, if required (see Section 12.3.3.5, "Time Stamp Register (TSRH-TSRL)"). To transmit a message, the CPU must identify an available transmit buffer, which is indicated by a set transmitter buffer empty (TXEx) flag (see Section 12.3.2.7, "MSCAN Transmitter Flag Register (CANTFLG)"). If a transmit buffer is available, the CPU must set a pointer to this buffer by writing to the CANTBSEL register (see Section 12.3.2.11, "MSCAN Transmit Buffer Selection Register (CANTBSEL)"). This makes the respective buffer accessible within the CANTXFG address space (see Section 12.3.3, "Programmer's Model of Message Storage"). The algorithmic feature associated with the CANTBSEL register simplifies the transmit buffer selection. In addition, this scheme makes the handler software simpler because only one address area is applicable for the transmit process, and the required address space is minimized. The CPU then stores the identifier, the control bits, and the data content into one of the transmit buffers. Finally, the buffer is flagged as ready for transmission by clearing the associated TXE flag.
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The MSCAN then schedules the message for transmission and signals the successful transmission of the buffer by setting the associated TXE flag. A transmit interrupt (see Section 12.4.8.2, "Transmit Interrupt") is generated1 when TXEx is set and can be used to drive the application software to re-load the buffer. If more than one buffer is scheduled for transmission when the CAN bus becomes available for arbitration, the MSCAN uses the local priority setting of the three buffers to determine the prioritization. For this purpose, every transmit buffer has an 8-bit local priority field (PRIO). The application software programs this field when the message is set up. The local priority reflects the priority of this particular message relative to the set of messages being transmitted from this node. The lowest binary value of the PRIO field is defined to be the highest priority. The internal scheduling process takes place whenever the MSCAN arbitrates for the CAN bus. This is also the case after the occurrence of a transmission error. When a high priority message is scheduled by the application software, it may become necessary to abort a lower priority message in one of the three transmit buffers. Because messages that are already in transmission cannot be aborted, the user must request the abort by setting the corresponding abort request bit (ABTRQ) (see Section 12.3.2.9, "MSCAN Transmitter Message Abort Request Register (CANTARQ)".) The MSCAN then grants the request, if possible, by: 1. Setting the corresponding abort acknowledge flag (ABTAK) in the CANTAAK register. 2. Setting the associated TXE flag to release the buffer. 3. Generating a transmit interrupt. The transmit interrupt handler software can determine from the setting of the ABTAK flag whether the message was aborted (ABTAK = 1) or sent (ABTAK = 0).
12.4.2.3
Receive Structures
The received messages are stored in a five stage input FIFO. The five message buffers are alternately mapped into a single memory area (see Figure 12-36). The background receive buffer (RxBG) is exclusively associated with the MSCAN, but the foreground receive buffer (RxFG) is addressable by the CPU (see Figure 12-36). This scheme simplifies the handler software because only one address area is applicable for the receive process. All receive buffers have a size of 15 bytes to store the CAN control bits, the identifier (standard or extended), the data contents, and a time stamp, if enabled (see Section 12.3.3, "Programmer's Model of Message Storage"). The receiver full flag (RXF) (see Section 12.3.2.5, "MSCAN Receiver Flag Register (CANRFLG)") signals the status of the foreground receive buffer. When the buffer contains a correctly received message with a matching identifier, this flag is set. On reception, each message is checked to see whether it passes the filter (see Section 12.4.3, "Identifier Acceptance Filter") and simultaneously is written into the active RxBG. After successful reception of a valid message, the MSCAN shifts the content of RxBG into the receiver FIFO2, sets the RXF flag, and generates a receive interrupt (see Section 12.4.8.3, "Receive Interrupt") to the CPU3. The user's receive handler must read the received message from the RxFG and then reset the RXF flag to acknowledge the interrupt and to release the foreground buffer. A new message, which can follow immediately after the IFS
1. The transmit interrupt occurs only if not masked. A polling scheme can be applied on TXEx also. 2. Only if the RXF flag is not set. 3. The receive interrupt occurs only if not masked. A polling scheme can be applied on RXF also. MC9S12HZ256 Data Sheet, Rev. 2.05 370 Freescale Semiconductor
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field of the CAN frame, is received into the next available RxBG. If the MSCAN receives an invalid message in its RxBG (wrong identifier, transmission errors, etc.) the actual contents of the buffer will be over-written by the next message. The buffer will then not be shifted into the FIFO. When the MSCAN module is transmitting, the MSCAN receives its own transmitted messages into the background receive buffer, RxBG, but does not shift it into the receiver FIFO, generate a receive interrupt, or acknowledge its own messages on the CAN bus. The exception to this rule is in loopback mode (see Section 12.3.2.2, "MSCAN Control Register 1 (CANCTL1)") where the MSCAN treats its own messages exactly like all other incoming messages. The MSCAN receives its own transmitted messages in the event that it loses arbitration. If arbitration is lost, the MSCAN must be prepared to become a receiver. An overrun condition occurs when all receive message buffers in the FIFO are filled with correctly received messages with accepted identifiers and another message is correctly received from the CAN bus with an accepted identifier. The latter message is discarded and an error interrupt with overrun indication is generated if enabled (see Section 12.4.8.5, "Error Interrupt"). The MSCAN remains able to transmit messages while the receiver FIFO being filled, but all incoming messages are discarded. As soon as a receive buffer in the FIFO is available again, new valid messages will be accepted.
12.4.3
Identifier Acceptance Filter
The MSCAN identifier acceptance registers (see Section 12.3.2.12, "MSCAN Identifier Acceptance Control Register (CANIDAC)") define the acceptable patterns of the standard or extended identifier (ID[10:0] or ID[28:0]). Any of these bits can be marked `don't care' in the MSCAN identifier mask registers (see Section 12.3.2.17, "MSCAN Identifier Mask Registers (CANIDMR0-CANIDMR7)"). A filter hit is indicated to the application software by a set receive buffer full flag (RXF = 1) and three bits in the CANIDAC register (see Section 12.3.2.12, "MSCAN Identifier Acceptance Control Register (CANIDAC)"). These identifier hit flags (IDHIT[2:0]) clearly identify the filter section that caused the acceptance. They simplify the application software's task to identify the cause of the receiver interrupt. If more than one hit occurs (two or more filters match), the lower hit has priority. A very flexible programmable generic identifier acceptance filter has been introduced to reduce the CPU interrupt loading. The filter is programmable to operate in four different modes (see Bosch CAN 2.0A/B protocol specification): * Two identifier acceptance filters, each to be applied to: -- The full 29 bits of the extended identifier and to the following bits of the CAN 2.0B frame: - Remote transmission request (RTR) - Identifier extension (IDE) - Substitute remote request (SRR) -- The 11 bits of the standard identifier plus the RTR and IDE bits of the CAN 2.0A/B messages1. This mode implements two filters for a full length CAN 2.0B compliant extended identifier. Figure 12-37 shows how the first 32-bit filter bank (CANIDAR0-CANIDAR3, CANIDMR0-CANIDMR3) produces a filter 0 hit. Similarly, the second filter bank (CANIDAR4-CANIDAR7, CANIDMR4-CANIDMR7) produces a filter 1 hit.
1.Although this mode can be used for standard identifiers, it is recommended to use the four or eight identifier acceptance filters for standard identifiers MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 371
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*
*
*
Four identifier acceptance filters, each to be applied to -- a) the 14 most significant bits of the extended identifier plus the SRR and IDE bits of CAN 2.0B messages or -- b) the 11 bits of the standard identifier, the RTR and IDE bits of CAN 2.0A/B messages. Figure 12-38 shows how the first 32-bit filter bank (CANIDAR0-CANIDA3, CANIDMR0-3CANIDMR) produces filter 0 and 1 hits. Similarly, the second filter bank (CANIDAR4-CANIDAR7, CANIDMR4-CANIDMR7) produces filter 2 and 3 hits. Eight identifier acceptance filters, each to be applied to the first 8 bits of the identifier. This mode implements eight independent filters for the first 8 bits of a CAN 2.0A/B compliant standard identifier or a CAN 2.0B compliant extended identifier. Figure 12-39 shows how the first 32-bit filter bank (CANIDAR0-CANIDAR3, CANIDMR0-CANIDMR3) produces filter 0 to 3 hits. Similarly, the second filter bank (CANIDAR4-CANIDAR7, CANIDMR4-CANIDMR7) produces filter 4 to 7 hits. Closed filter. No CAN message is copied into the foreground buffer RxFG, and the RXF flag is never set.
IDR0 IDR0 ID21 ID3 ID20 ID2 IDR1 IDR1 ID15 IDE ID14 ID10 IDR2 IDR2 ID7 ID3 ID6 ID10 IDR3 IDR3 RTR ID3
CAN 2.0B Extended Identifier ID28 CAN 2.0A/B Standard Identifier ID10
AM7
CANIDMR0
AM0
AM7
CANIDMR1
AM0
AM7
CANIDMR2
AM0
AM7
CANIDMR3
AM0
AC7
CANIDAR0
AC0
AC7
CANIDAR1
AC0
AC7
CANIDAR2
AC0
AC7
CANIDAR3
AC0
ID Accepted (Filter 0 Hit)
Figure 12-37. 32-bit Maskable Identifier Acceptance Filter
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CAN 2.0B Extended Identifier CAN 2.0A/B Standard Identifier
ID28 ID10
IDR0 IDR0
ID21 ID3
ID20 ID2
IDR1 IDR1
ID15 IDE
ID14 ID10
IDR2 IDR2
ID7 ID3
ID6 ID10
IDR3 IDR3
RTR ID3
AM7
CANIDMR0
AM0
AM7
CANIDMR1
AM0
AC7
CANIDAR0
AC0
AC7
CANIDAR1
AC0
ID Accepted (Filter 0 Hit)
AM7
CANIDMR2
AM0
AM7
CANIDMR3
AM0
AC7
CANIDAR2
AC0
AC7
CANIDAR3
AC0
ID Accepted (Filter 1 Hit)
Figure 12-38. 16-bit Maskable Identifier Acceptance Filters
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CAN 2.0B Extended Identifier ID28 CAN 2.0A/B Standard Identifier ID10
IDR0 IDR0
ID21 ID3
ID20 ID2
IDR1 IDR1
ID15 IDE
ID14 ID10
IDR2 IDR2
ID7 ID3
ID6 ID10
IDR3 IDR3
RTR ID3
AM7
CIDMR0
AM0
AC7
CIDAR0
AC0
ID Accepted (Filter 0 Hit)
AM7
CIDMR1
AM0
AC7
CIDAR1
AC0
ID Accepted (Filter 1 Hit)
AM7
CIDMR2
AM0
AC7
CIDAR2
AC0
ID Accepted (Filter 2 Hit)
AM7
CIDMR3
AM0
AC7
CIDAR3
AC0
ID Accepted (Filter 3 Hit)
Figure 12-39. 8-bit Maskable Identifier Acceptance Filters
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12.4.3.1
Protocol Violation Protection
The MSCAN protects the user from accidentally violating the CAN protocol through programming errors. The protection logic implements the following features: * The receive and transmit error counters cannot be written or otherwise manipulated. * All registers which control the configuration of the MSCAN cannot be modified while the MSCAN is on-line. The MSCAN has to be in Initialization Mode. The corresponding INITRQ/INITAK handshake bits in the CANCTL0/CANCTL1 registers (see Section 12.3.2.1, "MSCAN Control Register 0 (CANCTL0)") serve as a lock to protect the following registers: -- MSCAN control 1 register (CANCTL1) -- MSCAN bus timing registers 0 and 1 (CANBTR0, CANBTR1) -- MSCAN identifier acceptance control register (CANIDAC) -- MSCAN identifier acceptance registers (CANIDAR0-CANIDAR7) -- MSCAN identifier mask registers (CANIDMR0-CANIDMR7) * The TXCAN pin is immediately forced to a recessive state when the MSCAN goes into the power down mode or initialization mode (see Section 12.4.6.6, "MSCAN Power Down Mode," and Section 12.4.6.5, "MSCAN Initialization Mode"). * The MSCAN enable bit (CANE) is writable only once in normal system operation modes, which provides further protection against inadvertently disabling the MSCAN.
12.4.3.2
Clock System
Figure 12-40 shows the structure of the MSCAN clock generation circuitry.
MSCAN
Bus Clock
CANCLK CLKSRC
Prescaler (1 .. 64)
Time quanta clock (Tq)
CLKSRC Oscillator Clock
Figure 12-40. MSCAN Clocking Scheme
The clock source bit (CLKSRC) in the CANCTL1 register (12.3.2.2/12-340) defines whether the internal CANCLK is connected to the output of a crystal oscillator (oscillator clock) or to the bus clock. The clock source has to be chosen such that the tight oscillator tolerance requirements (up to 0.4%) of the CAN protocol are met. Additionally, for high CAN bus rates (1 Mbps), a 45% to 55% duty cycle of the clock is required.
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If the bus clock is generated from a PLL, it is recommended to select the oscillator clock rather than the bus clock due to jitter considerations, especially at the faster CAN bus rates. For microcontrollers without a clock and reset generator (CRG), CANCLK is driven from the crystal oscillator (oscillator clock). A programmable prescaler generates the time quanta (Tq) clock from CANCLK. A time quantum is the atomic unit of time handled by the MSCAN.
Eqn. 12-2
f CANCLK = ----------------------------------------------------Tq ( Prescaler value ) A bit time is subdivided into three segments as described in the Bosch CAN specification. (see Figure 12-41): * SYNC_SEG: This segment has a fixed length of one time quantum. Signal edges are expected to happen within this section. * Time Segment 1: This segment includes the PROP_SEG and the PHASE_SEG1 of the CAN standard. It can be programmed by setting the parameter TSEG1 to consist of 4 to 16 time quanta. * Time Segment 2: This segment represents the PHASE_SEG2 of the CAN standard. It can be programmed by setting the TSEG2 parameter to be 2 to 8 time quanta long.
Eqn. 12-3
f Tq Bit Rate = -------------------------------------------------------------------------------( number of Time Quanta )
NRZ Signal
SYNC_SEG
Time Segment 1 (PROP_SEG + PHASE_SEG1) 4 ... 16 8 ... 25 Time Quanta = 1 Bit Time
Time Segment 2 (PHASE_SEG2) 2 ... 8
1
Transmit Point
Sample Point (single or triple sampling)
Figure 12-41. Segments within the Bit Time
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Table 12-35. Time Segment Syntax
Syntax SYNC_SEG Transmit Point Description System expects transitions to occur on the CAN bus during this period. A node in transmit mode transfers a new value to the CAN bus at this point. A node in receive mode samples the CAN bus at this point. If the three samples per bit option is selected, then this point marks the position of the third sample.
Sample Point
The synchronization jump width (see the Bosch CAN specification for details) can be programmed in a range of 1 to 4 time quanta by setting the SJW parameter. The SYNC_SEG, TSEG1, TSEG2, and SJW parameters are set by programming the MSCAN bus timing registers (CANBTR0, CANBTR1) (see Section 12.3.2.3, "MSCAN Bus Timing Register 0 (CANBTR0)" and Section 12.3.2.4, "MSCAN Bus Timing Register 1 (CANBTR1)"). Table 12-36 gives an overview of the CAN compliant segment settings and the related parameter values. NOTE It is the user's responsibility to ensure the bit time settings are in compliance with the CAN standard.
Table 12-36. CAN Standard Compliant Bit Time Segment Settings
Time Segment 1 5 .. 10 4 .. 11 5 .. 12 6 .. 13 7 .. 14 8 .. 15 9 .. 16 TSEG1 4 .. 9 3 .. 10 4 .. 11 5 .. 12 6 .. 13 7 .. 14 8 .. 15 Time Segment 2 2 3 4 5 6 7 8 TSEG2 1 2 3 4 5 6 7 Synchronization Jump Width 1 .. 2 1 .. 3 1 .. 4 1 .. 4 1 .. 4 1 .. 4 1 .. 4 SJW 0 .. 1 0 .. 2 0 .. 3 0 .. 3 0 .. 3 0 .. 3 0 .. 3
12.4.4
Timer Link
The MSCAN generates an internal time stamp whenever a valid frame is received or transmitted and the TIME bit is enabled. Because the CAN specification defines a frame to be valid if no errors occur before the end of frame (EOF) field is transmitted successfully, the actual value of an internal timer is written at EOF to the appropriate time stamp position within the transmit buffer. For receive frames, the time stamp is written to the receive buffer.
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12.4.5
12.4.5.1
Modes of Operation
Normal Modes
The MSCAN module behaves as described within this specification in all normal system operation modes.
12.4.5.2
Special Modes
The MSCAN module behaves as described within this specification in all special system operation modes.
12.4.5.3
Emulation Modes
In all emulation modes, the MSCAN module behaves just like normal system operation modes as described within this specification.
12.4.5.4
Listen-Only Mode
In an optional CAN bus monitoring mode (listen-only), the CAN node is able to receive valid data frames and valid remote frames, but it sends only "recessive" bits on the CAN bus. In addition, it cannot start a transmision. If the MAC sub-layer is required to send a "dominant" bit (ACK bit, overload flag, or active error flag), the bit is rerouted internally so that the MAC sub-layer monitors this "dominant" bit, although the CAN bus may remain in recessive state externally.
12.4.5.5
Security Modes
The MSCAN module has no security features.
12.4.6
Low-Power Options
If the MSCAN is disabled (CANE = 0), the MSCAN clocks are stopped for power saving. If the MSCAN is enabled (CANE = 1), the MSCAN has two additional modes with reduced power consumption, compared to normal mode: sleep and power down mode. In sleep mode, power consumption is reduced by stopping all clocks except those to access the registers from the CPU side. In power down mode, all clocks are stopped and no power is consumed. Table 12-37 summarizes the combinations of MSCAN and CPU modes. A particular combination of modes is entered by the given settings on the CSWAI and SLPRQ/SLPAK bits. For all modes, an MSCAN wake-up interrupt can occur only if the MSCAN is in sleep mode (SLPRQ = 1 and SLPAK = 1), wake-up functionality is enabled (WUPE = 1), and the wake-up interrupt is enabled (WUPIE = 1).
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Table 12-37. CPU vs. MSCAN Operating Modes
MSCAN Mode CPU Mode Normal Sleep CSWAI = X1 SLPRQ = 0 SLPAK = 0 CSWAI = 0 SLPRQ = 0 SLPAK = 0 CSWAI = X SLPRQ = 1 SLPAK = 1 CSWAI = 0 SLPRQ = 1 SLPAK = 1 CSWAI = 1 SLPRQ = X SLPAK = X CSWAI = X SLPRQ = X SLPAK = X Power Down Reduced Power Consumption Disabled (CANE=0) CSWAI = X SLPRQ = X SLPAK = X CSWAI = X SLPRQ = X SLPAK = X CSWAI = X SLPRQ = X SLPAK = X
RUN
WAIT
STOP
1
`X' means don't care.
12.4.6.1
Operation in Run Mode
As shown in Table 12-37, only MSCAN sleep mode is available as low power option when the CPU is in run mode.
12.4.6.2
Operation in Wait Mode
The WAI instruction puts the MCU in a low power consumption stand-by mode. If the CSWAI bit is set, additional power can be saved in power down mode because the CPU clocks are stopped. After leaving this power down mode, the MSCAN restarts its internal controllers and enters normal mode again. While the CPU is in wait mode, the MSCAN can be operated in normal mode and generate interrupts (registers can be accessed via background debug mode). The MSCAN can also operate in any of the low-power modes depending on the values of the SLPRQ/SLPAK and CSWAI bits as seen in Table 12-37.
12.4.6.3
Operation in Stop Mode
The STOP instruction puts the MCU in a low power consumption stand-by mode. In stop mode, the MSCAN is set in power down mode regardless of the value of the SLPRQ/SLPAK and CSWAI bits Table 12-37.
12.4.6.4
MSCAN Sleep Mode
The CPU can request the MSCAN to enter this low power mode by asserting the SLPRQ bit in the CANCTL0 register. The time when the MSCAN enters sleep mode depends on a fixed synchronization delay and its current activity:
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*
* *
If there are one or more message buffers scheduled for transmission (TXEx = 0), the MSCAN will continue to transmit until all transmit message buffers are empty (TXEx = 1, transmitted successfully or aborted) and then goes into sleep mode. If the MSCAN is receiving, it continues to receive and goes into sleep mode as soon as the CAN bus next becomes idle. If the MSCAN is neither transmitting nor receiving, it immediately goes into sleep mode.
Bus Clock Domain
CAN Clock Domain SLPRQ Flag
SLPRQ CPU Sleep Request
SYNC
sync. SLPRQ
SLPAK Flag
sync.
SLPAK
SYNC
SLPAK MSCAN in Sleep Mode
Figure 12-42. Sleep Request / Acknowledge Cycle
NOTE The application software must avoid setting up a transmission (by clearing one or more TXEx flag(s)) and immediately request sleep mode (by setting SLPRQ). Whether the MSCAN starts transmitting or goes into sleep mode directly depends on the exact sequence of operations. If sleep mode is active, the SLPRQ and SLPAK bits are set (Figure 12-42). The application software must use SLPAK as a handshake indication for the request (SLPRQ) to go into sleep mode. When in sleep mode (SLPRQ = 1 and SLPAK = 1), the MSCAN stops its internal clocks. However, clocks that allow register accesses from the CPU side continue to run. If the MSCAN is in bus-off state, it stops counting the 128 occurrences of 11 consecutive recessive bits due to the stopped clocks. The TXCAN pin remains in a recessive state. If RXF = 1, the message can be read and RXF can be cleared. Shifting a new message into the foreground buffer of the receiver FIFO (RxFG) does not take place while in sleep mode. It is possible to access the transmit buffers and to clear the associated TXE flags. No message abort takes place while in sleep mode. If the WUPE bit in CANCLT0 is not asserted, the MSCAN will mask any activity it detects on CAN. The RXCAN pin is therefore held internally in a recessive state. This locks the MSCAN in sleep mode (Figure 12-43).
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Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
The MSCAN is able to leave sleep mode (wake up) only when: * CAN bus activity occurs and WUPE = 1 or * the CPU clears the SLPRQ bit NOTE The CPU cannot clear the SLPRQ bit before sleep mode (SLPRQ = 1 and SLPAK = 1) is active. After wake-up, the MSCAN waits for 11 consecutive recessive bits to synchronize to the CAN bus. As a consequence, if the MSCAN is woken-up by a CAN frame, this frame is not received. The receive message buffers (RxFG and RxBG) contain messages if they were received before sleep mode was entered. All pending actions will be executed upon wake-up; copying of RxBG into RxFG, message aborts and message transmissions. If the MSCAN remains in bus-off state after sleep mode was exited, it continues counting the 128 occurrences of 11 consecutive recessive bits.
CAN Activity
StartUp
Wait for Idle
CAN Activity SLPRQ
(CAN Activity & WUPE) | SLPRQ
CAN Activity & SLPRQ
Idle
Sleep
(CAN Activity & WUPE) |
CAN Activity & SLPRQ
CAN Activity CAN Activity
Tx/Rx Message Active
CAN Activity
Figure 12-43. Simplified State Transitions for Entering/Leaving Sleep Mode
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 381
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
12.4.6.5
MSCAN Initialization Mode
In initialization mode, any on-going transmission or reception is immediately aborted and synchronization to the CAN bus is lost, potentially causing CAN protocol violations. To protect the CAN bus system from fatal consequences of violations, the MSCAN immediately drives the TXCAN pin into a recessive state. NOTE The user is responsible for ensuring that the MSCAN is not active when initialization mode is entered. The recommended procedure is to bring the MSCAN into sleep mode (SLPRQ = 1 and SLPAK = 1) before setting the INITRQ bit in the CANCTL0 register. Otherwise, the abort of an on-going message can cause an error condition and can impact other CAN bus devices. In initialization mode, the MSCAN is stopped. However, interface registers remain accessible. This mode is used to reset the CANCTL0, CANRFLG, CANRIER, CANTFLG, CANTIER, CANTARQ, CANTAAK, and CANTBSEL registers to their default values. In addition, the MSCAN enables the configuration of the CANBTR0, CANBTR1 bit timing registers; CANIDAC; and the CANIDAR, CANIDMR message filters. See Section 12.3.2.1, "MSCAN Control Register 0 (CANCTL0)," for a detailed description of the initialization mode.
Bus Clock Domain
CAN Clock Domain INIT Flag
INITRQ CPU Init Request
SYNC
sync. INITRQ
INITAK Flag
sync.
INITAK
SYNC
INITAK
Figure 12-44. Initialization Request/Acknowledge Cycle
Due to independent clock domains within the MSCAN, INITRQ must be synchronized to all domains by using a special handshake mechanism. This handshake causes additional synchronization delay (see Section Figure 12-44., "Initialization Request/Acknowledge Cycle"). If there is no message transfer ongoing on the CAN bus, the minimum delay will be two additional bus clocks and three additional CAN clocks. When all parts of the MSCAN are in initialization mode, the INITAK flag is set. The application software must use INITAK as a handshake indication for the request (INITRQ) to go into initialization mode. NOTE The CPU cannot clear INITRQ before initialization mode (INITRQ = 1 and INITAK = 1) is active.
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Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
12.4.6.6
MSCAN Power Down Mode
The MSCAN is in power down mode (Table 12-37) when * CPU is in stop mode or * CPU is in wait mode and the CSWAI bit is set When entering the power down mode, the MSCAN immediately stops all ongoing transmissions and receptions, potentially causing CAN protocol violations. To protect the CAN bus system from fatal consequences of violations to the above rule, the MSCAN immediately drives the TXCAN pin into a recessive state. NOTE The user is responsible for ensuring that the MSCAN is not active when power down mode is entered. The recommended procedure is to bring the MSCAN into Sleep mode before the STOP or WAI instruction (if CSWAI is set) is executed. Otherwise, the abort of an ongoing message can cause an error condition and impact other CAN bus devices. In power down mode, all clocks are stopped and no registers can be accessed. If the MSCAN was not in sleep mode before power down mode became active, the module performs an internal recovery cycle after powering up. This causes some fixed delay before the module enters normal mode again.
12.4.6.7
Programmable Wake-Up Function
The MSCAN can be programmed to wake up the MSCAN as soon as CAN bus activity is detected (see control bit WUPE in Section 12.3.2.1, "MSCAN Control Register 0 (CANCTL0)"). The sensitivity to existing CAN bus action can be modified by applying a low-pass filter function to the RXCAN input line while in sleep mode (see control bit WUPM in Section 12.3.2.2, "MSCAN Control Register 1 (CANCTL1)"). This feature can be used to protect the MSCAN from wake-up due to short glitches on the CAN bus lines. Such glitches can result from--for example--electromagnetic interference within noisy environments.
12.4.7
Reset Initialization
The reset state of each individual bit is listed in Section 12.3.2, "Register Descriptions," which details all the registers and their bit-fields.
12.4.8
Interrupts
This section describes all interrupts originated by the MSCAN. It documents the enable bits and generated flags. Each interrupt is listed and described separately.
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Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
12.4.8.1
Description of Interrupt Operation
The MSCAN supports four interrupt vectors (see Table 12-38), any of which can be individually masked (for details see sections from Section 12.3.2.6, "MSCAN Receiver Interrupt Enable Register (CANRIER)," to Section 12.3.2.8, "MSCAN Transmitter Interrupt Enable Register (CANTIER)"). NOTE The dedicated interrupt vector addresses are defined in the Resets and Interrupts chapter.
Table 12-38. Interrupt Vectors
Interrupt Source Wake-Up Interrupt (WUPIF) Error Interrupts Interrupt (CSCIF, OVRIF) Receive Interrupt (RXF) Transmit Interrupts (TXE[2:0]) CCR Mask I bit I bit I bit I bit Local Enable CANRIER (WUPIE) CANRIER (CSCIE, OVRIE) CANRIER (RXFIE) CANTIER (TXEIE[2:0])
12.4.8.2
Transmit Interrupt
At least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message for transmission. The TXEx flag of the empty message buffer is set.
12.4.8.3
Receive Interrupt
A message is successfully received and shifted into the foreground buffer (RxFG) of the receiver FIFO. This interrupt is generated immediately after receiving the EOF symbol. The RXF flag is set. If there are multiple messages in the receiver FIFO, the RXF flag is set as soon as the next message is shifted to the foreground buffer.
12.4.8.4
Wake-Up Interrupt
A wake-up interrupt is generated if activity on the CAN bus occurs during MSCN internal sleep mode. WUPE (see Section 12.3.2.1, "MSCAN Control Register 0 (CANCTL0)") must be enabled.
12.4.8.5
Error Interrupt
An error interrupt is generated if an overrun of the receiver FIFO, error, warning, or bus-off condition occurrs. Section 12.3.2.5, "MSCAN Receiver Flag Register (CANRFLG) indicates one of the following conditions: * Overrun -- An overrun condition of the receiver FIFO as described in Section 12.4.2.3, "Receive Structures," occurred. * CAN Status Change -- The actual value of the transmit and receive error counters control the CAN bus state of the MSCAN. As soon as the error counters skip into a critical range (Tx/Rx-warning, Tx/Rx-error, bus-off) the MSCAN flags an error condition. The status change, which caused the error condition, is indicated by the TSTAT and RSTAT flags (see
MC9S12HZ256 Data Sheet, Rev. 2.05 384 Freescale Semiconductor
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
Section 12.3.2.5, "MSCAN Receiver Flag Register (CANRFLG)" and Section 12.3.2.6, "MSCAN Receiver Interrupt Enable Register (CANRIER)").
12.4.8.6
Interrupt Acknowledge
Interrupts are directly associated with one or more status flags in either the Section 12.3.2.5, "MSCAN Receiver Flag Register (CANRFLG)" or the Section 12.3.2.7, "MSCAN Transmitter Flag Register (CANTFLG)." Interrupts are pending as long as one of the corresponding flags is set. The flags in CANRFLG and CANTFLG must be reset within the interrupt handler to handshake the interrupt. The flags are reset by writing a 1 to the corresponding bit position. A flag cannot be cleared if the respective condition prevails. NOTE It must be guaranteed that the CPU clears only the bit causing the current interrupt. For this reason, bit manipulation instructions (BSET) must not be used to clear interrupt flags. These instructions may cause accidental clearing of interrupt flags which are set after entering the current interrupt service routine.
12.4.8.7
Recovery from Stop or Wait
The MSCAN can recover from stop or wait via the wake-up interrupt. This interrupt can only occur if the MSCAN was in sleep mode (SLPRQ = 1 and SLPAK = 1) before entering power down mode, the wake-up option is enabled (WUPE = 1), and the wake-up interrupt is enabled (WUPIE = 1).
12.5
12.5.1
Initialization/Application Information
MSCAN initialization
The procedure to initially start up the MSCAN module out of reset is as follows: 1. Assert CANE 2. Write to the configuration registers in initialization mode 3. Clear INITRQ to leave initialization mode and enter normal mode If the configuration of registers which are writable in initialization mode needs to be changed only when the MSCAN module is in normal mode: 1. Bring the module into sleep mode by setting SLPRQ and awaiting SLPAK to assert after the CAN bus becomes idle. 2. Enter initialization mode: assert INITRQ and await INITAK 3. Write to the configuration registers in initialization mode 4. Clear INITRQ to leave initialization mode and continue in normal mode
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 385
Chapter 12 Freescale's Scalable Controller Area Network (MSCANV2)
MC9S12HZ256 Data Sheet, Rev. 2.05 386 Freescale Semiconductor
Chapter 13 Serial Communication Interface (SCIV4)
13.1 Introduction
This block description chapter provides an overview of serial communication interface (SCI) module. The SCI allows full duplex, asynchronous, serial communication between the CPU and remote devices, including other CPUs. The SCI transmitter and receiver operate independently, although they use the same baud rate generator. The CPU monitors the status of the SCI, writes the data to be transmitted, and processes received data.
13.1.1
IR: infrared
Glossary
IrDA: Infrared Design Association IRQ: interrupt request LSB: least significant bit MSB: most significant bit NRZ: non-return-to-Zero RZI: return-to-zero-inverted RXD: receive pin SCI: serial communication interface TXD: transmit pin
13.1.2
Features
The SCI includes these distinctive features: * Full-duplex or single-wire operation * Standard mark/space non-return-to-zero (NRZ) format * Selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse widths * 13-bit baud rate selection * Programmable 8-bit or 9-bit data format * Separately enabled transmitter and receiver * Programmable polarity for transmitter and receiver
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Chapter 13 Serial Communication Interface (SCIV4)
* *
*
* * *
Programmable transmitter output parity Two receiver wakeup methods: -- Idle line wakeup -- Address mark wakeup Interrupt-driven operation with eight flags: -- Transmitter empty -- Transmission complete -- Receiver full -- Idle receiver input -- Receiver overrun -- Noise error -- Framing error -- Parity error Receiver framing error detection Hardware parity checking 1/16 bit-time noise detection
13.1.3
Modes of Operation
The SCI functions the same in normal, special, and emulation modes. It has two low-power modes, wait and stop modes.
13.1.3.1
Run Mode
Normal mode of operation.
13.1.3.2
Wait Mode
SCI operation in wait mode depends on the state of the SCISWAI bit in the SCI control register 1 (SCICR1). * If SCISWAI is clear, the SCI operates normally when the CPU is in wait mode. * If SCISWAI is set, SCI clock generation ceases and the SCI module enters a power-conservation state when the CPU is in wait mode. Setting SCISWAI does not affect the state of the receiver enable bit, RE, or the transmitter enable bit, TE. If SCISWAI is set, any transmission or reception in progress stops at wait mode entry. The transmission or reception resumes when either an internal or external interrupt brings the CPU out of wait mode. Exiting wait mode by reset aborts any transmission or reception in progress and resets the SCI.
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Chapter 13 Serial Communication Interface (SCIV4)
13.1.3.3
Stop Mode
The SCI is inactive during stop mode for reduced power consumption. The STOP instruction does not affect the SCI register states, but the SCI bus clock will be disabled. The SCI operation resumes after an external interrupt brings the CPU out of stop mode. Exiting stop mode by reset aborts any transmission or reception in progress and resets the SCI.
13.1.4
Block Diagram
Figure 13-1 is a high level block diagram of the SCI module, showing the interaction of various function blocks.
SCI Data Register IDLE Interrupt Request RXD Data In Infrared Decoder Receive Shift Register IRQ Generation
Receive & Wakeup Control
RDRF/OR Interrupt Request TDRE Interrupt Request
Bus Clk
BAUD Generator
/16
Data Format Control
SCI Interrupt Request
Transmit Control
Transmit Shift Register
IRQ Generation TC Interrupt Request
SCI Data Register
Infrared Encoder
Data Out
TXD
Figure 13-1. SCI Block Diagram
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 389
Chapter 13 Serial Communication Interface (SCIV4)
13.2
External Signal Descriptions
The SCI module has a total of two external pins.
13.2.1
TXD -- SCI Transmit Pin
The TXD pin transmits SCI (standard or infrared) data. It will idle high in either mode and is high impedance anytime the transmitter is disabled.
13.2.2
RXD -- SCI Receive Pin
The RXD pin receives SCI (standard or infrared) data. An idle line is detected as a line high. This input is ignored when the receiver is disabled and should be terminated to a known voltage.
13.3
Memory Map and Register Definition
This subsection provides a detailed description of all the SCI registers.
13.3.1
Module Memory Map
The memory map for the SCI module is given in Figure 13-2. The address listed for each register is the address offset. The total address for each register is the sum of the base address for the SCI module and the address offset for each register.
13.3.2
Register Descriptions
This subsection consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Writes to reserved register locations do not have any effect and reads of these locations return a 0. Details of register bit and field function follow the register diagrams, in bit order.
Register Name SCIBDH R IREN W SCIBDL R SBR7 W SCICR1 R LOOPS W = Unimplemented or Reserved SCISWAI RSRC M WAKE ILT PE PT SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 TNP1 TNP0 SBR12 SBR11 SBR10 SBR9 SBR8
Bit 7
6
5
4
3
2
1
Bit 0
Figure 13-2. SCI Registers Summary
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Chapter 13 Serial Communication Interface (SCIV4)
Register Name SCICR2 R
Bit 7
6
5
4
3
2
1
Bit 0
TIE W SCISR1 R W SCISR2 R W SCIDRH R W SCIDRL R W R7 T7 R8 0 TDRE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
TC
RDRF
IDLE
OR
NF
FE
PF
0
0 TXPOL RXPOL BRK13 TXDIR
RAF
0 T8
0
0
0
0
0
R6 T6
R5 T5
R4 T4
R3 T3
R2 T2
R1 T1
R0 T0
= Unimplemented or Reserved
Figure 13-2. SCI Registers Summary
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 391
Chapter 13 Serial Communication Interface (SCIV4)
13.3.2.1
SCI Baud Rate Registers (SCIBDH and SCIBDL)
7 6 5 4 3 2 1 0
R IREN W Reset 0 0 0 0 0 0 0 0 TNP1 TNP0 SBR12 SBR11 SBR10 SBR9 SBR8
Figure 13-3. SCI Baud Rate Register High (SCIBDH) Table 13-1. SCIBDH Field Descriptions
Field 7 IREN 6:5 TNP[1:0] 4:0 SBR[11:8] Description Infrared Enable Bit -- This bit enables/disables the infrared modulation/demodulation submodule. 0 IR disabled 1 IR enabled Transmitter Narrow Pulse Bits -- These bits determine if the SCI will transmit a 1/16, 3/16, 1/32, or 1/4 narrow pulse. Refer to Table 13-3. SCI Baud Rate Bits -- The baud rate for the SCI is determined by the bits in this register. The baud rate is calculated two different ways depending on the state of the IREN bit. The formulas for calculating the baud rate are: When IREN = 0 then, SCI baud rate = SCI module clock / (16 x SBR[12:0]) When IREN = 1 then, SCI baud rate = SCI module clock / (32 x SBR[12:1])
7
6
5
4
3
2
1
0
R SBR7 W Reset 0 0 0 0 0 1 0 0 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0
Figure 13-4. SCI Baud Rate Register Low (SCIBDL) Table 13-2. SCIBDL Field Descriptions
Field 7:0 SBR[7:0] Description SCI Baud Rate Bits -- The baud rate for the SCI is determined by the bits in this register. The baud rate is calculated two different ways depending on the state of the IREN bit. The formulas for calculating the baud rate are: When IREN = 0 then, SCI baud rate = SCI module clock / (16 x SBR[12:0]) When IREN = 1 then, SCI baud rate = SCI module clock / (32 x SBR[12:1])
Read: anytime
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Chapter 13 Serial Communication Interface (SCIV4)
NOTE If only SCIBDH is written to, a read will not return the correct data until SCIBDL is written to as well, following a write to SCIBDH. Write: anytime The SCI baud rate register is used to determine the baud rate of the SCI and to control the infrared modulation/demodulation submodule.
Table 13-3. IRSCI Transmit Pulse Width
TNP[1:0] 11 10 01 00 Narrow Pulse Width 1/4 1/32 1/16 3/16
NOTE The baud rate generator is disabled after reset and not started until the TE bit or the RE bit is set for the first time. The baud rate generator is disabled when (SBR[12:0] = 0 and IREN = 0) or (SBR[12:1] = 0 and IREN = 1). Writing to SCIBDH has no effect without writing to SCIBDL, because writing to SCIBDH puts the data in a temporary location until SCIBDL is written to.
13.3.2.2
SCI Control Register 1 (SCICR1)
7 6 5 4 3 2 1 0
R LOOPS W Reset 0 0 0 0 0 0 0 0 SCISWAI RSRC M WAKE ILT PE PT
Figure 13-5. SCI Control Register 1 (SCICR1)
Read: anytime Write: anytime
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Chapter 13 Serial Communication Interface (SCIV4)
Table 13-4. SCICR1 Field Descriptions
Field 7 LOOPS Description Loop Select Bit -- LOOPS enables loop operation. In loop operation, the RXD pin is disconnected from the SCI and the transmitter output is internally connected to the receiver input. Both the transmitter and the receiver must be enabled to use the loop function. 0 Normal operation enabled 1 Loop operation enabled The receiver input is determined by the RSRC bit. SCI Stop in Wait Mode Bit -- SCISWAI disables the SCI in wait mode. 0 SCI enabled in wait mode 1 SCI disabled in wait mode Receiver Source Bit -- When LOOPS = 1, the RSRC bit determines the source for the receiver shift register input. 0 Receiver input internally connected to transmitter output 1 Receiver input connected externally to transmitter Refer to Table 13-5. Data Format Mode Bit -- MODE determines whether data characters are eight or nine bits long. 0 One start bit, eight data bits, one stop bit 1 One start bit, nine data bits, one stop bit Wakeup Condition Bit -- WAKE determines which condition wakes up the SCI: a logic 1 (address mark) in the most significant bit position of a received data character or an idle condition on the RXD pin. 0 Idle line wakeup 1 Address mark wakeup Idle Line Type Bit -- ILT determines when the receiver starts counting logic 1s as idle character bits. The counting begins either after the start bit or after the stop bit. If the count begins after the start bit, then a string of logic 1s preceding the stop bit may cause false recognition of an idle character. Beginning the count after the stop bit avoids false idle character recognition, but requires properly synchronized transmissions. 0 Idle character bit count begins after start bit 1 Idle character bit count begins after stop bit Parity Enable Bit -- PE enables the parity function. When enabled, the parity function inserts a parity bit in the most significant bit position. 0 Parity function disabled 1 Parity function enabled Parity Type Bit -- PT determines whether the SCI generates and checks for even parity or odd parity. With even parity, an even number of 1s clears the parity bit and an odd number of 1s sets the parity bit. With odd parity, an odd number of 1s clears the parity bit and an even number of 1s sets the parity bit. 0 Even parity 1 Odd parity
6 SCISWAI 5 RSRC
4 M 3 WAKE
2 ILT
1 PE
0 PT
Table 13-5. Loop Functions
LOOPS 0 1 1 RSRC x 0 1 Normal operation Loop mode with transmitter output internally connected to receiver input Single-wire mode with TXD pin connected to receiver input Function
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Chapter 13 Serial Communication Interface (SCIV4)
13.3.2.3
SCI Control Register 2 (SCICR2)
7 6 5 4 3 2 1 0
R TIE W Reset 0 0 0 0 0 0 0 0 TCIE RIE ILIE TE RE RWU SBK
Figure 13-6. SCI Control Register 2 (SCICR2)
Read: anytime Write: anytime
Table 13-6. SCICR2 Field Descriptions
Field 7 TIE Description Transmitter Interrupt Enable Bit --TIE enables the transmit data register empty flag, TDRE, to generate interrupt requests. 0 TDRE interrupt requests disabled 1 TDRE interrupt requests enabled Transmission Complete Interrupt Enable Bit -- TCIE enables the transmission complete flag, TC, to generate interrupt requests. 0 TC interrupt requests disabled 1 TC interrupt requests enabled Receiver Full Interrupt Enable Bit -- RIE enables the receive data register full flag, RDRF, or the overrun flag, OR, to generate interrupt requests. 0 RDRF and OR interrupt requests disabled 1 RDRF and OR interrupt requests enabled Idle Line Interrupt Enable Bit -- ILIE enables the idle line flag, IDLE, to generate interrupt requests. 0 IDLE interrupt requests disabled 1 IDLE interrupt requests enabled Transmitter Enable Bit -- TE enables the SCI transmitter and configures the TXD pin as being controlled by the SCI. The TE bit can be used to queue an idle preamble. 0 Transmitter disabled 1 Transmitter enabled Receiver Enable Bit -- RE enables the SCI receiver. 0 Receiver disabled 1 Receiver enabled Receiver Wakeup Bit -- Standby state 0 Normal operation. 1 RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU. Send Break Bit -- Toggling SBK sends one break character (10 or 11 logic 0s, respectively 13 or 14 logics 0s if BRK13 is set). Toggling implies clearing the SBK bit before the break character has finished transmitting. As long as SBK is set, the transmitter continues to send complete break characters (10 or 11 bits, respectively 13 or 14 bits). 0 No break characters 1 Transmit break characters
6 TCIE
5 RIE
4 ILIE 3 TE
2 RE 1 RWU
0 SBK
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Chapter 13 Serial Communication Interface (SCIV4)
13.3.2.4
SCI Status Register 1 (SCISR1)
The SCISR1 and SCISR2 registers provide inputs to the MCU for generation of SCI interrupts. Also, these registers can be polled by the MCU to check the status of these bits. The flag-clearing procedures require that the status register be read followed by a read or write to the SCI data register. It is permissible to execute other instructions between the two steps as long as it does not compromise the handling of I/O. Note that the order of operations is important for flag clearing.
7 6 5 4 3 2 1 0
R W Reset
TDRE
TC
RDRF
IDLE
OR
NF
FE
PF
1
1
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 13-7. SCI Status Register 1 (SCISR1)
Read: anytime Write: has no meaning or effect
Table 13-7. SCISR1 Field Descriptions
Field 7 TDRE Description Transmit Data Register Empty Flag -- TDRE is set when the transmit shift register receives a byte from the SCI data register. When TDRE is 1, the transmit data register (SCIDRH/L) is empty and can receive a new value to transmit.Clear TDRE by reading SCI status register 1 (SCISR1), with TDRE set and then writing to SCI data register low (SCIDRL). 0 No byte transferred to transmit shift register 1 Byte transferred to transmit shift register; transmit data register empty Transmit Complete Flag -- TC is set low when there is a transmission in progress or when a preamble or break character is loaded. TC is set high when the TDRE flag is set and no data, preamble, or break character is being transmitted.When TC is set, the TXD pin becomes idle (logic 1). Clear TC by reading SCI status register 1 (SCISR1) with TC set and then writing to SCI data register low (SCIDRL). TC is cleared automatically when data, preamble, or break is queued and ready to be sent. TC is cleared in the event of a simultaneous set and clear of the TC flag (transmission not complete). 0 Transmission in progress 1 No transmission in progress Receive Data Register Full Flag -- RDRF is set when the data in the receive shift register transfers to the SCI data register. Clear RDRF by reading SCI status register 1 (SCISR1) with RDRF set and then reading SCI data register low (SCIDRL). 0 Data not available in SCI data register 1 Received data available in SCI data register Idle Line Flag1 -- IDLE is set when 10 consecutive logic 1s (if M = 0) or 11 consecutive logic 1s (if M = 1) appear on the receiver input. After the IDLE flag is cleared, a valid frame must again set the RDRF flag before an idle condition can set the IDLE flag.Clear IDLE by reading SCI status register 1 (SCISR1) with IDLE set and then reading SCI data register low (SCIDRL). 0 Receiver input is either active now or has never become active since the IDLE flag was last cleared 1 Receiver input has become idle
6 TC
5 RDRF
4 IDLE
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Chapter 13 Serial Communication Interface (SCIV4)
Table 13-7. SCISR1 Field Descriptions (continued)
Field 3 OR Description Overrun Flag2 -- OR is set when software fails to read the SCI data register before the receive shift register receives the next frame. The OR bit is set immediately after the stop bit has been completely received for the second frame. The data in the shift register is lost, but the data already in the SCI data registers is not affected. Clear OR by reading SCI status register 1 (SCISR1) with OR set and then reading SCI data register low (SCIDRL). 0 No overrun 1 Overrun Noise Flag -- NF is set when the SCI detects noise on the receiver input. NF bit is set during the same cycle as the RDRF flag but does not get set in the case of an overrun. Clear NF by reading SCI status register 1(SCISR1), and then reading SCI data register low (SCIDRL). 0 No noise 1 Noise Framing Error Flag -- FE is set when a logic 0 is accepted as the stop bit. FE bit is set during the same cycle as the RDRF flag but does not get set in the case of an overrun. FE inhibits further data reception until it is cleared. Clear FE by reading SCI status register 1 (SCISR1) with FE set and then reading the SCI data register low (SCIDRL). 0 No framing error 1 Framing error Parity Error Flag -- PF is set when the parity enable bit (PE) is set and the parity of the received data does not match the parity type bit (PT). PF bit is set during the same cycle as the RDRF flag but does not get set in the case of an overrun. Clear PF by reading SCI status register 1 (SCISR1), and then reading SCI data register low (SCIDRL). 0 No parity error 1 Parity error
2 NF
1 FE
0 PF
1 2
When the receiver wakeup bit (RWU) is set, an idle line condition does not set the IDLE flag. The OR flag may read back as set when RDRF flag is clear. This may happen if the following sequence of events occurs: 1. After the first frame is received, read status register SCISR1 (returns RDRF set and OR flag clear); 2. Receive second frame without reading the first frame in the data register (the second frame is not received and OR flag is set); 3. Read data register SCIDRL (returns first frame and clears RDRF flag in the status register); 4. Read status register SCISR1 (returns RDRF clear and OR set). Event 3 may be at exactly the same time as event 2 or any time after. When this happens, a dummy SCIDRL read following event 4 will be required to clear the OR flag if further frames are to be received.
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Chapter 13 Serial Communication Interface (SCIV4)
13.3.2.5
SCI Status Register 2 (SCISR2)
7 6 5 4 3 2 1 0
R W Reset
0
0
0 TXPOL RXPOL 0 BRK13 0 TXDIR 0
RAF
0
0
0
0
0
= Unimplemented or Reserved
Figure 13-8. SCI Status Register 2 (SCISR2)
Read: anytime Write: anytime
Table 13-8. SCISR2 Field Descriptions
Field 4 TXPOL Description Transmit Polarity -- This bit control the polarity of the transmitted data. In NRZ format, a 1 is represented by a mark and a 0 is represented by a space for normal polarity, and the opposite for inverted polarity. In IrDA format, a 0 is represented by short high pulse in the middle of a bit time remaining idle low for a 1 for normal polarity, and a 0 is represented by short low pulse in the middle of a bit time remaining idle high for a 1 for inverted polarity. 0 Normal polarity 1 Inverted polarity Receive Polarity -- This bit control the polarity of the received data. In NRZ format, a 1 is represented by a mark and a 0 is represented by a space for normal polarity, and the opposite for inverted polarity. In IrDA format, a 0 is represented by short high pulse in the middle of a bit time remaining idle low for a 1 for normal polarity, and a 0 is represented by short low pulse in the middle of a bit time remaining idle high for a 1 for inverted polarity. 0 Normal polarity 1 Inverted polarity Break Transmit Character Length -- This bit determines whether the transmit break character is 10 or 11 bit respectively 13 or 14 bits long. The detection of a framing error is not affected by this bit. 0 Break character is 10 or 11 bit long 1 Break character is 13 or 14 bit long Transmitter Pin Data Direction in Single-Wire Mode -- This bit determines whether the TXD pin is going to be used as an input or output, in the single-wire mode of operation. This bit is only relevant in the single-wire mode of operation. 0 TXD pin to be used as an input in single-wire mode 1 TXD pin to be used as an output in single-wire mode Receiver Active Flag -- RAF is set when the receiver detects a logic 0 during the RT1 time period of the start bit search. RAF is cleared when the receiver detects an idle character. 0 No reception in progress 1 Reception in progress
3 RXPOL
2 BRK13
1 TXDIR
0 RAF
MC9S12HZ256 Data Sheet, Rev. 2.05 398 Freescale Semiconductor
Chapter 13 Serial Communication Interface (SCIV4)
13.3.2.6
SCI Data Registers (SCIDRH and SCIDRL)
7 6 5 4 3 2 1 0
R W Reset
R8 T8 0 0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 13-9. SCI Data Register High (SCIDRH)
Table 13-9. SCIDRH Field Descriptions
Field 7 R8 6 T8 Description Received Bit 8 -- R8 is the ninth data bit received when the SCI is configured for 9-bit data format (M = 1). Transmit Bit 8 -- T8 is the ninth data bit transmitted when the SCI is configured for 9-bit data format (M = 1).
7
6
5
4
3
2
1
0
R W Reset
R7 T7 0
R6 T6 0
R5 T5 0
R4 T4 0
R3 T3 0
R2 T2 0
R1 T1 0
R0 T0 0
Figure 13-10. SCI Data Register Low (SCIDRL)
Read: anytime; reading accesses SCI receive data register Write: anytime; writing accesses SCI transmit data register; writing to R8 has no effect
Table 13-10. SCIDRL Field Descriptions
Field 7:0 R[7:0] T[7:0} Description Received bits 7 through 0 -- For 9-bit or 8-bit data formats Transmit bits 7 through 0 -- For 9-bit or 8-bit formats
NOTE If the value of T8 is the same as in the previous transmission, T8 does not have to be rewritten.The same value is transmitted until T8 is rewritten In 8-bit data format, only SCI data register low (SCIDRL) needs to be accessed. When transmitting in 9-bit data format and using 8-bit write instructions, write first to SCI data register high (SCIDRH) then to SCIDRL.
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Chapter 13 Serial Communication Interface (SCIV4)
13.4
Functional Description
This subsection provides a complete functional description of the SCI block, detailing the operation of the design from the end user's perspective in a number of descriptions. Figure 13-11 shows the structure of the SCI module. The SCI allows full duplex, asynchronous, serial communication between the CPU and remote devices, including other CPUs. The SCI transmitter and receiver operate independently, although they use the same baud rate generator. The CPU monitors the status of the SCI, writes the data to be transmitted, and processes received data.
IREN SCI DATA REGISTER RXD INFRARED RECEIVE DECODER R8 Ir_RXD SCRXD RECEIVE SHIFT REGISTER RE R16XCLK RECEIVE AND WAKEUP CONTROL RWU LOOPS RSRC M BAUD RATE GENERATOR WAKE DATA FORMAT CONTROL ILT PE SBR12-SBR0 PT TE /16 TRANSMIT CONTROL LOOPS SBK RSRC T8 TRANSMIT SHIFT REGISTER SCI DATA REGISTER R16XCLK R32XCLK TNP[1:0] IREN INFRARED TRANSMIT ENCODER TXD Ir_TXD TDRE TC TCIE SCTXD TC TDRE TIE SCI Interrupt Request RIE NF FE PF RAF IDLE RDRF OR RDRF/OR ILIE IDLE
BUS CLOCK
Figure 13-11. Detailed SCI Block Diagram
MC9S12HZ256 Data Sheet, Rev. 2.05 400 Freescale Semiconductor
Chapter 13 Serial Communication Interface (SCIV4)
13.4.1
Infrared Interface Submodule
This module provides the capability of transmitting narrow pulses to an IR LED and receiving narrow pulses and transforming them to serial bits, which are sent to the SCI. The IrDA physical layer specification defines a half-duplex infrared communication link for exchange data. The full standard includes data rates up to 16 Mbits/s. This design covers only data rates between 2.4 kbits/s and 115.2 kbits/s. The infrared submodule consists of two major blocks: the transmit encoder and the receive decoder. The SCI transmits serial bits of data which are encoded by the infrared submodule to transmit a narrow pulse for every 0 bit. No pulse is transmitted for every 1 bit. When receiving data, the IR pulses should be detected using an IR photo diode and transformed to CMOS levels by the IR receive decoder (external from the MCU). The narrow pulses are then stretched by the infrared submodule to get back to a serial bit stream to be received by the SCI. The polarity of transmitted pulses and expected receive pulses can be inverted so that a direct connection can be made to external IrDA transceiver modules that uses active low pulses. The infrared submodule receives its clock sources from the SCI. One of these two clocks are selected in the infrared submodule in order to generate either 3/16, 1/16, 1/32, or 1/4 narrow pulses during transmission. The infrared block receives two clock sources from the SCI, R16XCLK, and R32XCLK, which are configured to generate the narrow pulse width during transmission. The R16XCLK and R32XCLK are internal clocks with frequencies 16 and 32 times the baud rate respectively. Both R16XCLK and R32XCLK clocks are used for transmitting data. The receive decoder uses only the R16XCLK clock.
13.4.1.1
Infrared Transmit Encoder
The infrared transmit encoder converts serial bits of data from transmit shift register to the TXD pin. A narrow pulse is transmitted for a 0 bit and no pulse for a 1 bit. The narrow pulse is sent in the middle of the bit with a duration of 1/32, 1/16, 3/16, or 1/4 of a bit time. A narrow high pulse is transmitted for a 0 bit when TXPOL is cleared, while a narrow low pulse is transmitted for a 0 bit when TXPOL is set.
13.4.1.2
Infrared Receive Decoder
The infrared receive block converts data from the RXD pin to the receive shift register. A narrow pulse is expected for each 0 received and no pulse is expected for each 1 received. A narrow high pulse is expected for a 0 bit when RXPOL is cleared, while a narrow low pulse is expected for a 0 bit when RXPOL is set. This receive decoder meets the edge jitter requirement as defined by the IrDA serial infrared physical layer specification.
13.4.2
Data Format
The SCI uses the standard NRZ mark/space data format. When Infrared is enabled, the SCI uses RZI data format where 0s are represented by light pulses and 1s remain low. See Figure 13-12.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 401
Chapter 13 Serial Communication Interface (SCIV4)
8-BIT DATA FORMAT (BIT M IN SCICR1 CLEAR) START BIT
POSSIBLE PARITY BIT BIT 6 BIT 7 STOP BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
NEXT START BIT
STANDARD SCI DATA
INFRARED SCI DATA
9-BIT DATA FORMAT (BIT M IN SCICR1 SET) START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7
POSSIBLE PARITY BIT BIT 8 STOP BIT
NEXT START BIT
STANDARD SCI DATA
INFRARED SCI DATA
Figure 13-12. SCI Data Formats
Each data character is contained in a frame that includes a start bit, eight or nine data bits, and a stop bit. Clearing the M bit in SCI control register 1 configures the SCI for 8-bit data characters. A frame with eight data bits has a total of 10 bits. Setting the M bit configures the SCI for nine-bit data characters. A frame with nine data bits has a total of 11 bits
Table 13-11. Example of 8-bit Data Formats
Start Bit 1 1 1
1
Data Bits 8 7 7
Address Bits 0 0 1
1
Parity Bits 0 1 0
Stop Bit 1 1 1
The address bit identifies the frame as an address character. See Section 13.4.5.6, "Receiver Wakeup".
When the SCI is configured for 9-bit data characters, the ninth data bit is the T8 bit in SCI data register high (SCIDRH). It remains unchanged after transmission and can be used repeatedly without rewriting it. A frame with nine data bits has a total of 11 bits.
Table 13-12. Example of 9-Bit Data Formats
Start Bit 1 1 1
1
Data Bits 9 8 8
Address Bits 0 0 11
Parity Bits 0 1 0
Stop Bit 1 1 1
The address bit identifies the frame as an address character. See Section 13.4.5.6, "Receiver Wakeup".
MC9S12HZ256 Data Sheet, Rev. 2.05 402 Freescale Semiconductor
Chapter 13 Serial Communication Interface (SCIV4)
13.4.3
Baud Rate Generation
A 13-bit modulus counter in the baud rate generator derives the baud rate for both the receiver and the transmitter. The value from 0 to 8191 written to the SBR[12:0] bits determines the module clock divisor. The SBR bits are in the SCI baud rate registers (SCIBDH and SCIBDL). The baud rate clock is synchronized with the bus clock and drives the receiver. The baud rate clock divided by 16 drives the transmitter. The receiver has an acquisition rate of 16 samples per bit time. Baud rate generation is subject to one source of error: * Integer division of the module clock may not give the exact target frequency. Table 13-13 lists some examples of achieving target baud rates with a module clock frequency of 10.2 MHz. When IREN = 0 then, SCI baud rate = SCI module clock / (16 * SCIBR[12:0])
Table 13-13. Baud Rates (Example: Module Clock = 10.2 MHz)
Bits SBR[12-0] 17 33 66 133 266 531 1062 2125 4250 5795 Receiver Clock (Hz) 600,000.0 309,090.9 154,545.5 76,691.7 38,345.9 19,209.0 9604.5 4800.0 2400.0 1760.1 Transmitter Clock (Hz) 37,500.0 19,318.2 9659.1 4793.2 2396.6 1200.6 600.3 300.0 150.0 110.0 Target Baud Rate 38,400 19,200 9600 4800 2400 1200 600 300 150 110 Error (%) 2.3 .62 .62 .14 .14 .11 .05 .00 .00 .00
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Chapter 13 Serial Communication Interface (SCIV4)
13.4.4
Transmitter
INTERNAL BUS
BUS CLOCK
BAUD DIVIDER
/ 16
SCI DATA REGISTERS
STOP
SBR12-SBR0
START
11-BIT TRANSMIT SHIFT REGISTER 8 7 6 5 4 3 2 1 0
TXPOL
SCTXD
M
H
L
MSB
PREAMBLE (ALL ONES)
LOAD FROM SCIDR
T8
LOOP CONTROL
TO RECEIVER
PE PT
PARITY GENERATION
BREAK (ALL 0s)
SHIFT ENABLE
LOOPS RSRC
TRANSMITTER CONTROL
TDRE INTERRUPT REQUEST
TDRE TIE TC TCIE
TE
SBK
TC INTERRUPT REQUEST
Figure 13-13. Transmitter Block Diagram
13.4.4.1
Transmitter Character Length
The SCI transmitter can accommodate either 8-bit or 9-bit data characters. The state of the M bit in SCI control register 1 (SCICR1) determines the length of data characters. When transmitting 9-bit data, bit T8 in SCI data register high (SCIDRH) is the ninth bit (bit 8).
13.4.4.2
Character Transmission
To transmit data, the MCU writes the data bits to the SCI data registers (SCIDRH/SCIDRL), which in turn are transferred to the transmitter shift register. The transmit shift register then shifts a frame out through the TXD pin, after it has prefaced them with a start bit and appended them with a stop bit. The SCI data registers (SCIDRH and SCIDRL) are the write-only buffers between the internal data bus and the transmit shift register. The SCI also sets a flag, the transmit data register empty flag (TDRE), every time it transfers data from the buffer (SCIDRH/L) to the transmitter shift register. The transmit driver routine may respond to this
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Chapter 13 Serial Communication Interface (SCIV4)
flag by writing another byte to the transmitter buffer (SCIDRH/SCIDRL), while the shift register is shifting out the first byte. To initiate an SCI transmission: 1. Configure the SCI: a) Select a baud rate. Write this value to the SCI baud registers (SCIBDH/L) to begin the baud rate generator. Remember that the baud rate generator is disabled when the baud rate is 0. Writing to the SCIBDH has no effect without also writing to SCIBDL. b) Write to SCICR1 to configure word length, parity, and other configuration bits (LOOPS, RSRC, M, WAKE, ILT, PE, and PT). c) Enable the transmitter, interrupts, receive, and wake up as required, by writing to the SCICR2 register bits (TIE, TCIE, RIE, ILIE, TE, RE, RWU, and SBK). A preamble or idle character will now be shifted out of the transmitter shift register. 2. Transmit procedure for each byte: a) Poll the TDRE flag by reading the SCISR1 or responding to the TDRE interrupt. Keep in mind that the TDRE bit resets to 1. b) If the TDRE flag is set, write the data to be transmitted to SCIDRH/L, where the ninth bit is written to the T8 bit in SCIDRH if the SCI is in 9-bit data format. A new transmission will not result until the TDRE flag has been cleared. 3. Repeat step 2 for each subsequent transmission. NOTE The TDRE flag is set when the shift register is loaded with the next data to be transmitted from SCIDRH/L, which happens, generally speaking, a little over half-way through the stop bit of the previous frame. Specifically, this transfer occurs 9/16ths of a bit time AFTER the start of the stop bit of the previous frame. Writing the TE bit from 0 to a 1 automatically loads the transmit shift register with a preamble of 10 logic 1s (if M = 0) or 11 logic 1s (if M = 1). After the preamble shifts out, control logic transfers the data from the SCI data register into the transmit shift register. A logic 0 start bit automatically goes into the least significant bit position of the transmit shift register. A logic 1 stop bit goes into the most significant bit position. Hardware supports odd or even parity. When parity is enabled, the most significant bit (MSB) of the data character is the parity bit. The transmit data register empty flag, TDRE, in SCI status register 1 (SCISR1) becomes set when the SCI data register transfers a byte to the transmit shift register. The TDRE flag indicates that the SCI data register can accept new data from the internal data bus. If the transmit interrupt enable bit, TIE, in SCI control register 2 (SCICR2) is also set, the TDRE flag generates a transmitter interrupt request. When the transmit shift register is not transmitting a frame, the TXD pin goes to the idle condition, logic 1. If at any time software clears the TE bit in SCI control register 2 (SCICR2), the transmitter enable signal goes low and the transmit signal goes idle.
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Chapter 13 Serial Communication Interface (SCIV4)
If software clears TE while a transmission is in progress (TC = 0), the frame in the transmit shift register continues to shift out. To avoid accidentally cutting off the last frame in a message, always wait for TDRE to go high after the last frame before clearing TE. To separate messages with preambles with minimum idle line time, use this sequence between messages: 1. Write the last byte of the first message to SCIDRH/L. 2. Wait for the TDRE flag to go high, indicating the transfer of the last frame to the transmit shift register. 3. Queue a preamble by clearing and then setting the TE bit. 4. Write the first byte of the second message to SCIDRH/L.
13.4.4.3
Break Characters
Writing a logic 1 to the send break bit, SBK, in SCI control register 2 (SCICR2) loads the transmit shift register with a break character. A break character contains all logic 0s and has no start, stop, or parity bit. Break character length depends on the M bit in SCI control register 1 (SCICR1). As long as SBK is at logic 1, transmitter logic continuously loads break characters into the transmit shift register. After software clears the SBK bit, the shift register finishes transmitting the last break character and then transmits at least one logic 1. The automatic logic 1 at the end of a break character guarantees the recognition of the start bit of the next frame. The SCI recognizes a break character when a start bit is followed by eight or nine logic 0 data bits and a logic 0 where the stop bit should be. Receiving a break character has these effects on SCI registers: * Sets the framing error flag, FE * Sets the receive data register full flag, RDRF * Clears the SCI data registers (SCIDRH/L) * May set the overrun flag, OR, noise flag, NF, parity error flag, PE, or the receiver active flag, RAF (see Section 13.3.2.4, "SCI Status Register 1 (SCISR1)" and Section 13.3.2.5, "SCI Status Register 2 (SCISR2)").
13.4.4.4
Idle Characters
An idle character (or preamble) contains all logic 1s and has no start, stop, or parity bit. Idle character length depends on the M bit in SCI control register 1 (SCICR1). The preamble is a synchronizing idle character that begins the first transmission initiated after writing the TE bit from 0 to 1. If the TE bit is cleared during a transmission, the TXD pin becomes idle after completion of the transmission in progress. Clearing and then setting the TE bit during a transmission queues an idle character to be sent after the frame currently being transmitted. NOTE When queueing an idle character, return the TE bit to logic 1 before the stop bit of the current frame shifts out through the TXD pin. Setting TE after the stop bit appears on TXD causes data previously written to the SCI data register to be lost. Toggle the TE bit for a queued idle character while the
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Chapter 13 Serial Communication Interface (SCIV4)
TDRE flag is set and immediately before writing the next byte to the SCI data register. If the TE bit is clear and the transmission is complete, the SCI is not the master of the TXD pin
13.4.5
Receiver
INTERNAL BUS
SBR12-SBR0
SCI DATA REGISTER
11-BIT RECEIVE SHIFT REGISTER 8 7 6 5 4 3 2 1 0
RXPOL SCRXD FROM TXD PIN OR TRANSMITTER LOOP CONTROL
DATA RECOVERY ALL ONES
H
RE RAF
MSB
LOOPS RSRC
FE M WAKE ILT PE PT WAKEUP LOGIC NF PE RWU
PARITY CHECKING IDLE ILIE RDRF
R8
IDLE INTERRUPT REQUEST
RDRF/OR INTERRUPT REQUEST RIE
OR
Figure 13-14. SCI Receiver Block Diagram
13.4.5.1
Receiver Character Length
The SCI receiver can accommodate either 8-bit or 9-bit data characters. The state of the M bit in SCI control register 1 (SCICR1) determines the length of data characters. When receiving 9-bit data, bit R8 in SCI data register high (SCIDRH) is the ninth bit (bit 8).
13.4.5.2
Character Reception
During an SCI reception, the receive shift register shifts a frame in from the RXD pin. The SCI data register is the read-only buffer between the internal data bus and the receive shift register. After a complete frame shifts into the receive shift register, the data portion of the frame transfers to the SCI data register. The receive data register full flag, RDRF, in SCI status register 1 (SCISR1) becomes set,
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 407
START L
STOP
BUS CLOCK
BAUD DIVIDER
Chapter 13 Serial Communication Interface (SCIV4)
indicating that the received byte can be read. If the receive interrupt enable bit, RIE, in SCI control register 2 (SCICR2) is also set, the RDRF flag generates an RDRF interrupt request.
13.4.5.3
Data Sampling
The receiver samples the RXD pin at the RT clock rate. The RT clock is an internal signal with a frequency 16 times the baud rate. To adjust for baud rate mismatch, the RT clock (see Figure 13-15) is re-synchronized: * After every start bit * After the receiver detects a data bit change from logic 1 to logic 0 (after the majority of data bit samples at RT8, RT9, and RT10 returns a valid logic 1 and the majority of the next RT8, RT9, and RT10 samples returns a valid logic 0) To locate the start bit, data recovery logic does an asynchronous search for a logic 0 preceded by three logic 1s. When the falling edge of a possible start bit occurs, the RT clock begins to count to 16.
START BIT RXD SAMPLES 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 LSB
START BIT QUALIFICATION
START BIT VERIFICATION
DATA SAMPLING
RT CLOCK RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3
RT4
RT5
RT6
RT7
RT8
RT9
RT1
RT2
RT3
RT10
RT11
RT12
RT13
RT14
RT15
RT CLOCK COUNT RESET RT CLOCK
Figure 13-15. Receiver Data Sampling
To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7. Table 13-14 summarizes the results of the start bit verification samples.
Table 13-14. Start Bit Verification
RT3, RT5, and RT7 Samples 000 001 010 011 100 101 110 111 Start Bit Verification Yes Yes Yes No Yes No No No Noise Flag 0 1 1 0 1 0 0 0
If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins.
MC9S12HZ256 Data Sheet, Rev. 2.05 408 Freescale Semiconductor
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Chapter 13 Serial Communication Interface (SCIV4)
To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 13-15 summarizes the results of the data bit samples.
Table 13-15. Data Bit Recovery
RT8, RT9, and RT10 Samples 000 001 010 011 100 101 110 111 Data Bit Determination 0 0 0 1 0 1 1 1 Noise Flag 0 1 1 1 1 1 1 0
NOTE The RT8, RT9, and RT10 samples do not affect start bit verification. If any or all of the RT8, RT9, and RT10 start bit samples are logic 1s following a successful start bit verification, the noise flag (NF) is set and the receiver assumes that the bit is a start bit (logic 0). To verify a stop bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 13-16 summarizes the results of the stop bit samples.
Table 13-16. Stop Bit Recovery
RT8, RT9, and RT10 Samples 000 001 010 011 100 101 110 111 Framing Error Flag 1 1 1 0 1 0 0 0 Noise Flag 0 1 1 1 1 1 1 0
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Chapter 13 Serial Communication Interface (SCIV4)
In Figure 13-16 the verification samples RT3 and RT5 determine that the first low detected was noise and not the beginning of a start bit. The RT clock is reset and the start bit search begins again. The noise flag is not set because the noise occurred before the start bit was found.
START BIT RXD SAMPLES 1 1 1 0 1 1 1 0 0 0 0 0 0 0 LSB
RT CLOCK RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT1 RT1 RT2
RT3
RT4
RT5
RT6
RT7
RT8
RT9
RT1
RT2 LSB RT6
RT10
RT11
RT12
RT13
RT14
RT15
RT CLOCK COUNT RESET RT CLOCK
Figure 13-16. Start Bit Search Example 1
In Figure 13-17, verification sample at RT3 is high. The RT3 sample sets the noise flag. Although the perceived bit time is misaligned, the data samples RT8, RT9, and RT10 are within the bit time and data recovery is successful.
PERCEIVED START BIT ACTUAL START BIT RXD SAMPLES 1 1 1 1 1 0 1 0 0 0 0 0
RT CLOCK RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT6
RT7
RT8
RT9
RT1
RT2
RT3
RT4
RT16
RT5
RT10
RT11
RT12
RT13
RT14
RT15
RT CLOCK COUNT RESET RT CLOCK
Figure 13-17. Start Bit Search Example 2
MC9S12HZ256 Data Sheet, Rev. 2.05 410 Freescale Semiconductor
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Chapter 13 Serial Communication Interface (SCIV4)
In Figure 13-18, a large burst of noise is perceived as the beginning of a start bit, although the test sample at RT5 is high. The RT5 sample sets the noise flag. Although this is a worst-case misalignment of perceived bit time, the data samples RT8, RT9, and RT10 are within the bit time and data recovery is successful.
PERCEIVED START BIT ACTUAL START BIT RXD SAMPLES 1 1 1 0 0 1 0 0 0 0 LSB
RT CLOCK RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8
RT9
RT1
RT2
RT3
RT4
RT5
RT6
RT7
RT8 LSB RT2
RT10
RT11
RT12
RT13
RT14
RT15
RT CLOCK COUNT RESET RT CLOCK
Figure 13-18. Start Bit Search Example 3
Figure 13-19 shows the effect of noise early in the start bit time. Although this noise does not affect proper synchronization with the start bit time, it does set the noise flag.
PERCEIVED AND ACTUAL START BIT RXD SAMPLES 1 1 1 1 1 1 1 1 1 0 1 0
RT CLOCK RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2
RT3
RT4
RT5
RT6
RT7
RT8
RT9
RT16
RT1
RT10
RT11
RT12
RT13
RT14
RT15
RT CLOCK COUNT RESET RT CLOCK
Figure 13-19. Start Bit Search Example 4
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 411
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Chapter 13 Serial Communication Interface (SCIV4)
Figure 13-20 shows a burst of noise near the beginning of the start bit that resets the RT clock. The sample after the reset is low but is not preceded by three high samples that would qualify as a falling edge. Depending on the timing of the start bit search and on the data, the frame may be missed entirely or it may set the framing error flag.
START BIT NO START BIT FOUND 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 0 0 0 0 0 0 LSB
RXD SAMPLES
RT CLOCK RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2
RT3
RT4
RT5
RT6
RT7
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT1
RT1 LSB RT2
RT CLOCK COUNT RESET RT CLOCK
Figure 13-20. Start Bit Search Example 5
In Figure 13-21, a noise burst makes the majority of data samples RT8, RT9, and RT10 high. This sets the noise flag but does not reset the RT clock. In start bits only, the RT8, RT9, and RT10 data samples are ignored.
START BIT RXD SAMPLES 1 1 1 1 1 1 1 1 1 0 0 0 0 1 0 1
RT CLOCK RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2
RT3
RT4
RT5
RT6
RT7
RT8
RT9
RT1
RT10
RT11
RT12
RT13
RT14
RT15
RT CLOCK COUNT RESET RT CLOCK
Figure 13-21. Start Bit Search Example 6
13.4.5.4
Framing Errors
If the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming frame, it sets the framing error flag, FE, in SCI status register 1 (SCISR1). A break character also sets the FE flag because a break character has no stop bit. The FE flag is set at the same time that the RDRF flag is set.
MC9S12HZ256 Data Sheet, Rev. 2.05 412 Freescale Semiconductor
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Chapter 13 Serial Communication Interface (SCIV4)
13.4.5.5
Baud Rate Tolerance
A transmitting device may be operating at a baud rate below or above the receiver baud rate. Accumulated bit time misalignment can cause one of the three stop bit data samples (RT8, RT9, and RT10) to fall outside the actual stop bit. A noise error will occur if the RT8, RT9, and RT10 samples are not all the same logical values. A framing error will occur if the receiver clock is misaligned in such a way that the majority of the RT8, RT9, and RT10 stop bit samples are a logic 0. As the receiver samples an incoming frame, it re-synchronizes the RT clock on any valid falling edge within the frame. Re synchronization within frames will correct a misalignment between transmitter bit times and receiver bit times. 13.4.5.5.1 Slow Data Tolerance
Figure 13-22 shows how much a slow received frame can be misaligned without causing a noise error or a framing error. The slow stop bit begins at RT8 instead of RT1 but arrives in time for the stop bit data samples at RT8, RT9, and RT10.
MSB STOP
RECEIVER RT CLOCK RT10 RT11 RT12 RT13 RT14 RT15 RT16 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9
DATA SAMPLES
Figure 13-22. Slow Data
Let's take RTr as receiver RT clock and RTt as transmitter RT clock. For an 8-bit data character, it takes the receiver 9 bit times x 16 RTr cycles +7 RTr cycles =151 RTr cycles to start data sampling of the stop bit. With the misaligned character shown in Figure 13-22, the receiver counts 151 RTr cycles at the point when the count of the transmitting device is 9 bit times x 16 RTt cycles = 144 RTt cycles. The maximum percent difference between the receiver count and the transmitter count of a slow 8-bit data character with no errors is: ((151 - 144) / 151) x 100 = 4.63% For a 9-bit data character, it takes the receiver 10 bit times x 16 RTr cycles + 7 RTr cycles = 167 RTr cycles to start data sampling of the stop bit. With the misaligned character shown in Figure 13-22, the receiver counts 167 RTr cycles at the point when the count of the transmitting device is 10 bit times x 16 RTt cycles = 160 RTt cycles. The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit character with no errors is: ((167 - 160) / 167) X 100 = 4.19%
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 413
Chapter 13 Serial Communication Interface (SCIV4)
13.4.5.5.2
Fast Data Tolerance
Figure 13-23 shows how much a fast received frame can be misaligned. The fast stop bit ends at RT10 instead of RT16 but continues to be sampled at RT8, RT9, and RT10.
STOP
IDLE OR NEXT FRAME
RECEIVER RT CLOCK RT10 RT11 RT12 RT13 RT14 RT15 RT16 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9
DATA SAMPLES
Figure 13-23. Fast Data
For an 8-bit data character, it takes the receiver 9 bit times x 16 RTr cycles + 10 RTr cycles = 154 RTr cycles to finish data sampling of the stop bit. With the misaligned character shown in Figure 13-23, the receiver counts 154 RTr cycles at the point when the count of the transmitting device is 10 bit times x 16 RTt cycles = 160 RTt cycles. The maximum percent difference between the receiver count and the transmitter count of a fast 8-bit character with no errors is: ((160 - 154) / 160) x 100 = 3.75% For a 9-bit data character, it takes the receiver 10 bit times x 16 RTr cycles + 10 RTr cycles = 170 RTr cycles to finish data sampling of the stop bit. With the misaligned character shown in Figure 13-23, the receiver counts 170 RTr cycles at the point when the count of the transmitting device is 11 bit times x 16 RTt cycles = 176 RTt cycles. The maximum percent difference between the receiver count and the transmitter count of a fast 9-bit character with no errors is: ((176 - 170) / 176) x 100 = 3.40%
13.4.5.6
Receiver Wakeup
To enable the SCI to ignore transmissions intended only for other receivers in multiple-receiver systems, the receiver can be put into a standby state. Setting the receiver wakeup bit, RWU, in SCI control register 2 (SCICR2) puts the receiver into standby state during which receiver interrupts are disabled.The SCI will continue to load the receive data into the SCIDRH/L registers, but it will not set the RDRF flag. The transmitting device can address messages to selected receivers by including addressing information in the initial frame or frames of each message. The WAKE bit in SCI control register 1 (SCICR1) determines how the SCI is brought out of the standby state to process an incoming message. The WAKE bit enables either idle line wakeup or address mark wakeup.
MC9S12HZ256 Data Sheet, Rev. 2.05 414 Freescale Semiconductor
Chapter 13 Serial Communication Interface (SCIV4)
13.4.5.6.1
Idle Input Line Wakeup (WAKE = 0)
In this wakeup method, an idle condition on the RXD pin clears the RWU bit and wakes up the SCI. The initial frame or frames of every message contain addressing information. All receivers evaluate the addressing information, and receivers for which the message is addressed process the frames that follow. Any receiver for which a message is not addressed can set its RWU bit and return to the standby state. The RWU bit remains set and the receiver remains on standby until another idle character appears on the RXD pin. Idle line wakeup requires that messages be separated by at least one idle character and that no message contains idle characters. The idle character that wakes a receiver does not set the receiver idle bit, IDLE, or the receive data register full flag, RDRF. The idle line type bit, ILT, determines whether the receiver begins counting logic 1s as idle character bits after the start bit or after the stop bit. ILT is in SCI control register 1 (SCICR1). 13.4.5.6.2 Address Mark Wakeup (WAKE = 1)
In this wakeup method, a logic 1 in the most significant bit (MSB) position of a frame clears the RWU bit and wakes up the SCI. The logic 1 in the MSB position marks a frame as an address frame that contains addressing information. All receivers evaluate the addressing information, and the receivers for which the message is addressed process the frames that follow. Any receiver for which a message is not addressed can set its RWU bit and return to the standby state. The RWU bit remains set and the receiver remains on standby until another address frame appears on the RXD pin. The logic 1 MSB of an address frame clears the receiver's RWU bit before the stop bit is received and sets the RDRF flag. Address mark wakeup allows messages to contain idle characters but requires that the MSB be reserved for use in address frames. NOTE With the WAKE bit clear, setting the RWU bit after the RXD pin has been idle can cause the receiver to wake up immediately.
13.4.6
Single-Wire Operation
Normally, the SCI uses two pins for transmitting and receiving. In single-wire operation, the RXD pin is disconnected from the SCI. The SCI uses the TXD pin for both receiving and transmitting.
TRANSMITTER TXD
RECEIVER
RXD
Figure 13-24. Single-Wire Operation (LOOPS = 1, RSRC = 1)
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Chapter 13 Serial Communication Interface (SCIV4)
Enable single-wire operation by setting the LOOPS bit and the receiver source bit, RSRC, in SCI control register 1 (SCICR1). Setting the LOOPS bit disables the path from the RXD pin to the receiver. Setting the RSRC bit connects the TXD pin to the receiver. Both the transmitter and receiver must be enabled (TE = 1 and RE = 1).The TXDIR bit (SCISR2[1]) determines whether the TXD pin is going to be used as an input (TXDIR = 0) or an output (TXDIR = 1) in this mode of operation. NOTE In single-wire operation data from the TXD pin is inverted if RXPOL is set.
13.4.7
Loop Operation
In loop operation the transmitter output goes to the receiver input. The RXD pin is disconnected from the SCI
.
TRANSMITTER
TXD
RECEIVER
RXD
Figure 13-25. Loop Operation (LOOPS = 1, RSRC = 0)
Enable loop operation by setting the LOOPS bit and clearing the RSRC bit in SCI control register 1 (SCICR1). Setting the LOOPS bit disables the path from the RXD pin to the receiver. Clearing the RSRC bit connects the transmitter output to the receiver input. Both the transmitter and receiver must be enabled (TE = 1 and RE = 1). NOTE In loop operation data from the transmitter is not recognized by the receiver if RXPOL and TXPOL are not the same.
13.5
Interrupts
This section describes the interrupt originated by the SCI block.The MCU must service the interrupt requests. Table 13-17 lists the five interrupt sources of the SCI.
Table 13-17. SCI Interrupt Sources
Interrupt TDRE Source SCISR1[7] Local Enable TIE Description Active high level. Indicates that a byte was transferred from SCIDRH/L to the transmit shift register. Active high level. Indicates that a transmit is complete. Active high level. The RDRF interrupt indicates that received data is available in the SCI data register. Active high level. This interrupt indicates that an overrun condition has occurred.
TC RDRF
SCISR1[6] SCISR1[5]
TCIE RIE
OR
SCISR1[3]
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Chapter 13 Serial Communication Interface (SCIV4)
Table 13-17. SCI Interrupt Sources
IDLE SCISR1[4] ILIE Active high level. Indicates that receiver input has become idle.
13.5.1
Description of Interrupt Operation
The SCI only originates interrupt requests. The following is a description of how the SCI makes a request and how the MCU should acknowledge that request. The interrupt vector offset and interrupt number are chip dependent. The SCI only has a single interrupt line (SCI interrupt signal, active high operation) and all the following interrupts, when generated, are ORed together and issued through that port.
13.5.1.1
TDRE Description
The TDRE interrupt is set high by the SCI when the transmit shift register receives a byte from the SCI data register. A TDRE interrupt indicates that the transmit data register (SCIDRH/L) is empty and that a new byte can be written to the SCIDRH/L for transmission.Clear TDRE by reading SCI status register 1 with TDRE set and then writing to SCI data register low (SCIDRL).
13.5.1.2
TC Description
The TC interrupt is set by the SCI when a transmission has been completed.A TC interrupt indicates that there is no transmission in progress. TC is set high when the TDRE flag is set and no data, preamble, or break character is being transmitted. When TC is set, the TXD pin becomes idle (logic 1). Clear TC by reading SCI status register 1 (SCISR1) with TC set and then writing to SCI data register low (SCIDRL).TC is cleared automatically when data, preamble, or break is queued and ready to be sent.
13.5.1.3
RDRF Description
The RDRF interrupt is set when the data in the receive shift register transfers to the SCI data register. A RDRF interrupt indicates that the received data has been transferred to the SCI data register and that the byte can now be read by the MCU. The RDRF interrupt is cleared by reading the SCI status register one (SCISR1) and then reading SCI data register low (SCIDRL).
13.5.1.4
OR Description
The OR interrupt is set when software fails to read the SCI data register before the receive shift register receives the next frame. The newly acquired data in the shift register will be lost in this case, but the data already in the SCI data registers is not affected. The OR interrupt is cleared by reading the SCI status register one (SCISR1) and then reading SCI data register low (SCIDRL).
13.5.1.5
IDLE Description
The IDLE interrupt is set when 10 consecutive logic 1s (if M = 0) or 11 consecutive logic 1s (if M = 1) appear on the receiver input. After the IDLE is cleared, a valid frame must again set the RDRF flag before an idle condition can set the IDLE flag. Clear IDLE by reading SCI status register 1 (SCISR1) with IDLE set and then reading SCI data register low (SCIDRL).
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13.5.2
Recovery from Wait Mode
The SCI interrupt request can be used to bring the CPU out of wait mode.
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Chapter 14 Serial Peripheral Interface (SPIV3)
14.1 Introduction
The SPI module allows a duplex, synchronous, serial communication between the MCU and peripheral devices. Software can poll the SPI status flags or the SPI operation can be interrupt driven.
14.1.1
Features
The SPI includes these distinctive features: * Master mode and slave mode * Bidirectional mode * Slave select output * Mode fault error flag with CPU interrupt capability * Double-buffered data register * Serial clock with programmable polarity and phase * Control of SPI operation during wait mode
14.1.2
Modes of Operation
The SPI functions in three modes, run, wait, and stop. * Run Mode This is the basic mode of operation. * Wait Mode SPI operation in wait mode is a configurable low power mode, controlled by the SPISWAI bit located in the SPICR2 register. In wait mode, if the SPISWAI bit is clear, the SPI operates like in Run Mode. If the SPISWAI bit is set, the SPI goes into a power conservative state, with the SPI clock generation turned off. If the SPI is configured as a master, any transmission in progress stops, but is resumed after CPU goes into Run Mode. If the SPI is configured as a slave, reception and transmission of a byte continues, so that the slave stays synchronized to the master. * Stop Mode The SPI is inactive in stop mode for reduced power consumption. If the SPI is configured as a master, any transmission in progress stops, but is resumed after CPU goes into run mode. If the SPI is configured as a slave, reception and transmission of a byte continues, so that the slave stays synchronized to the master. This is a high level description only, detailed descriptions of operating modes are contained in Section 14.4, "Functional Description."
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14.1.3
Block Diagram
Figure 14-1 gives an overview on the SPI architecture. The main parts of the SPI are status, control, and data registers, shifter logic, baud rate generator, master/slave control logic, and port control logic.
SPI 2 SPI Control Register 1 BIDIROE SPI Control Register 2 2 SPC0 SPI Status Register SPIF SPI Interrupt Request Baud Rate Generator Counter Bus Clock Prescaler Clock Select SPPR 3 SPR 3 Shifter SPI Baud Rate Register LSBFE=1 8 SPI Data Register 8 LSBFE=0 MSB LSBFE=0 LSBFE=1 LSBFE=0 LSBFE=1 LSB data out data in Baud Rate Shift Clock Sample Clock MODF SPTEF Slave Control
CPOL
CPHA
MOSI
Interrupt Control
Phase + SCK in Slave Baud Rate Polarity Control Master Baud Rate Phase + SCK out Polarity Control Master Control
Port Control Logic
SCK
SS
Figure 14-1. SPI Block Diagram
14.2
External Signal Description
This section lists the name and description of all ports including inputs and outputs that do, or may, connect off chip. The SPI module has a total of four external pins.
14.2.1
MOSI -- Master Out/Slave In Pin
This pin is used to transmit data out of the SPI module when it is configured as a master and receive data when it is configured as slave.
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Chapter 14 Serial Peripheral Interface (SPIV3)
14.2.2
MISO -- Master In/Slave Out Pin
This pin is used to transmit data out of the SPI module when it is configured as a slave and receive data when it is configured as master.
14.2.3
SS -- Slave Select Pin
This pin is used to output the select signal from the SPI module to another peripheral with which a data transfer is to take place when its configured as a master and its used as an input to receive the slave select signal when the SPI is configured as slave.
14.2.4
SCK -- Serial Clock Pin
This pin is used to output the clock with respect to which the SPI transfers data or receive clock in case of slave.
14.3
Memory Map and Register Definition
This section provides a detailed description of address space and registers used by the SPI. The memory map for the SPI is given below in Table 14-1. The address listed for each register is the sum of a base address and an address offset. The base address is defined at the SoC level and the address offset is defined at the module level. Reads from the reserved bits return zeros and writes to the reserved bits have no effect.
14.3.1
Module Memory Map
Table 14-1. SPI Memory Map
Address 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 SPI Control Register 1 (SPICR1) SPI Control Register 2 (SPICR2) SPI Baud Rate Register (SPIBR) SPI Status Register (SPISR) Reserved SPI Data Register (SPIDR) Reserved Reserved Use Access R/W R/W1 R/W1 R2 -- 2,3 R/W -- 2,3 -- 2,3
Certain bits are non-writable. Writes to this register are ignored. 3 Reading from this register returns all zeros.
2
1
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14.3.2
Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order.
Name SPICR1 R W R W R W R W R W R W R W R W = Unimplemented or Reserved Bit 7 6 5 4 3 2 2 Bit 0 SPIF 0 SPPR2 0 SPPR1 SPTEF 7 SPIE 0 6 SPE 0 5 SPTIE 0 4 MSTR 3 CPOL 2 CPHA 0 1 SSOE 0 LSBFE
SPICR2
MODFEN
BIDIROE 0
SPISWAI
SPC0
SPIBR
SPPR0 MODF
SPR2 0
SPR1 0
SPR0 0
SPISR
0
Reserved
SPIDR
Reserved
Reserved
Figure 14-2. SPI Register Summary
14.3.2.1
SPI Control Register 1 (SPICR1)
7 6 5 4 3 2 1 0
R SPIE W Reset 0 0 0 0 0 1 0 0 SPE SPTIE MSTR CPOL CPHA SSOE LSBFE
Figure 14-3. SPI Control Register 1 (SPICR1)
Read: anytime Write: anytime
MC9S12HZ256 Data Sheet, Rev. 2.05 422 Freescale Semiconductor
Chapter 14 Serial Peripheral Interface (SPIV3)
Table 14-2. SPICR1 Field Descriptions
Field 7 SPIE 6 SPE Description SPI Interrupt Enable Bit -- This bit enables SPI interrupt requests, if SPIF or MODF status flag is set. 0 SPI interrupts disabled. 1 SPI interrupts enabled. SPI System Enable Bit -- This bit enables the SPI system and dedicates the SPI port pins to SPI system functions. If SPE is cleared, SPI is disabled and forced into idle state, status bits in SPISR register are reset. 0 SPI disabled (lower power consumption). 1 SPI enabled, port pins are dedicated to SPI functions. SPI Transmit Interrupt Enable -- This bit enables SPI interrupt requests, if SPTEF flag is set. 0 SPTEF interrupt disabled. 1 SPTEF interrupt enabled. SPI Master/Slave Mode Select Bit -- This bit selects, if the SPI operates in master or slave mode. Switching the SPI from master to slave or vice versa forces the SPI system into idle state. 0 SPI is in slave mode 1 SPI is in master mode SPI Clock Polarity Bit -- This bit selects an inverted or non-inverted SPI clock. To transmit data between SPI modules, the SPI modules must have identical CPOL values. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. 0 Active-high clocks selected. In idle state SCK is low. 1 Active-low clocks selected. In idle state SCK is high. SPI Clock Phase Bit -- This bit is used to select the SPI clock format. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. 0 Sampling of data occurs at odd edges (1,3,5,...,15) of the SCK clock 1 Sampling of data occurs at even edges (2,4,6,...,16) of the SCK clock Slave Select Output Enable -- The SS output feature is enabled only in master mode, if MODFEN is set, by asserting the SSOE as shown in Table 14-3. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. LSB-First Enable -- This bit does not affect the position of the MSB and LSB in the data register. Reads and writes of the data register always have the MSB in bit 7. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. 0 Data is transferred most significant bit first. 1 Data is transferred least significant bit first.
5 SPTIE 4 MSTR
3 CPOL
2 CPHA
1 SSOE 0 LSBFE
Table 14-3. SS Input / Output Selection
MODFEN 0 0 1 1 SSOE 0 1 0 1 Master Mode SS not used by SPI SS not used by SPI SS input with MODF feature SS is slave select output Slave Mode SS input SS input SS input SS input
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14.3.2.2
SPI Control Register 2 (SPICR2)
7 6 5 4 3 2 1 0
R W Reset
0
0
0 MODFEN BIDIROE 0
0 SPISWAI 0 0 SPC0 0
0
0
0
0
= Unimplemented or Reserved
Figure 14-4. SPI Control Register 2 (SPICR2)
Read: anytime Write: anytime; writes to the reserved bits have no effect
Table 14-4. SPICR2 Field Descriptions
Field 4 MODFEN Description Mode Fault Enable Bit -- This bit allows the MODF failure being detected. If the SPI is in master mode and MODFEN is cleared, then the SS port pin is not used by the SPI. In slave mode, the SS is available only as an input regardless of the value of MODFEN. For an overview on the impact of the MODFEN bit on the SS port pin configuration refer to Table 14-3. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. 0 SS port pin is not used by the SPI 1 SS port pin with MODF feature Output Enable in the Bidirectional Mode of Operation -- This bit controls the MOSI and MISO output buffer of the SPI, when in bidirectional mode of operation (SPC0 is set). In master mode this bit controls the output buffer of the MOSI port, in slave mode it controls the output buffer of the MISO port. In master mode, with SPC0 set, a change of this bit will abort a transmission in progress and force the SPI into idle state. 0 Output buffer disabled 1 Output buffer enabled SPI Stop in Wait Mode Bit -- This bit is used for power conservation while in wait mode. 0 SPI clock operates normally in wait mode 1 Stop SPI clock generation when in wait mode Serial Pin Control Bit 0 -- This bit enables bidirectional pin configurations as shown in Table 14-5. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state
3 BIDIROE
1 SPISWAI 0 SPC0
Table 14-5. Bidirectional Pin Configurations
Pin Mode SPC0 BIDIROE MISO MOSI
Master Mode of Operation Normal Bidirectional 0 1 X 0 1 Slave Mode of Operation Normal Bidirectional 0 1 X 0 1 Slave Out Slave In Slave I/O Slave In MOSI not used by SPI Master In MISO not used by SPI Master Out Master In Master I/O
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Chapter 14 Serial Peripheral Interface (SPIV3)
14.3.2.3
SPI Baud Rate Register (SPIBR)
7 6 5 4 3 2 1 0
R W Reset
0 SPPR2 0 0 SPPR1 0 SPPR0 0
0 SPR2 0 0 SPR1 0 SPR0 0
= Unimplemented or Reserved
Figure 14-5. SPI Baud Rate Register (SPIBR)
Read: anytime Write: anytime; writes to the reserved bits have no effect
Table 14-6. SPIBR Field Descriptions
Field 6:4 SPPR[2:0] 2:0 SPR[2:0} Description SPI Baud Rate Preselection Bits -- These bits specify the SPI baud rates as shown in Table 14-7. In master mode, a change of these bits will abort a transmission in progress and force the SPI system into idle state. SPI Baud Rate Selection Bits -- These bits specify the SPI baud rates as shown in Table 14-7. In master mode, a change of these bits will abort a transmission in progress and force the SPI system into idle state.
The baud rate divisor equation is as follows:
BaudRateDivisor = ( SPPR + 1 ) * 2 ( SPR + 1 )
The baud rate can be calculated with the following equation:
Baud Rate = BusClock BaudRateDivisor
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Table 14-7. Example SPI Baud Rate Selection (25 MHz Bus Clock)
SPPR2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 SPPR1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 SPPR0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 SPR2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 SPR1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 SPR0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Baud Rate Divisor 2 4 8 16 32 64 128 256 4 8 16 32 64 128 256 512 6 12 24 48 96 192 384 768 8 16 32 64 128 256 512 1024 10 20 40 80 160 320 640 Baud Rate 12.5 MHz 6.25 MHz 3.125 MHz 1.5625 MHz 781.25 kHz 390.63 kHz 195.31 kHz 97.66 kHz 6.25 MHz 3.125 MHz 1.5625 MHz 781.25 kHz 390.63 kHz 195.31 kHz 97.66 kHz 48.83 kHz 4.16667 MHz 2.08333 MHz 1.04167 MHz 520.83 kHz 260.42 kHz 130.21 kHz 65.10 kHz 32.55 kHz 3.125 MHz 1.5625 MHz 781.25 kHz 390.63 kHz 195.31 kHz 97.66 kHz 48.83 kHz 24.41 kHz 2.5 MHz 1.25 MHz 625 kHz 312.5 kHz 156.25 kHz 78.13 kHz 39.06 kHz
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Chapter 14 Serial Peripheral Interface (SPIV3)
Table 14-7. Example SPI Baud Rate Selection (25 MHz Bus Clock) (continued)
SPPR2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 SPPR1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 SPPR0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SPR2 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SPR1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SPR0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Baud Rate Divisor 1280 12 24 48 96 192 384 768 1536 14 28 56 112 224 448 896 1792 16 32 64 128 256 512 1024 2048 Baud Rate 19.53 kHz 2.08333 MHz 1.04167 MHz 520.83 kHz 260.42 kHz 130.21 kHz 65.10 kHz 32.55 kHz 16.28 kHz 1.78571 MHz 892.86 kHz 446.43 kHz 223.21 kHz 111.61 kHz 55.80 kHz 27.90 kHz 13.95 kHz 1.5625 MHz 781.25 kHz 390.63 kHz 195.31 kHz 97.66 kHz 48.83 kHz 24.41 kHz 12.21 kHz
NOTE In slave mode of SPI S-clock speed DIV2 is not supported.
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14.3.2.4
SPI Status Register (SPISR)
7 6 5 4 3 2 1 0
R W Reset
SPIF
0
SPTEF
MODF
0
0
0
0
0
0
1
0
0
0
0
0
= Unimplemented or Reserved
Figure 14-6. SPI Status Register (SPISR)
Read: anytime Write: has no effect
Table 14-8. SPISR Field Descriptions
Field 7 SPIF Description SPIF Interrupt Flag -- This bit is set after a received data byte has been transferred into the SPI Data Register. This bit is cleared by reading the SPISR register (with SPIF set) followed by a read access to the SPI Data Register. 0 Transfer not yet complete 1 New data copied to SPIDR SPI Transmit Empty Interrupt Flag -- If set, this bit indicates that the transmit data register is empty. To clear this bit and place data into the transmit data register, SPISR has to be read with SPTEF = 1, followed by a write to SPIDR. Any write to the SPI Data Register without reading SPTEF = 1, is effectively ignored. 0 SPI Data register not empty 1 SPI Data register empty Mode Fault Flag -- This bit is set if the SS input becomes low while the SPI is configured as a master and mode fault detection is enabled, MODFEN bit of SPICR2 register is set. Refer to MODFEN bit description in Section 14.3.2.2, "SPI Control Register 2 (SPICR2)." The flag is cleared automatically by a read of the SPI Status Register (with MODF set) followed by a write to the SPI Control Register 1. 0 Mode fault has not occurred. 1 Mode fault has occurred.
5 SPTEF
4 MODF
14.3.2.5
SPI Data Register (SPIDR)
7 6 5 4 3 2 1 0
R Bit 7 W Reset 0 0 0 0 0 0 0 0 6 5 4 3 2 2 Bit 0
= Unimplemented or Reserved
Figure 14-7. SPI Data Register (SPIDR)
Read: anytime; normally read only after SPIF is set Write: anytime
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Chapter 14 Serial Peripheral Interface (SPIV3)
The SPI Data Register is both the input and output register for SPI data. A write to this register allows a data byte to be queued and transmitted. For a SPI configured as a master, a queued data byte is transmitted immediately after the previous transmission has completed. The SPI Transmitter Empty Flag SPTEF in the SPISR register indicates when the SPI Data Register is ready to accept new data. Reading the data can occur anytime from after the SPIF is set to before the end of the next transfer. If the SPIF is not serviced by the end of the successive transfers, those data bytes are lost and the data within the SPIDR retains the first byte until SPIF is serviced.
14.4
Functional Description
The SPI module allows a duplex, synchronous, serial communication between the MCU and peripheral devices. Software can poll the SPI status flags or SPI operation can be interrupt driven. The SPI system is enabled by setting the SPI enable (SPE) bit in SPI Control Register 1. While SPE bit is set, the four associated SPI port pins are dedicated to the SPI function as: * Slave select (SS) * Serial clock (SCK) * Master out/slave in (MOSI) * Master in/slave out (MISO) The main element of the SPI system is the SPI Data Register. The 8-bit data register in the master and the 8-bit data register in the slave are linked by the MOSI and MISO pins to form a distributed 16-bit register. When a data transfer operation is performed, this 16-bit register is serially shifted eight bit positions by the S-clock from the master, so data is exchanged between the master and the slave. Data written to the master SPI Data Register becomes the output data for the slave, and data read from the master SPI Data Register after a transfer operation is the input data from the slave. A read of SPISR with SPTEF = 1 followed by a write to SPIDR puts data into the transmit data register. When a transfer is complete, received data is moved into the receive data register. Data may be read from this double-buffered system any time before the next transfer has completed. This 8-bit data register acts as the SPI receive data register for reads and as the SPI transmit data register for writes. A single SPI register address is used for reading data from the read data buffer and for writing data to the transmit data register. The clock phase control bit (CPHA) and a clock polarity control bit (CPOL) in the SPI Control Register 1 (SPICR1) select one of four possible clock formats to be used by the SPI system. The CPOL bit simply selects a non-inverted or inverted clock. The CPHA bit is used to accommodate two fundamentally different protocols by sampling data on odd numbered SCK edges or on even numbered SCK edges (see Section 14.4.3, "Transmission Formats"). The SPI can be configured to operate as a master or as a slave. When the MSTR bit in SPI Control Register1 is set, master mode is selected, when the MSTR bit is clear, slave mode is selected.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 429
Chapter 14 Serial Peripheral Interface (SPIV3)
14.4.1
Master Mode
The SPI operates in master mode when the MSTR bit is set. Only a master SPI module can initiate transmissions. A transmission begins by writing to the master SPI Data Register. If the shift register is empty, the byte immediately transfers to the shift register. The byte begins shifting out on the MOSI pin under the control of the serial clock. * S-clock The SPR2, SPR1, and SPR0 baud rate selection bits in conjunction with the SPPR2, SPPR1, and SPPR0 baud rate preselection bits in the SPI Baud Rate register control the baud rate generator and determine the speed of the transmission. The SCK pin is the SPI clock output. Through the SCK pin, the baud rate generator of the master controls the shift register of the slave peripheral. * MOSI and MISO Pins In master mode, the function of the serial data output pin (MOSI) and the serial data input pin (MISO) is determined by the SPC0 and BIDIROE control bits. * SS Pin If MODFEN and SSOE bit are set, the SS pin is configured as slave select output. The SS output becomes low during each transmission and is high when the SPI is in idle state. If MODFEN is set and SSOE is cleared, the SS pin is configured as input for detecting mode fault error. If the SS input becomes low this indicates a mode fault error where another master tries to drive the MOSI and SCK lines. In this case, the SPI immediately switches to slave mode, by clearing the MSTR bit and also disables the slave output buffer MISO (or SISO in bidirectional mode). So the result is that all outputs are disabled and SCK, MOSI and MISO are inputs. If a transmission is in progress when the mode fault occurs, the transmission is aborted and the SPI is forced into idle state. This mode fault error also sets the mode fault (MODF) flag in the SPI Status Register (SPISR). If the SPI interrupt enable bit (SPIE) is set when the MODF flag gets set, then an SPI interrupt sequence is also requested. When a write to the SPI Data Register in the master occurs, there is a half SCK-cycle delay. After the delay, SCK is started within the master. The rest of the transfer operation differs slightly, depending on the clock format specified by the SPI clock phase bit, CPHA, in SPI Control Register 1 (see Section 14.4.3, "Transmission Formats"). NOTE A change of the bits CPOL, CPHA, SSOE, LSBFE, MODFEN, SPC0, BIDIROE with SPC0 set, SPPR2-SPPR0 and SPR2-SPR0 in master mode will abort a transmission in progress and force the SPI into idle state. The remote slave cannot detect this, therefore the master has to ensure that the remote slave is set back to idle state.
MC9S12HZ256 Data Sheet, Rev. 2.05 430 Freescale Semiconductor
Chapter 14 Serial Peripheral Interface (SPIV3)
14.4.2
Slave Mode
The SPI operates in slave mode when the MSTR bit in SPI Control Register1 is clear. * SCK Clock In slave mode, SCK is the SPI clock input from the master. * MISO and MOSI Pins In slave mode, the function of the serial data output pin (MISO) and serial data input pin (MOSI) is determined by the SPC0 bit and BIDIROE bit in SPI Control Register 2. * SS Pin The SS pin is the slave select input. Before a data transmission occurs, the SS pin of the slave SPI must be low. SS must remain low until the transmission is complete. If SS goes high, the SPI is forced into idle state. The SS input also controls the serial data output pin, if SS is high (not selected), the serial data output pin is high impedance, and, if SS is low the first bit in the SPI Data Register is driven out of the serial data output pin. Also, if the slave is not selected (SS is high), then the SCK input is ignored and no internal shifting of the SPI shift register takes place. Although the SPI is capable of duplex operation, some SPI peripherals are capable of only receiving SPI data in a slave mode. For these simpler devices, there is no serial data out pin. NOTE When peripherals with duplex capability are used, take care not to simultaneously enable two receivers whose serial outputs drive the same system slave's serial data output line. As long as no more than one slave device drives the system slave's serial data output line, it is possible for several slaves to receive the same transmission from a master, although the master would not receive return information from all of the receiving slaves. If the CPHA bit in SPI Control Register 1 is clear, odd numbered edges on the SCK input cause the data at the serial data input pin to be latched. Even numbered edges cause the value previously latched from the serial data input pin to shift into the LSB or MSB of the SPI shift register, depending on the LSBFE bit. If the CPHA bit is set, even numbered edges on the SCK input cause the data at the serial data input pin to be latched. Odd numbered edges cause the value previously latched from the serial data input pin to shift into the LSB or MSB of the SPI shift register, depending on the LSBFE bit. When CPHA is set, the first edge is used to get the first data bit onto the serial data output pin. When CPHA is clear and the SS input is low (slave selected), the first bit of the SPI data is driven out of the serial data output pin. After the eighth shift, the transfer is considered complete and the received data is transferred into the SPI Data Register. To indicate transfer is complete, the SPIF flag in the SPI Status Register is set. NOTE A change of the bits CPOL, CPHA, SSOE, LSBFE, MODFEN, SPC0 and BIDIROE with SPC0 set in slave mode will corrupt a transmission in progress and has to be avoided.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 431
Chapter 14 Serial Peripheral Interface (SPIV3)
14.4.3
Transmission Formats
During an SPI transmission, data is transmitted (shifted out serially) and received (shifted in serially) simultaneously. The serial clock (SCK) synchronizes shifting and sampling of the information on the two serial data lines. A slave select line allows selection of an individual slave SPI device, slave devices that are not selected do not interfere with SPI bus activities. Optionally, on a master SPI device, the slave select line can be used to indicate multiple-master bus contention.
MASTER SPI MISO MOSI SCK BAUD RATE GENERATOR SS MISO MOSI SCK SS SLAVE SPI
SHIFT REGISTER
SHIFT REGISTER
VDD
Figure 14-8. Master/Slave Transfer Block Diagram
14.4.3.1
Clock Phase and Polarity Controls
Using two bits in the SPI Control Register1, software selects one of four combinations of serial clock phase and polarity. The CPOL clock polarity control bit specifies an active high or low clock and has no significant effect on the transmission format. The CPHA clock phase control bit selects one of two fundamentally different transmission formats. Clock phase and polarity should be identical for the master SPI device and the communicating slave device. In some cases, the phase and polarity are changed between transmissions to allow a master device to communicate with peripheral slaves having different requirements.
14.4.3.2
CPHA = 0 Transfer Format
The first edge on the SCK line is used to clock the first data bit of the slave into the master and the first data bit of the master into the slave. In some peripherals, the first bit of the slave's data is available at the slave's data out pin as soon as the slave is selected. In this format, the first SCK edge is issued a half cycle after SS has become low. A half SCK cycle later, the second edge appears on the SCK line. When this second edge occurs, the value previously latched from the serial data input pin is shifted into the LSB or MSB of the shift register, depending on LSBFE bit. After this second edge, the next bit of the SPI master data is transmitted out of the serial data output pin of the master to the serial input pin on the slave. This process continues for a total of 16 edges on the SCK line, with data being latched on odd numbered edges and shifted on even numbered edges.
MC9S12HZ256 Data Sheet, Rev. 2.05 432 Freescale Semiconductor
Chapter 14 Serial Peripheral Interface (SPIV3)
Data reception is double buffered. Data is shifted serially into the SPI shift register during the transfer and is transferred to the parallel SPI Data Register after the last bit is shifted in. After the 16th (last) SCK edge: * Data that was previously in the master SPI Data Register should now be in the slave data register and the data that was in the slave data register should be in the master. * The SPIF flag in the SPI Status Register is set indicating that the transfer is complete. Figure 14-9 is a timing diagram of an SPI transfer where CPHA = 0. SCK waveforms are shown for CPOL = 0 and CPOL = 1. The diagram may be interpreted as a master or slave timing diagram because the SCK, MISO, and MOSI pins are connected directly between the master and the slave. The MISO signal is the output from the slave and the MOSI signal is the output from the master. The SS pin of the master must be either high or reconfigured as a general-purpose output not affecting the SPI.
End of Idle State SCK Edge Nr. SCK (CPOL = 0) SCK (CPOL = 1) 1 2 Begin 3 4 5 6 Transfer 7 8 9 10 11 12 End 13 14 15 16 Begin of Idle State
CHANGE O MOSI pin CHANGE O MISO pin SEL SS (O) Master only SEL SS (I) tL MSB first (LSBFE = 0): MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 LSB first (LSBFE = 1): LSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 tL = Minimum leading time before the first SCK edge tT = Minimum trailing time after the last SCK edge tI = Minimum idling time between transfers (minimum SS high time) tL, tT, and tI are guaranteed for the master mode and required for the slave mode. Bit 1 Bit 6 tT tI tL
LSB Minimum 1/2 SCK for tT, tl, tL MSB
Figure 14-9. SPI Clock Format 0 (CPHA = 0)
In slave mode, if the SS line is not deasserted between the successive transmissions then the content of the SPI Data Register is not transmitted, instead the last received byte is transmitted. If the SS line is deasserted for at least minimum idle time (half SCK cycle) between successive transmissions then the content of the SPI Data Register is transmitted.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 433
If next transfer begins here
SAMPLE I MOSI/MISO
Chapter 14 Serial Peripheral Interface (SPIV3)
In master mode, with slave select output enabled the SS line is always deasserted and reasserted between successive transfers for at least minimum idle time.
14.4.3.3
CPHA = 1 Transfer Format
Some peripherals require the first SCK edge before the first data bit becomes available at the data out pin, the second edge clocks data into the system. In this format, the first SCK edge is issued by setting the CPHA bit at the beginning of the 8-cycle transfer operation. The first edge of SCK occurs immediately after the half SCK clock cycle synchronization delay. This first edge commands the slave to transfer its first data bit to the serial data input pin of the master. A half SCK cycle later, the second edge appears on the SCK pin. This is the latching edge for both the master and slave. When the third edge occurs, the value previously latched from the serial data input pin is shifted into the LSB or MSB of the SPI shift register, depending on LSBFE bit. After this edge, the next bit of the master data is coupled out of the serial data output pin of the master to the serial input pin on the slave. This process continues for a total of 16 edges on the SCK line with data being latched on even numbered edges and shifting taking place on odd numbered edges. Data reception is double buffered, data is serially shifted into the SPI shift register during the transfer and is transferred to the parallel SPI Data Register after the last bit is shifted in. After the 16th SCK edge: * Data that was previously in the SPI Data Register of the master is now in the data register of the slave, and data that was in the data register of the slave is in the master. * The SPIF flag bit in SPISR is set indicating that the transfer is complete. Figure 14-10 shows two clocking variations for CPHA = 1. The diagram may be interpreted as a master or slave timing diagram because the SCK, MISO, and MOSI pins are connected directly between the master and the slave. The MISO signal is the output from the slave, and the MOSI signal is the output from the master. The SS line is the slave select input to the slave. The SS pin of the master must be either high or reconfigured as a general-purpose output not affecting the SPI. The SS line can remain active low between successive transfers (can be tied low at all times). This format is sometimes preferred in systems having a single fixed master and a single slave that drive the MISO data line. * Back-to-back transfers in master mode In master mode, if a transmission has completed and a new data byte is available in the SPI Data Register, this byte is send out immediately without a trailing and minimum idle time. The SPI interrupt request flag (SPIF) is common to both the master and slave modes. SPIF gets set one half SCK cycle after the last SCK edge.
MC9S12HZ256 Data Sheet, Rev. 2.05 434 Freescale Semiconductor
Chapter 14 Serial Peripheral Interface (SPIV3)
End of Idle State SCK Edge Nr. SCK (CPOL = 0) SCK (CPOL = 1) 1 2 3
Begin 4 5 6 7
Transfer 8 9 10 11 12
End 13 14 15 16
Begin of Idle State
CHANGE O MOSI pin CHANGE O MISO pin SEL SS (O) Master only SEL SS (I) tL MSB first (LSBFE = 0): LSB first (LSBFE = 1): tT tI tL
MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB Minimum 1/2 SCK for tT, tl, tL LSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB tL = Minimum leading time before the first SCK edge, not required for back to back transfers tT = Minimum trailing time after the last SCK edge tI = Minimum idling time between transfers (minimum SS high time), not required for back to back transfers
Figure 14-10. SPI Clock Format 1 (CPHA = 1)
14.4.4
SPI Baud Rate Generation
Baud rate generation consists of a series of divider stages. Six bits in the SPI Baud Rate register (SPPR2, SPPR1, SPPR0, SPR2, SPR1, and SPR0) determine the divisor to the SPI module clock which results in the SPI baud rate. The SPI clock rate is determined by the product of the value in the baud rate preselection bits (SPPR2-SPPR0) and the value in the baud rate selection bits (SPR2-SPR0). The module clock divisor equation is shown in Figure 14-11 When all bits are clear (the default condition), the SPI module clock is divided by 2. When the selection bits (SPR2-SPR0) are 001 and the preselection bits (SPPR2-SPPR0) are 000, the module clock divisor becomes 4. When the selection bits are 010, the module clock divisor becomes 8 etc. When the preselection bits are 001, the divisor determined by the selection bits is multiplied by 2. When the preselection bits are 010, the divisor is multiplied by 3, etc. See Table 14-7 for baud rate calculations for all bit conditions, based on a 25-MHz bus clock. The two sets of selects allows the clock to be divided by a non-power of two to achieve other baud rates such as divide by 6, divide by 10, etc.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 435
If next transfer begins here
SAMPLE I MOSI/MISO
Chapter 14 Serial Peripheral Interface (SPIV3)
The baud rate generator is activated only when the SPI is in the master mode and a serial transfer is taking place. In the other cases, the divider is disabled to decrease IDD current.
BaudRateDivisor = ( SPPR + 1 ) * 2 ( SPR + 1 )
Figure 14-11. Baud Rate Divisor Equation
14.4.5
14.4.5.1
Special Features
SS Output
The SS output feature automatically drives the SS pin low during transmission to select external devices and drives it high during idle to deselect external devices. When SS output is selected, the SS output pin is connected to the SS input pin of the external device. The SS output is available only in master mode during normal SPI operation by asserting SSOE and MODFEN bit as shown in Table 14-3. The mode fault feature is disabled while SS output is enabled. NOTE Care must be taken when using the SS output feature in a multimaster system because the mode fault feature is not available for detecting system errors between masters.
14.4.5.2
Bidirectional Mode (MOSI or MISO)
The bidirectional mode is selected when the SPC0 bit is set in SPI Control Register 2 (see Table 14-9). In this mode, the SPI uses only one serial data pin for the interface with external device(s). The MSTR bit decides which pin to use. The MOSI pin becomes the serial data I/O (MOMI) pin for the master mode, and the MISO pin becomes serial data I/O (SISO) pin for the slave mode. The MISO pin in master mode and MOSI pin in slave mode are not used by the SPI.
Table 14-9. Normal Mode and Bidirectional Mode
When SPE = 1 Master Mode MSTR = 1
Serial Out MOSI
Slave Mode MSTR = 0
Serial In SPI MISO Serial Out MISO MOSI
Normal Mode SPC0 = 0
SPI Serial In
Serial Out
MOMI BIDIROE
Serial In BIDIROE SPI Serial Out SISO
Bidirectional Mode SPC0 = 1
SPI Serial In
MC9S12HZ256 Data Sheet, Rev. 2.05 436 Freescale Semiconductor
Chapter 14 Serial Peripheral Interface (SPIV3)
The direction of each serial I/O pin depends on the BIDIROE bit. If the pin is configured as an output, serial data from the shift register is driven out on the pin. The same pin is also the serial input to the shift register. The SCK is output for the master mode and input for the slave mode. The SS is the input or output for the master mode, and it is always the input for the slave mode. The bidirectional mode does not affect SCK and SS functions. NOTE In bidirectional master mode, with mode fault enabled, both data pins MISO and MOSI can be occupied by the SPI, though MOSI is normally used for transmissions in bidirectional mode and MISO is not used by the SPI. If a mode fault occurs, the SPI is automatically switched to slave mode, in this case MISO becomes occupied by the SPI and MOSI is not used. This has to be considered, if the MISO pin is used for other purpose.
14.4.6
Error Conditions
The SPI has one error condition: * Mode fault error
14.4.6.1
Mode Fault Error
If the SS input becomes low while the SPI is configured as a master, it indicates a system error where more than one master may be trying to drive the MOSI and SCK lines simultaneously. This condition is not permitted in normal operation, the MODF bit in the SPI Status Register is set automatically provided the MODFEN bit is set. In the special case where the SPI is in master mode and MODFEN bit is cleared, the SS pin is not used by the SPI. In this special case, the mode fault error function is inhibited and MODF remains cleared. In case the SPI system is configured as a slave, the SS pin is a dedicated input pin. Mode fault error doesn't occur in slave mode. If a mode fault error occurs the SPI is switched to slave mode, with the exception that the slave output buffer is disabled. So SCK, MISO and MOSI pins are forced to be high impedance inputs to avoid any possibility of conflict with another output driver. A transmission in progress is aborted and the SPI is forced into idle state. If the mode fault error occurs in the bidirectional mode for a SPI system configured in master mode, output enable of the MOMI (MOSI in bidirectional mode) is cleared if it was set. No mode fault error occurs in the bidirectional mode for SPI system configured in slave mode. The mode fault flag is cleared automatically by a read of the SPI Status Register (with MODF set) followed by a write to SPI Control Register 1. If the mode fault flag is cleared, the SPI becomes a normal master or slave again.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 437
Chapter 14 Serial Peripheral Interface (SPIV3)
14.4.7
Operation in Run Mode
In run mode with the SPI system enable (SPE) bit in the SPI control register clear, the SPI system is in a low-power, disabled state. SPI registers remain accessible, but clocks to the core of this module are disabled.
14.4.8
Operation in Wait Mode
SPI operation in wait mode depends upon the state of the SPISWAI bit in SPI Control Register 2. * If SPISWAI is clear, the SPI operates normally when the CPU is in wait mode * If SPISWAI is set, SPI clock generation ceases and the SPI module enters a power conservation state when the CPU is in wait mode. -- If SPISWAI is set and the SPI is configured for master, any transmission and reception in progress stops at wait mode entry. The transmission and reception resumes when the SPI exits wait mode. -- If SPISWAI is set and the SPI is configured as a slave, any transmission and reception in progress continues if the SCK continues to be driven from the master. This keeps the slave synchronized to the master and the SCK. If the master transmits several bytes while the slave is in wait mode, the slave will continue to send out bytes consistent with the operation mode at the start of wait mode (i.e. If the slave is currently sending its SPIDR to the master, it will continue to send the same byte. Else if the slave is currently sending the last received byte from the master, it will continue to send each previous master byte). NOTE Care must be taken when expecting data from a master while the slave is in wait or stop mode. Even though the shift register will continue to operate, the rest of the SPI is shut down (i.e. a SPIF interrupt will not be generated until exiting stop or wait mode). Also, the byte from the shift register will not be copied into the SPIDR register until after the slave SPI has exited wait or stop mode. A SPIF flag and SPIDR copy is only generated if wait mode is entered or exited during a tranmission. If the slave enters wait mode in idle mode and exits wait mode in idle mode, neither a SPIF nor a SPIDR copy will occur.
14.4.9
Operation in Stop Mode
Stop mode is dependent on the system. The SPI enters stop mode when the module clock is disabled (held high or low). If the SPI is in master mode and exchanging data when the CPU enters stop mode, the transmission is frozen until the CPU exits stop mode. After stop, data to and from the external SPI is exchanged correctly. In slave mode, the SPI will stay synchronized with the master. The stop mode is not dependent on the SPISWAI bit.
MC9S12HZ256 Data Sheet, Rev. 2.05 438 Freescale Semiconductor
Chapter 14 Serial Peripheral Interface (SPIV3)
14.5
Reset
The reset values of registers and signals are described in the Memory Map and Registers section (see Section 14.3, "Memory Map and Register Definition") which details the registers and their bit-fields. * If a data transmission occurs in slave mode after reset without a write to SPIDR, it will transmit garbage, or the byte last received from the master before the reset. * Reading from the SPIDR after reset will always read a byte of zeros.
14.6
Interrupts
The SPI only originates interrupt requests when SPI is enabled (SPE bit in SPICR1 set). The following is a description of how the SPI makes a request and how the MCU should acknowledge that request. The interrupt vector offset and interrupt priority are chip dependent. The interrupt flags MODF, SPIF and SPTEF are logically ORed to generate an interrupt request.
14.6.1
MODF
MODF occurs when the master detects an error on the SS pin. The master SPI must be configured for the MODF feature (see Table 14-3). After MODF is set, the current transfer is aborted and the following bit is changed: * MSTR = 0, The master bit in SPICR1 resets. The MODF interrupt is reflected in the status register MODF flag. Clearing the flag will also clear the interrupt. This interrupt will stay active while the MODF flag is set. MODF has an automatic clearing process which is described in Section 14.3.2.4, "SPI Status Register (SPISR)."
14.6.2
SPIF
SPIF occurs when new data has been received and copied to the SPI Data Register. After SPIF is set, it does not clear until it is serviced. SPIF has an automatic clearing process which is described in Section 14.3.2.4, "SPI Status Register (SPISR)." In the event that the SPIF is not serviced before the end of the next transfer (i.e. SPIF remains active throughout another transfer), the latter transfers will be ignored and no new data will be copied into the SPIDR.
14.6.3
SPTEF
SPTEF occurs when the SPI Data Register is ready to accept new data. After SPTEF is set, it does not clear until it is serviced. SPTEF has an automatic clearing process which is described in Section 14.3.2.4, "SPI Status Register (SPISR)."
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 439
Chapter 14 Serial Peripheral Interface (SPIV3)
MC9S12HZ256 Data Sheet, Rev. 2.05 440 Freescale Semiconductor
Chapter 15 Pulse-Width Modulator (PWM8B6CV1)
15.1 Introduction
The pulse width modulation (PWM) definition is based on the HC12 PWM definitions. The PWM8B6C module contains the basic features from the HC11 with some of the enhancements incorporated on the HC12, that is center aligned output mode and four available clock sources. The PWM8B6C module has six channels with independent control of left and center aligned outputs on each channel. Each of the six PWM channels has a programmable period and duty cycle as well as a dedicated counter. A flexible clock select scheme allows a total of four different clock sources to be used with the counters. Each of the modulators can create independent continuous waveforms with software-selectable duty rates from 0% to 100%. The PWM outputs can be programmed as left aligned outputs or center aligned outputs
15.1.1
* * * * * * * * * *
Features
Six independent PWM channels with programmable period and duty cycle Dedicated counter for each PWM channel Programmable PWM enable/disable for each channel Software selection of PWM duty pulse polarity for each channel Period and duty cycle are double buffered. Change takes effect when the end of the effective period is reached (PWM counter reaches 0) or when the channel is disabled. Programmable center or left aligned outputs on individual channels Six 8-bit channel or three 16-bit channel PWM resolution Four clock sources (A, B, SA, and SB) provide for a wide range of frequencies. Programmable clock select logic Emergency shutdown
15.1.2
Modes of Operation
There is a software programmable option for low power consumption in wait mode that disables the input clock to the prescaler. In freeze mode there is a software programmable option to disable the input clock to the prescaler. This is useful for emulation.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 441
Chapter 15 Pulse-Width Modulator (PWM8B6CV1)
15.1.3
Block Diagram
PWM8B6C
PWM Channels Channel 5 Bus Clock Clock Select PWM Clock Period and Duty Counter PWM5
Channel 4 Period and Duty Control Channel 3 Period and Duty Counter Counter
PWM4
PWM3
Channel 2 Enable Period and Duty Counter
PWM2
Polarity
Channel 1 Period and Duty Counter
PWM1
Alignment
Channel 0 Period and Duty Counter
PWM0
Figure 15-1. PWM8B6C Block Diagram
15.2
External Signal Description
The PWM8B6C module has a total of six external pins.
15.2.1
PWM5 -- Pulse Width Modulator Channel 5 Pin
This pin serves as waveform output of PWM channel 5 and as an input for the emergency shutdown feature.
15.2.2
PWM4 -- Pulse Width Modulator Channel 4 Pin
This pin serves as waveform output of PWM channel 4.
15.2.3
PWM3 -- Pulse Width Modulator Channel 3 Pin
This pin serves as waveform output of PWM channel 3.
MC9S12HZ256 Data Sheet, Rev. 2.05 442 Freescale Semiconductor
Chapter 15 Pulse-Width Modulator (PWM8B6CV1)
15.2.4
PWM2 -- Pulse Width Modulator Channel 2 Pin
This pin serves as waveform output of PWM channel 2.
15.2.5
PWM1 -- Pulse Width Modulator Channel 1 Pin
This pin serves as waveform output of PWM channel 1.
15.2.6
PWM0 -- Pulse Width Modulator Channel 0 Pin
This pin serves as waveform output of PWM channel 0.
15.3
Memory Map and Register Definition
This subsection describes in detail all the registers and register bits in the PWM8B6C module. The special-purpose registers and register bit functions that would not normally be made available to device end users, such as factory test control registers and reserved registers are clearly identified by means of shading the appropriate portions of address maps and register diagrams. Notes explaining the reasons for restricting access to the registers and functions are also explained in the individual register descriptions.
15.3.1
Module Memory Map
The following paragraphs describe the content of the registers in the PWM8B6C module. The base address of the PWM8B6C module is determined at the MCU level when the MCU is defined. The register decode map is fixed and begins at the first address of the module address offset. Table 15-1 shows the registers associated with the PWM and their relative offset from the base address. The register detail description follows the order in which they appear in the register map. Reserved bits within a register will always read as 0 and the write will be unimplemented. Unimplemented functions are indicated by shading the bit. Table 15-1 shows the memory map for the PWM8B6C module. NOTE Register address = base address + address offset, where the base address is defined at the MCU level and the address offset is defined at the module level.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 443
Chapter 15 Pulse-Width Modulator (PWM8B6CV1)
Table 15-1. PWM8B6C Memory Map
Address Offset 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C 0x000D 0x000E 0x000F 0x0010 0x0011 0x0012 0x0013 0x0014 0x0015 0x0016 0x0017 0x0018 0x0019 0x001A 0x001B 0x001C 0x001D 0x001E
1 2
Register PWM Enable Register (PWME) PWM Polarity Register (PWMPOL) PWM Clock Select Register (PWMCLK) PWM Prescale Clock Select Register (PWMPRCLK) PWM Center Align Enable Register (PWMCAE) PWM Control Register (PWMCTL) PWM Test Register (PWMTST)
1 2
Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
PWM Prescale Counter Register (PWMPRSC) PWM Scale A Register (PWMSCLA) PWM Scale B Register (PWMSCLB) PWM Scale A Counter Register PWM Scale B Counter Register
(PWMSCNTA)3 (PWMSCNTB)4
PWM Channel 0 Counter Register (PWMCNT0) PWM Channel 1 Counter Register (PWMCNT1) PWM Channel 2 Counter Register (PWMCNT2) PWM Channel 3 Counter Register (PWMCNT3) PWM Channel 4 Counter Register (PWMCNT4) PWM Channel 5 Counter Register (PWMCNT5) PWM Channel 0 Period Register (PWMPER0) PWM Channel 1 Period Register (PWMPER1) PWM Channel 2 Period Register (PWMPER2) PWM Channel 3 Period Register (PWMPER3) PWM Channel 4 Period Register (PWMPER4) PWM Channel 5 Period Register (PWMPER5) PWM Channel 0 Duty Register (PWMDTY0) PWM Channel 1 Duty Register (PWMDTY1) PWM Channel 2 Duty Register (PWMDTY2) PWM Channel 3 Duty Register (PWMDTY3) PWM Channel 4 Duty Register (PWMDTY4) PWM Channel 5 Duty Register (PWMDTY5) PWM Shutdown Register (PWMSDN)
PWMTST is intended for factory test purposes only. PWMPRSC is intended for factory test purposes only. 3 PWMSCNTA is intended for factory test purposes only. 4 PWMSCNTB is intended for factory test purposes only.
MC9S12HZ256 Data Sheet, Rev. 2.05 444 Freescale Semiconductor
Chapter 15 Pulse-Width Modulator (PWM8B6CV1)
15.3.2
Register Descriptions
The following paragraphs describe in detail all the registers and register bits in the PWM8B6C module.
Register Name PWME R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit 7 0 6 0 5 PWME5 4 PWME4 3 PWME3 2 PWME2 1 PWME1 Bit 0 PWME0
PWMPOL
0
0
PPOL5
PPOL4
PPOL3
PPOL2
PPOL1
PPOL0
PWMCLK
0
0
PCLK5
PCLK4
PCLK3 0
PCLK2
PCLK1
PCLK0
PWMPRCLK
0
PCKB2 0
PCKB1
PCKB0
PCKA2
PCKA1
PCKA0
PWMCAE
0
CAE5
CAE4
CAE2
CAE2
CAE1 0
CAE0 0
PWMCTL
0
CON45 0
CON23 0
CON01 0
PSWAI 0
PFRZ 0
PWMTST
0
0
0
PWMPRSC
0
0
0
0
0
0
0
0
PWMSCLA
Bit 7
6
5
4
3
2
1
Bit 0
PWMSCLB
Bit 7 0
6 0
5 0
4 0
3 0
2 0
1 0
Bit 0 0
PWMSCNTA
PWMSCNTB
0
0
0
0
0
0
0
0
PWMCNT0
Bit 7 0 Bit 7 0 Bit 7 0
6 0 6 0 6 0
5 0 5 0 5 0
4 0 4 0 4 0
3 0 3 0 3 0
2 0 2 0 2 0
1 0 1 0 1 0
Bit 0 0 Bit 0 0 Bit 0 0
PWMCNT1
PWMCNT2
= Unimplemented or Reserved
Figure 15-2. PWM Register Summary
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 445
Chapter 15 Pulse-Width Modulator (PWM8B6CV1)
Register Name PWMCNT3 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W
Bit 7 Bit 7 0 Bit 7 0 Bit 7 0 Bit 7
6 6 0 6 0 6 0 6
5 5 0 5 0 5 0 5
4 4 0 4 0 4 0 4
3 3 0 3 0 3 0 3
2 2 0 2 0 2 0 2
1 1 0 1 0 1 0 1
Bit 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0
PWMCNT4
PWMCNT5
PWMPER0
PWMPER1
Bit 7
6
5
4
3
2
1
Bit 0
PWMPER2
Bit 7
6
5
4
3
2
1
Bit 0
PWMPER3
Bit 7
6
5
4
3
2
1
Bit 0
PWMPER4
Bit 7
6
5
4
3
2
1
Bit 0
PWMPER5
Bit 7
6
5
4
3
2
1
Bit 0
PWMDTY0
Bit 7
6
5
4
3
2
1
Bit 0
PWMPER1
Bit 7
6
5
4
3
2
1
Bit 0
PWMPER2
Bit 7
6
5
4
3
2
1
Bit 0
PWMPER3
Bit 7
6
5
4
3
2
1
Bit 0
PWMPER4
Bit 7
6
5
4
3
2
1
Bit 0
PWMPER5
Bit 7
6
5 0 PWMRSTRT
4
3 0
2 PWM5IN
1
Bit 0
PWMSDB
PWMIF
PWMIE
PWMLVL
PWM5INL PWM5ENA
= Unimplemented or Reserved
Figure 15-2. PWM Register Summary (continued)
MC9S12HZ256 Data Sheet, Rev. 2.05 446 Freescale Semiconductor
Chapter 15 Pulse-Width Modulator (PWM8B6CV1)
15.3.2.1
PWM Enable Register (PWME)
Each PWM channel has an enable bit (PWMEx) to start its waveform output. When any of the PWMEx bits are set (PWMEx = 1), the associated PWM output is enabled immediately. However, the actual PWM waveform is not available on the associated PWM output until its clock source begins its next cycle due to the synchronization of PWMEx and the clock source. NOTE The first PWM cycle after enabling the channel can be irregular. An exception to this is when channels are concatenated. After concatenated mode is enabled (CONxx bits set in PWMCTL register), enabling/disabling the corresponding 16-bit PWM channel is controlled by the low-order PWMEx bit. In this case, the high-order bytes PWMEx bits have no effect and their corresponding PWM output lines are disabled. While in run mode, if all six PWM channels are disabled (PWME5-PWME0 = 0), the prescaler counter shuts off for power savings.
7 6 5 4 3 2 1 0
R W Reset
0
0 PWME5 PWME4 0 PWME3 0 PWME2 0 PWME1 0 PWME0 0
0
0
0
= Unimplemented or Reserved
Figure 15-3. PWM Enable Register (PWME)
Read: anytime Write: anytime
Table 15-2. PWME Field Descriptions
Field 5 PWME5 Description Pulse Width Channel 5 Enable 0 Pulse width channel 5 is disabled. 1 Pulse width channel 5 is enabled. The pulse modulated signal becomes available at PWM,output bit 5 when its clock source begins its next cycle. Pulse Width Channel 4 Enable 0 Pulse width channel 4 is disabled. 1 Pulse width channel 4 is enabled. The pulse modulated signal becomes available at PWM, output bit 4 when its clock source begins its next cycle. If CON45 = 1, then bit has no effect and PWM output line 4 is disabled. Pulse Width Channel 3 Enable 0 Pulse width channel 3 is disabled. 1 Pulse width channel 3 is enabled. The pulse modulated signal becomes available at PWM, output bit 3 when its clock source begins its next cycle. Pulse Width Channel 2 Enable 0 Pulse width channel 2 is disabled. 1 Pulse width channel 2 is enabled. The pulse modulated signal becomes available at PWM, output bit 2 when its clock source begins its next cycle. If CON23 = 1, then bit has no effect and PWM output line 2 is disabled.
4 PWME4
3 PWME3
2 PWME2
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 447
Chapter 15 Pulse-Width Modulator (PWM8B6CV1)
Table 15-2. PWME Field Descriptions (continued)
Field 1 PWME1 Description Pulse Width Channel 1 Enable 0 Pulse width channel 1 is disabled. 1 Pulse width channel 1 is enabled. The pulse modulated signal becomes available at PWM, output bit 1 when its clock source begins its next cycle. Pulse Width Channel 0 Enable 0 Pulse width channel 0 is disabled. 1 Pulse width channel 0 is enabled. The pulse modulated signal becomes available at PWM, output bit 0 when its clock source begins its next cycle. If CON01 = 1, then bit has no effect and PWM output line 0 is disabled.
0 PWME0
15.3.2.2
PWM Polarity Register (PWMPOL)
The starting polarity of each PWM channel waveform is determined by the associated PPOLx bit in the PWMPOL register. If the polarity bit is 1, the PWM channel output is high at the beginning of the cycle and then goes low when the duty count is reached. Conversely, if the polarity bit is 0 the output starts low and then goes high when the duty count is reached.
7 6 5 4 3 2 1 0
R W Reset
0
0 PPOL5 PPOL4 0 PPOL3 0 PPOL2 0 PPOL1 0 PPOL0 0
0
0
0
= Unimplemented or Reserved
Figure 15-4. PWM Polarity Register (PWMPOL)
Read: anytime Write: anytime NOTE PPOLx register bits can be written anytime. If the polarity is changed while a PWM signal is being generated, a truncated or stretched pulse can occur during the transition
Table 15-3. PWMPOL Field Descriptions
Field 5 PPOL5 4 PPOL4 3 PPOL3 Description Pulse Width Channel 5 Polarity 0 PWM channel 5 output is low at the beginning of the period, then goes high when the duty count is reached. 1 PWM channel 5 output is high at the beginning of the period, then goes low when the duty count is reached. Pulse Width Channel 4 Polarity 0 PWM channel 4 output is low at the beginning of the period, then goes high when the duty count is reached. 1 PWM channel 4 output is high at the beginning of the period, then goes low when the duty count is reached. Pulse Width Channel 3 Polarity 0 PWM channel 3 output is low at the beginning of the period, then goes high when the duty count is reached. 1 PWM channel 3 output is high at the beginning of the period, then goes low when the duty count is reached.
MC9S12HZ256 Data Sheet, Rev. 2.05 448 Freescale Semiconductor
Chapter 15 Pulse-Width Modulator (PWM8B6CV1)
Table 15-3. PWMPOL Field Descriptions (continued)
Field 2 PPOL2 1 PPOL1 0 PPOL0 Description Pulse Width Channel 2 Polarity 0 PWM channel 2 output is low at the beginning of the period, then goes high when the duty count is reached. 1 PWM channel 2 output is high at the beginning of the period, then goes low when the duty count is reached. Pulse Width Channel 1 Polarity 0 PWM channel 1 output is low at the beginning of the period, then goes high when the duty count is reached. 1 PWM channel 1 output is high at the beginning of the period, then goes low when the duty count is reached. Pulse Width Channel 0 Polarity 0 PWM channel 0 output is low at the beginning of the period, then goes high when the duty count is reached 1 PWM channel 0 output is high at the beginning of the period, then goes low when the duty count is reached.
15.3.2.3
PWM Clock Select Register (PWMCLK)
Each PWM channel has a choice of two clocks to use as the clock source for that channel as described below.
7 6 5 4 3 2 1 0
R W Reset
0
0 PCLK5 PCLK4 0 PCLK3 0 PCLK2 0 PCLK1 0 PCLK0 0
0
0
0
= Unimplemented or Reserved
Figure 15-5. PWM Clock Select Register (PWMCLK)
Read: anytime Write: anytime NOTE Register bits PCLK0 to PCLK5 can be written anytime. If a clock select is changed while a PWM signal is being generated, a truncated or stretched pulse can occur during the transition.
Table 15-4. PWMCLK Field Descriptions
Field 5 PCLK5 4 PCLK4 3 PCLK3 Description Pulse Width Channel 5 Clock Select 0 Clock A is the clock source for PWM channel 5. 1 Clock SA is the clock source for PWM channel 5. Pulse Width Channel 4 Clock Select 0 Clock A is the clock source for PWM channel 4. 1 Clock SA is the clock source for PWM channel 4. Pulse Width Channel 3 Clock Select 0 Clock B is the clock source for PWM channel 3. 1 Clock SB is the clock source for PWM channel 3.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 449
Chapter 15 Pulse-Width Modulator (PWM8B6CV1)
Table 15-4. PWMCLK Field Descriptions (continued)
Field 2 PCLK2 1 PCLK1 0 PCLK0 Description Pulse Width Channel 2 Clock Select 0 Clock B is the clock source for PWM channel 2. 1 Clock SB is the clock source for PWM channel 2. Pulse Width Channel 1 Clock Select 0 Clock A is the clock source for PWM channel 1. 1 Clock SA is the clock source for PWM channel 1. Pulse Width Channel 0 Clock Select 0 Clock A is the clock source for PWM channel 0. 1 Clock SA is the clock source for PWM channel 0.
15.3.2.4
PWM Prescale Clock Select Register (PWMPRCLK)
This register selects the prescale clock source for clocks A and B independently.
7 6 5 4 3 2 1 0
R W Reset
0 PCKB2 0 0 PCKB1 0 PCKB0 0
0 PCKA2 0 0 PCKA1 0 PCKA0 0
= Unimplemented or Reserved
Figure 15-6. PWM Prescaler Clock Select Register (PWMPRCLK)
Read: anytime Write: anytime NOTE PCKB2-PCKB0 and PCKA2-PCKA0 register bits can be written anytime. If the clock prescale is changed while a PWM signal is being generated, a truncated or stretched pulse can occur during the transition.
Table 15-5. PWMPRCLK Field Descriptions
Field 6:5 PCKB[2:0] 2:0 PCKA[2:0] Description Prescaler Select for Clock B -- Clock B is 1 of two clock sources which can be used for channels 2 or 3. These three bits determine the rate of clock B, as shown in Table 15-6. Prescaler Select for Clock A -- Clock A is 1 of two clock sources which can be used for channels 0, 1, 4, or 5. These three bits determine the rate of clock A, as shown in Table 15-7.
MC9S12HZ256 Data Sheet, Rev. 2.05 450 Freescale Semiconductor
Chapter 15 Pulse-Width Modulator (PWM8B6CV1)
Table 15-6. Clock B Prescaler Selects
PCKB2 0 0 0 0 1 1 1 1 PCKB1 0 0 1 1 0 0 1 1 PCKB0 0 1 0 1 0 1 0 1 Value of Clock B Bus Clock Bus Clock / 2 Bus Clock / 4 Bus Clock / 8 Bus Clock / 16 Bus Clock / 32 Bus Clock / 64 Bus Clock / 128
Table 15-7. Clock A Prescaler Selects
PCKA2 0 0 0 0 1 1 1 1 PCKA1 0 0 1 1 0 0 1 1 PCKA0 0 1 0 1 0 1 0 1 Value of Clock A Bus Clock Bus Clock / 2 Bus Clock / 4 Bus Clock / 8 Bus Clock / 16 Bus Clock / 32 Bus Clock / 64 Bus Clock / 128
15.3.2.5
PWM Center Align Enable Register (PWMCAE)
The PWMCAE register contains six control bits for the selection of center aligned outputs or left aligned outputs for each PWM channel. If the CAEx bit is set to a 1, the corresponding PWM output will be center aligned. If the CAEx bit is cleared, the corresponding PWM output will be left aligned. Reference Section 15.4.2.5, "Left Aligned Outputs," and Section 15.4.2.6, "Center Aligned Outputs," for a more detailed description of the PWM output modes.
7 6 5 4 3 2 1 0
R W Reset
0
0 CAE5 CAE4 0 CAE3 0 CAE2 0 CAE1 0 CAE0 0
0
0
0
= Unimplemented or Reserved
Figure 15-7. PWM Center Align Enable Register (PWMCAE)
Read: anytime Write: anytime NOTE Write these bits only when the corresponding channel is disabled.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 451
Chapter 15 Pulse-Width Modulator (PWM8B6CV1)
Table 15-8. PWMCAE Field Descriptions
Field 5 CAE5 4 CAE4 3 CAE3 2 CAE2 1 CAE1 0 CAE0 Description Center Aligned Output Mode on Channel 5 0 Channel 5 operates in left aligned output mode. 1 Channel 5 operates in center aligned output mode. Center Aligned Output Mode on Channel 4 0 Channel 4 operates in left aligned output mode. 1 Channel 4 operates in center aligned output mode. Center Aligned Output Mode on Channel 3 1 Channel 3 operates in left aligned output mode. 1 Channel 3 operates in center aligned output mode. Center Aligned Output Mode on Channel 2 0 Channel 2 operates in left aligned output mode. 1 Channel 2 operates in center aligned output mode. Center Aligned Output Mode on Channel 1 0 Channel 1 operates in left aligned output mode. 1 Channel 1 operates in center aligned output mode. Center Aligned Output Mode on Channel 0 0 Channel 0 operates in left aligned output mode. 1 Channel 0 operates in center aligned output mode.
15.3.2.6
PWM Control Register (PWMCTL)
The PWMCTL register provides for various control of the PWM module.
7 6 5 4 3 2 1 0
R W Reset
0 CON45 0 0 CON23 0 CON01 0 PSWAI 0 PFRZ 0
0
0
0
0
= Unimplemented or Reserved
Figure 15-8. PWM Control Register (PWMCTL)
Read: anytime Write: anytime There are three control bits for concatenation, each of which is used to concatenate a pair of PWM channels into one 16-bit channel. When channels 4 and 5 are concatenated, channel 4 registers become the high-order bytes of the double-byte channel. When channels 2 and 3 are concatenated, channel 2 registers become the high-order bytes of the double-byte channel. When channels 0 and 1 are concatenated, channel 0 registers become the high-order bytes of the double-byte channel. Reference Section 15.4.2.7, "PWM 16-Bit Functions," for a more detailed description of the concatenation PWM function.
MC9S12HZ256 Data Sheet, Rev. 2.05 452 Freescale Semiconductor
Chapter 15 Pulse-Width Modulator (PWM8B6CV1)
NOTE Change these bits only when both corresponding channels are disabled.
Table 15-9. PWMCTL Field Descriptions
Field 6 CON45 Description Concatenate Channels 4 and 5 0 Channels 4 and 5 are separate 8-bit PWMs. 1 Channels 4 and 5 are concatenated to create one 16-bit PWM channel. Channel 4 becomes the high-order byte and channel 5 becomes the low-order byte. Channel 5 output pin is used as the output for this 16-bit PWM (bit 5 of port PWMP). Channel 5 clock select control bit determines the clock source, channel 5 polarity bit determines the polarity, channel 5 enable bit enables the output and channel 5 center aligned enable bit determines the output mode. Concatenate Channels 2 and 3 0 Channels 2 and 3 are separate 8-bit PWMs. 1 Channels 2 and 3 are concatenated to create one 16-bit PWM channel. Channel 2 becomes the high-order byte and channel 3 becomes the low-order byte. Channel 3 output pin is used as the output for this 16-bit PWM (bit 3 of port PWMP). Channel 3 clock select control bit determines the clock source, channel 3 polarity bit determines the polarity, channel 3 enable bit enables the output and channel 3 center aligned enable bit determines the output mode. Concatenate Channels 0 and 1 0 Channels 0 and 1 are separate 8-bit PWMs. 1 Channels 0 and 1 are concatenated to create one 16-bit PWM channel. Channel 0 becomes the high-order byte and channel 1 becomes the low-order byte. Channel 1 output pin is used as the output for this 16-bit PWM (bit 1 of port PWMP). Channel 1 clock select control bit determines the clock source, channel 1 polarity bit determines the polarity, channel 1 enable bit enables the output and channel 1 center aligned enable bit determines the output mode. PWM Stops in Wait Mode -- Enabling this bit allows for lower power consumption in wait mode by disabling the input clock to the prescaler. 0 Allow the clock to the prescaler to continue while in wait mode. 1 Stop the input clock to the prescaler whenever the MCU is in wait mode. PWM Counters Stop in Freeze Mode -- In freeze mode, there is an option to disable the input clock to the prescaler by setting the PFRZ bit in the PWMCTL register. If this bit is set, whenever the MCU is in freeze mode the input clock to the prescaler is disabled. This feature is useful during emulation as it allows the PWM function to be suspended. In this way, the counters of the PWM can be stopped while in freeze mode so that after normal program flow is continued, the counters are re-enabled to simulate real-time operations. Because the registers remain accessible in this mode, to re-enable the prescaler clock, either disable the PFRZ bit or exit freeze mode. 0 Allow PWM to continue while in freeze mode. 1 Disable PWM input clock to the prescaler whenever the part is in freeze mode. This is useful for emulation.
5 CON23
4 CON01
3 PSWAI
2 PFRZ
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 453
Chapter 15 Pulse-Width Modulator (PWM8B6CV1)
15.3.2.7
Reserved Register (PWMTST)
This register is reserved for factory testing of the PWM module and is not available in normal modes.
7 6 5 4 3 2 1 0
R W Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 15-9. Reserved Register (PWMTST)
Read: always read 0x0000 in normal modes Write: unimplemented in normal modes NOTE Writing to this register when in special modes can alter the PWM functionality.
15.3.2.8
Reserved Register (PWMPRSC)
This register is reserved for factory testing of the PWM module and is not available in normal modes.
7 6 5 4 3 2 1 0
R W Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 15-10. Reserved Register (PWMPRSC)
Read: always read 0x0000 in normal modes Write: unimplemented in normal modes NOTE Writing to this register when in special modes can alter the PWM functionality.
MC9S12HZ256 Data Sheet, Rev. 2.05 454 Freescale Semiconductor
Chapter 15 Pulse-Width Modulator (PWM8B6CV1)
15.3.2.9
PWM Scale A Register (PWMSCLA)
PWMSCLA is the programmable scale value used in scaling clock A to generate clock SA. Clock SA is generated by taking clock A, dividing it by the value in the PWMSCLA register and dividing that by two. Clock SA = Clock A / (2 * PWMSCLA) NOTE When PWMSCLA = 0x0000, PWMSCLA value is considered a full scale value of 256. Clock A is thus divided by 512. Any value written to this register will cause the scale counter to load the new scale value (PWMSCLA).
7 6 5 4 3 2 1 0
R Bit 7 W Reset 0 0 0 0 0 0 0 0 6 5 4 3 2 1 Bit 0
Figure 15-11. PWM Scale A Register (PWMSCLA)
Read: anytime Write: anytime (causes the scale counter to load the PWMSCLA value)
15.3.2.10 PWM Scale B Register (PWMSCLB)
PWMSCLB is the programmable scale value used in scaling clock B to generate clock SB. Clock SB is generated by taking clock B, dividing it by the value in the PWMSCLB register and dividing that by two. Clock SB = Clock B / (2 * PWMSCLB) NOTE When PWMSCLB = 0x0000, PWMSCLB value is considered a full scale value of 256. Clock B is thus divided by 512. Any value written to this register will cause the scale counter to load the new scale value (PWMSCLB).
7 6 5 4 3 2 1 0
R Bit 7 W Reset 0 0 0 0 0 0 0 0 6 5 4 3 2 1 Bit 0
Figure 15-12. PWM Scale B Register (PWMSCLB)
Read: anytime Write: anytime (causes the scale counter to load the PWMSCLB value).
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 455
Chapter 15 Pulse-Width Modulator (PWM8B6CV1)
15.3.2.11 Reserved Registers (PWMSCNTx)
The registers PWMSCNTA and PWMSCNTB are reserved for factory testing of the PWM module and are not available in normal modes.
7 6 5 4 3 2 1 0
R W Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 15-13. Reserved Register (PWMSCNTA)
7 6 5 4 3 2 1 0
R W Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 15-14. Reserved Register (PWMSCNTB)
Read: always read 0x0000 in normal modes Write: unimplemented in normal modes NOTE Writing to these registers when in special modes can alter the PWM functionality.
MC9S12HZ256 Data Sheet, Rev. 2.05 456 Freescale Semiconductor
Chapter 15 Pulse-Width Modulator (PWM8B6CV1)
15.3.2.12 PWM Channel Counter Registers (PWMCNTx)
Each channel has a dedicated 8-bit up/down counter which runs at the rate of the selected clock source. The counter can be read at any time without affecting the count or the operation of the PWM channel. In left aligned output mode, the counter counts from 0 to the value in the period register - 1. In center aligned output mode, the counter counts from 0 up to the value in the period register and then back down to 0. Any value written to the counter causes the counter to reset to 0x0000, the counter direction to be set to up, the immediate load of both duty and period registers with values from the buffers, and the output to change according to the polarity bit. The counter is also cleared at the end of the effective period (see Section 15.4.2.5, "Left Aligned Outputs," and Section 15.4.2.6, "Center Aligned Outputs," for more details). When the channel is disabled (PWMEx = 0), the PWMCNTx register does not count. When a channel becomes enabled (PWMEx = 1), the associated PWM counter starts at the count in the PWMCNTx register. For more detailed information on the operation of the counters, reference Section 15.4.2.4, "PWM Timer Counters." In concatenated mode, writes to the 16-bit counter by using a 16-bit access or writes to either the low- or high-order byte of the counter will reset the 16-bit counter. Reads of the 16-bit counter must be made by 16-bit access to maintain data coherency. NOTE Writing to the counter while the channel is enabled can cause an irregular PWM cycle to occur.
7 6 5 4 3 2 1 0
R W Reset
Bit 7 0 0
6 0 0
5 0 0
4 0 0
3 0 0
2 0 0
1 0 0
Bit 0 0 0
Figure 15-15. PWM Channel Counter Registers (PWMCNT0)
7 6 5 4 3 2 1 0
R W Reset
Bit 7 0 0
6 0 0
5 0 0
4 0 0
3 0 0
2 0 0
1 0 0
Bit 0 0 0
Figure 15-16. PWM Channel Counter Registers (PWMCNT1)
7 6 5 4 3 2 1 0
R W Reset
Bit 7 0 0
6 0 0
5 0 0
4 0 0
3 0 0
2 0 0
1 0 0
Bit 0 0 0
Figure 15-17. PWM Channel Counter Registers (PWMCNT2)
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 457
Chapter 15 Pulse-Width Modulator (PWM8B6CV1)
7
6
5
4
3
2
1
0
R W Reset
Bit 7 0 0
6 0 0
5 0 0
4 0 0
3 0 0
2 0 0
1 0 0
Bit 0 0 0
Figure 15-18. PWM Channel Counter Registers (PWMCNT3)
7 6 5 4 3 2 1 0
R W Reset
Bit 7 0 0
6 0 0
5 0 0
4 0 0
3 0 0
2 0 0
1 0 0
Bit 0 0 0
Figure 15-19. PWM Channel Counter Registers (PWMCNT4)
7 6 5 4 3 2 1 0
R W Reset
Bit 7 0 0
6 0 0
5 0 0
4 0 0
3 0 0
2 0 0
1 0 0
Bit 0 0 0
Figure 15-20. PWM Channel Counter Registers (PWMCNT5)
Read: anytime Write: anytime (any value written causes PWM counter to be reset to 0x0000).
15.3.2.13 PWM Channel Period Registers (PWMPERx)
There is a dedicated period register for each channel. The value in this register determines the period of the associated PWM channel. The period registers for each channel are double buffered so that if they change while the channel is enabled, the change will NOT take effect until one of the following occurs: * The effective period ends * The counter is written (counter resets to 0x0000) * The channel is disabled In this way, the output of the PWM will always be either the old waveform or the new waveform, not some variation in between. If the channel is not enabled, then writes to the period register will go directly to the latches as well as the buffer. NOTE Reads of this register return the most recent value written. Reads do not necessarily return the value of the currently active period due to the double buffering scheme. Reference Section 15.4.2.3, "PWM Period and Duty," for more information.
MC9S12HZ256 Data Sheet, Rev. 2.05 458 Freescale Semiconductor
Chapter 15 Pulse-Width Modulator (PWM8B6CV1)
To calculate the output period, take the selected clock source period for the channel of interest (A, B, SA, or SB) and multiply it by the value in the period register for that channel: * Left aligned output (CAEx = 0) * PWMx period = channel clock period * PWMPERx center aligned output (CAEx = 1) * PWMx period = channel clock period * (2 * PWMPERx) For boundary case programming values, please refer to Section 15.4.2.8, "PWM Boundary Cases."
7 6 5 4 3 2 1 0
R Bit 7 W Reset 0 0 0 0 0 0 0 0 6 5 4 3 2 1 Bit 0
Figure 15-21. PWM Channel Period Registers (PWMPER0)
7 6 5 4 3 2 1 0
R Bit 7 W Reset 0 0 0 0 0 0 0 0 6 5 4 3 2 1 Bit 0
Figure 15-22. PWM Channel Period Registers (PWMPER1)
7 6 5 4 3 2 1 0
R Bit 7 W Reset 0 0 0 0 0 0 0 0 6 5 4 3 2 1 Bit 0
Figure 15-23. PWM Channel Period Registers (PWMPER2)
7 6 5 4 3 2 1 0
R Bit 7 W Reset 0 0 0 0 0 0 0 0 6 5 4 3 2 1 Bit 0
Figure 15-24. PWM Channel Period Registers (PWMPER3)
7 6 5 4 3 2 1 0
R Bit 7 W Reset 0 0 0 0 0 0 0 0 6 5 4 3 2 1 Bit 0
Figure 15-25. PWM Channel Period Registers (PWMPER4)
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 459
Chapter 15 Pulse-Width Modulator (PWM8B6CV1)
7
6
5
4
3
2
1
0
R Bit 7 W Reset 0 0 0 0 0 0 0 0 6 5 4 3 2 1 Bit 0
Figure 15-26. PWM Channel Period Registers (PWMPER5)
Read: anytime Write: anytime
15.3.2.14 PWM Channel Duty Registers (PWMDTYx)
There is a dedicated duty register for each channel. The value in this register determines the duty of the associated PWM channel. The duty value is compared to the counter and if it is equal to the counter value a match occurs and the output changes state. The duty registers for each channel are double buffered so that if they change while the channel is enabled, the change will NOT take effect until one of the following occurs: * The effective period ends * The counter is written (counter resets to 0x0000) * The channel is disabled In this way, the output of the PWM will always be either the old duty waveform or the new duty waveform, not some variation in between. If the channel is not enabled, then writes to the duty register will go directly to the latches as well as the buffer. NOTE Reads of this register return the most recent value written. Reads do not necessarily return the value of the currently active duty due to the double buffering scheme. Reference Section 15.4.2.3, "PWM Period and Duty," for more information. NOTE Depending on the polarity bit, the duty registers will contain the count of either the high time or the low time. If the polarity bit is 1, the output starts high and then goes low when the duty count is reached, so the duty registers contain a count of the high time. If the polarity bit is 0, the output starts low and then goes high when the duty count is reached, so the duty registers contain a count of the low time. To calculate the output duty cycle (high time as a % of period) for a particular channel: * Polarity = 0 (PPOLx = 0) Duty cycle = [(PWMPERx PWMDTYx)/PWMPERx] * 100% * Polarity = 1 (PPOLx = 1) Duty cycle = [PWMDTYx / PWMPERx] * 100% * For boundary case programming values, please refer to Section 15.4.2.8, "PWM Boundary Cases."
MC9S12HZ256 Data Sheet, Rev. 2.05 460 Freescale Semiconductor
Chapter 15 Pulse-Width Modulator (PWM8B6CV1)
7
6
5
4
3
2
1
0
R Bit 7 W Reset 1 1 1 1 1 1 1 1 6 5 4 3 2 1 Bit 0
Figure 15-27. PWM Channel Duty Registers (PWMDTY0)
7 6 5 4 3 2 1 0
R Bit 7 W Reset 1 1 1 1 1 1 1 1 6 5 4 3 2 1 Bit 0
Figure 15-28. PWM Channel Duty Registers (PWMDTY1)
7 6 5 4 3 2 1 0
R Bit 7 W Reset 1 1 1 1 1 1 1 1 6 5 4 3 2 1 Bit 0
Figure 15-29. PWM Channel Duty Registers (PWMDTY2)
7 6 5 4 3 2 1 0
R Bit 7 W Reset 1 1 1 1 1 1 1 1 6 5 4 3 2 1 Bit 0
Figure 15-30. PWM Channel Duty Registers (PWMDTY3)
7 6 5 4 3 2 1 0
R Bit 7 W Reset 1 1 1 1 1 1 1 1 6 5 4 3 2 1 Bit 0
Figure 15-31. PWM Channel Duty Registers (PWMDTY4)
7 6 5 4 3 2 1 0
R Bit 7 W Reset 1 1 1 1 1 1 1 1 6 5 4 3 2 1 Bit 0
Figure 15-32. PWM Channel Duty Registers (PWMDTY5)
Read: anytime Write: anytime
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 461
Chapter 15 Pulse-Width Modulator (PWM8B6CV1)
15.3.2.15 PWM Shutdown Register (PWMSDN)
The PWMSDN register provides for the shutdown functionality of the PWM module in the emergency cases.
7 6 5 4 3 2 1 0
R PWMIF W Reset 0 0 PWMIE
0 PWMLVL PWMRSTRT 0 0
0
PWM5IN PWM5INL PWM5ENA 0
0
0
0
= Unimplemented or Reserved
Figure 15-33. PWM Shutdown Register (PWMSDN)
Read: anytime Write: anytime
Table 15-10. PWMSDN Field Descriptions
Field 7 PWMIF Description PWM Interrupt Flag -- Any change from passive to asserted (active) state or from active to passive state will be flagged by setting the PWMIF flag = 1. The flag is cleared by writing a logic 1 to it. Writing a 0 has no effect. 0 No change on PWM5IN input. 1 Change on PWM5IN input PWM Interrupt Enable -- If interrupt is enabled an interrupt to the CPU is asserted. 0 PWM interrupt is disabled. 1 PWM interrupt is enabled.
6 PWMIE
5 PWM Restart -- The PWM can only be restarted if the PWM channel input 5 is deasserted. After writing a logic 1 PWMRSTRT to the PWMRSTRT bit (trigger event) the PWM channels start running after the corresponding counter passes next "counter = 0" phase. Also, if the PWM5ENA bit is reset to 0, the PWM do not start before the counter passes 0x0000. The bit is always read as 0. 4 PWMLVL PWM Shutdown Output Level -- If active level as defined by the PWM5IN input, gets asserted all enabled PWM channels are immediately driven to the level defined by PWMLVL. 0 PWM outputs are forced to 0 1 PWM outputs are forced to 1. PWM Channel 5 Input Status -- This reflects the current status of the PWM5 pin. PWM Shutdown Active Input Level for Channel 5 -- If the emergency shutdown feature is enabled (PWM5ENA = 1), this bit determines the active level of the PWM5 channel. 0 Active level is low 1 Active level is high
2 PWM5IN 1 PWM5INL
0 PWM Emergency Shutdown Enable -- If this bit is logic 1 the pin associated with channel 5 is forced to input PWM5ENA and the emergency shutdown feature is enabled. All the other bits in this register are meaningful only if PWM5ENA = 1. 0 PWM emergency feature disabled. 1 PWM emergency feature is enabled.
MC9S12HZ256 Data Sheet, Rev. 2.05 462 Freescale Semiconductor
Chapter 15 Pulse-Width Modulator (PWM8B6CV1)
15.4
15.4.1
Functional Description
PWM Clock Select
There are four available clocks called clock A, clock B, clock SA (scaled A), and clock SB (scaled B). These four clocks are based on the bus clock. Clock A and B can be software selected to be 1, 1/2, 1/4, 1/8,..., 1/64, 1/128 times the bus clock. Clock SA uses clock A as an input and divides it further with a reloadable counter. Similarly, clock SB uses clock B as an input and divides it further with a reloadable counter. The rates available for clock SA are software selectable to be clock A divided by 2, 4, 6, 8, ..., or 512 in increments of divide by 2. Similar rates are available for clock SB. Each PWM channel has the capability of selecting one of two clocks, either the pre-scaled clock (clock A or B) or the scaled clock (clock SA or SB). The block diagram in Figure 15-34 shows the four different clocks and how the scaled clocks are created.
15.4.1.1
Prescale
The input clock to the PWM prescaler is the bus clock. It can be disabled whenever the part is in freeze mode by setting the PFRZ bit in the PWMCTL register. If this bit is set, whenever the MCU is in freeze mode the input clock to the prescaler is disabled. This is useful for emulation in order to freeze the PWM. The input clock can also be disabled when all six PWM channels are disabled (PWME5-PWME0 = 0) This is useful for reducing power by disabling the prescale counter. Clock A and clock B are scaled values of the input clock. The value is software selectable for both clock A and clock B and has options of 1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, or 1/128 times the bus clock. The value selected for clock A is determined by the PCKA2, PCKA1, and PCKA0 bits in the PWMPRCLK register. The value selected for clock B is determined by the PCKB2, PCKB1, and PCKB0 bits also in the PWMPRCLK register.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 463
Chapter 15 Pulse-Width Modulator (PWM8B6CV1)
Clock A
M U X PCLK0
Clock to PWM Ch 0
Clock A/2, A/4, A/6,....A/512 PCKA2 PCKA1 PCKA0 Count = 1 Load PWMSCLA M U X PCLK2 M U X PCLK3 Clock B M U X PCLK4 8-Bit Down Counter Count = 1 Load PWMSCLB DIV 2 Clock SB M U X PCLK5 Clock to PWM Ch 5 Clock to PWM Ch 4 Clock to PWM Ch 3 DIV 2 Clock SA
8-Bit Down Counter
M U X PCLK1 M U X
Clock to PWM Ch 1
Clock to PWM Ch 2
Divide by Prescaler Taps:
4
8 16 32 64 128
Clock B/2, B/4, B/6,....B/512 M U X
2
Bus Clock PFRZ FREEZE
PWME5:0
PRESCALE
PCKB2 PCKB1 PCKB0
SCALE
CLOCK SELECT
Figure 15-34. PWM Clock Select Block Diagram
MC9S12HZ256 Data Sheet, Rev. 2.05 464 Freescale Semiconductor
Chapter 15 Pulse-Width Modulator (PWM8B6CV1)
15.4.1.2
Clock Scale
The scaled A clock uses clock A as an input and divides it further with a user programmable value and then divides this by 2. The scaled B clock uses clock B as an input and divides it further with a user programmable value and then divides this by 2. The rates available for clock SA are software selectable to be clock A divided by 2, 4, 6, 8, ..., or 512 in increments of divide by 2. Similar rates are available for clock SB. Clock A is used as an input to an 8-bit down counter. This down counter loads a user programmable scale value from the scale register (PWMSCLA). When the down counter reaches 1, two things happen; a pulse is output and the 8-bit counter is re-loaded. The output signal from this circuit is further divided by two. This gives a greater range with only a slight reduction in granularity. Clock SA equals clock A divided by two times the value in the PWMSCLA register. NOTE Clock SA = Clock A / (2 * PWMSCLA) When PWMSCLA = 0x0000, PWMSCLA value is considered a full scale value of 256. Clock A is thus divided by 512. Similarly, clock B is used as an input to an 8-bit down counter followed by a divide by two producing clock SB. Thus, clock SB equals clock B divided by two times the value in the PWMSCLB register. NOTE Clock SB = Clock B / (2 * PWMSCLB) When PWMSCLB = 0x0000, PWMSCLB value is considered a full scale value of 256. Clock B is thus divided by 512. As an example, consider the case in which the user writes 0x00FF into the PWMSCLA register. Clock A for this case will be bus clock divided by 4. A pulse will occur at a rate of once every 255 x 4 bus cycles. Passing this through the divide by two circuit produces a clock signal at a bus clock divided by 2040 rate. Similarly, a value of 0x0001 in the PWMSCLA register when clock A is bus clock divided by 4 will produce a bus clock divided by 8 rate. Writing to PWMSCLA or PWMSCLB causes the associated 8-bit down counter to be re-loaded. Otherwise, when changing rates the counter would have to count down to 0x0001 before counting at the proper rate. Forcing the associated counter to re-load the scale register value every time PWMSCLA or PWMSCLB is written prevents this. NOTE Writing to the scale registers while channels are operating can cause irregularities in the PWM outputs.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 465
Chapter 15 Pulse-Width Modulator (PWM8B6CV1)
15.4.1.3
Clock Select
Each PWM channel has the capability of selecting one of two clocks. For channels 0, 1, 4, and 5 the clock choices are clock A or clock SA. For channels 2 and 3 the choices are clock B or clock SB. The clock selection is done with the PCLKx control bits in the PWMCLK register. NOTE Changing clock control bits while channels are operating can cause irregularities in the PWM outputs.
15.4.2
PWM Channel Timers
The main part of the PWM module are the actual timers. Each of the timer channels has a counter, a period register and a duty register (each are 8 bit). The waveform output period is controlled by a match between the period register and the value in the counter. The duty is controlled by a match between the duty register and the counter value and causes the state of the output to change during the period. The starting polarity of the output is also selectable on a per channel basis. Figure 15-35 shows a block diagram for PWM timer.
Clock Source 8-Bit Counter GATE (clock edge sync) 8-Bit Compare = T PWMDTYx R 8-Bit Compare = PWMPERx PPOLx Q Q PWMCNTx From Port PWMP Data Register
up/down reset
M U X
M U X
To Pin Driver
Q Q
T R
CAEx
PWMEx
Figure 15-35. PWM Timer Channel Block Diagram
MC9S12HZ256 Data Sheet, Rev. 2.05 466 Freescale Semiconductor
Chapter 15 Pulse-Width Modulator (PWM8B6CV1)
15.4.2.1
PWM Enable
Each PWM channel has an enable bit (PWMEx) to start its waveform output. When any of the PWMEx bits are set (PWMEx = 1), the associated PWM output signal is enabled immediately. However, the actual PWM waveform is not available on the associated PWM output until its clock source begins its next cycle due to the synchronization of PWMEx and the clock source. An exception to this is when channels are concatenated. Refer to Section 15.4.2.7, "PWM 16-Bit Functions," for more detail. NOTE The first PWM cycle after enabling the channel can be irregular. On the front end of the PWM timer, the clock is enabled to the PWM circuit by the PWMEx bit being high. There is an edge-synchronizing circuit to guarantee that the clock will only be enabled or disabled at an edge. When the channel is disabled (PWMEx = 0), the counter for the channel does not count.
15.4.2.2
PWM Polarity
Each channel has a polarity bit to allow starting a waveform cycle with a high or low signal. This is shown on the block diagram as a mux select of either the Q output or the Q output of the PWM output flip-flop. When one of the bits in the PWMPOL register is set, the associated PWM channel output is high at the beginning of the waveform, then goes low when the duty count is reached. Conversely, if the polarity bit is 0, the output starts low and then goes high when the duty count is reached.
15.4.2.3
PWM Period and Duty
Dedicated period and duty registers exist for each channel and are double buffered so that if they change while the channel is enabled, the change will NOT take effect until one of the following occurs: * The effective period ends * The counter is written (counter resets to 0x0000) * The channel is disabled In this way, the output of the PWM will always be either the old waveform or the new waveform, not some variation in between. If the channel is not enabled, then writes to the period and duty registers will go directly to the latches as well as the buffer. A change in duty or period can be forced into effect "immediately" by writing the new value to the duty and/or period registers and then writing to the counter. This forces the counter to reset and the new duty and/or period values to be latched. In addition, because the counter is readable it is possible to know where the count is with respect to the duty value and software can be used to make adjustments. NOTE When forcing a new period or duty into effect immediately, an irregular PWM cycle can occur. Depending on the polarity bit, the duty registers will contain the count of either the high time or the low time.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 467
Chapter 15 Pulse-Width Modulator (PWM8B6CV1)
15.4.2.4
PWM Timer Counters
Each channel has a dedicated 8-bit up/down counter which runs at the rate of the selected clock source (reference Figure 15-34 for the available clock sources and rates). The counter compares to two registers, a duty register and a period register as shown in Figure 15-35. When the PWM counter matches the duty register the output flip-flop changes state causing the PWM waveform to also change state. A match between the PWM counter and the period register behaves differently depending on what output mode is selected as shown in Figure 15-35 and described in Section 15.4.2.5, "Left Aligned Outputs," and Section 15.4.2.6, "Center Aligned Outputs." Each channel counter can be read at anytime without affecting the count or the operation of the PWM channel. Any value written to the counter causes the counter to reset to 0x0000, the counter direction to be set to up, the immediate load of both duty and period registers with values from the buffers, and the output to change according to the polarity bit. When the channel is disabled (PWMEx = 0), the counter stops. When a channel becomes enabled (PWMEx = 1), the associated PWM counter continues from the count in the PWMCNTx register. This allows the waveform to resume when the channel is re-enabled. When the channel is disabled, writing 0 to the period register will cause the counter to reset on the next selected clock. NOTE If the user wants to start a new "clean" PWM waveform without any "history" from the old waveform, the user must write to channel counter (PWMCNTx) prior to enabling the PWM channel (PWMEx = 1). Generally, writes to the counter are done prior to enabling a channel to start from a known state. However, writing a counter can also be done while the PWM channel is enabled (counting). The effect is similar to writing the counter when the channel is disabled except that the new period is started immediately with the output set according to the polarity bit. NOTE Writing to the counter while the channel is enabled can cause an irregular PWM cycle to occur. The counter is cleared at the end of the effective period (see Section 15.4.2.5, "Left Aligned Outputs," and Section 15.4.2.6, "Center Aligned Outputs," for more details).
Table 15-11. PWM Timer Counter Conditions
Counter Clears (0x0000) When PWMCNTx register written to any value Effective period ends Counter Counts When PWM channel is enabled (PWMEx = 1). Counts from last value in PWMCNTx. Counter Stops When PWM channel is disabled (PWMEx = 0)
MC9S12HZ256 Data Sheet, Rev. 2.05 468 Freescale Semiconductor
Chapter 15 Pulse-Width Modulator (PWM8B6CV1)
15.4.2.5
Left Aligned Outputs
The PWM timer provides the choice of two types of outputs, left aligned or center aligned outputs. They are selected with the CAEx bits in the PWMCAE register. If the CAEx bit is cleared (CAEx = 0), the corresponding PWM output will be left aligned. In left aligned output mode, the 8-bit counter is configured as an up counter only. It compares to two registers, a duty register and a period register as shown in the block diagram in Figure 15-35. When the PWM counter matches the duty register the output flip-flop changes state causing the PWM waveform to also change state. A match between the PWM counter and the period register resets the counter and the output flip-flop as shown in Figure 15-35 as well as performing a load from the double buffer period and duty register to the associated registers as described in Section 15.4.2.3, "PWM Period and Duty." The counter counts from 0 to the value in the period register - 1. NOTE Changing the PWM output mode from left aligned output to center aligned output (or vice versa) while channels are operating can cause irregularities in the PWM output. It is recommended to program the output mode before enabling the PWM channel.
PPOLx = 0
PPOLx = 1 PWMDTYx Period = PWMPERx
Figure 15-36. PWM Left Aligned Output Waveform
To calculate the output frequency in left aligned output mode for a particular channel, take the selected clock source frequency for the channel (A, B, SA, or SB) and divide it by the value in the period register for that channel. * PWMx frequency = clock (A, B, SA, or SB) / PWMPERx * PWMx duty cycle (high time as a% of period): -- Polarity = 0 (PPOLx = 0) Duty cycle = [(PWMPERx-PWMDTYx)/PWMPERx] * 100% -- Polarity = 1 (PPOLx = 1) Duty cycle = [PWMDTYx / PWMPERx] * 100% As an example of a left aligned output, consider the following case: Clock source = bus clock, where bus clock = 10 MHz (100 ns period) PPOLx = 0 PWMPERx = 4 PWMDTYx = 1 PWMx frequency = 10 MHz/4 = 2.5 MHz PWMx period = 400 ns PWMx duty cycle = 3/4 *100% = 75%
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 469
Chapter 15 Pulse-Width Modulator (PWM8B6CV1)
Shown below is the output waveform generated.
E = 100 ns
DUTY CYCLE = 75% PERIOD = 400 ns
Figure 15-37. PWM Left Aligned Output Example Waveform
15.4.2.6
Center Aligned Outputs
For center aligned output mode selection, set the CAEx bit (CAEx = 1) in the PWMCAE register and the corresponding PWM output will be center aligned. The 8-bit counter operates as an up/down counter in this mode and is set to up whenever the counter is equal to 0x0000. The counter compares to two registers, a duty register and a period register as shown in the block diagram in Figure 15-35. When the PWM counter matches the duty register the output flip-flop changes state causing the PWM waveform to also change state. A match between the PWM counter and the period register changes the counter direction from an up-count to a down-count. When the PWM counter decrements and matches the duty register again, the output flip-flop changes state causing the PWM output to also change state. When the PWM counter decrements and reaches 0, the counter direction changes from a down-count back to an up-count and a load from the double buffer period and duty registers to the associated registers is performed as described in Section 15.4.2.3, "PWM Period and Duty." The counter counts from 0 up to the value in the period register and then back down to 0. Thus the effective period is PWMPERx*2. NOTE Changing the PWM output mode from left aligned output to center aligned output (or vice versa) while channels are operating can cause irregularities in the PWM output. It is recommended to program the output mode before enabling the PWM channel.
PPOLx = 0
PPOLx = 1 PWMDTYx PWMPERx Period = PWMPERx*2 PWMDTYx PWMPERx
Figure 15-38. PWM Center Aligned Output Waveform
MC9S12HZ256 Data Sheet, Rev. 2.05 470 Freescale Semiconductor
Chapter 15 Pulse-Width Modulator (PWM8B6CV1)
To calculate the output frequency in center aligned output mode for a particular channel, take the selected clock source frequency for the channel (A, B, SA, or SB) and divide it by twice the value in the period register for that channel. * PWMx frequency = clock (A, B, SA, or SB) / (2*PWMPERx) * PWMx duty cycle (high time as a% of period): -- Polarity = 0 (PPOLx = 0) Duty cycle = [(PWMPERx-PWMDTYx)/PWMPERx] * 100% -- Polarity = 1 (PPOLx = 1) Duty cycle = [PWMDTYx / PWMPERx] * 100% As an example of a center aligned output, consider the following case: Clock source = bus clock, where bus clock = 10 MHz (100 ns period) PPOLx = 0 PWMPERx = 4 PWMDTYx = 1 PWMx frequency = 10 MHz/8 = 1.25 MHz PWMx period = 800 ns PWMx duty cycle = 3/4 *100% = 75% Shown below is the output waveform generated.
E = 100 ns E = 100 ns
DUTY CYCLE = 75% PERIOD = 800 ns
Figure 15-39. PWM Center Aligned Output Example Waveform
15.4.2.7
PWM 16-Bit Functions
The PWM timer also has the option of generating 6-channels of 8-bits or 3-channels of 16-bits for greater PWM resolution}. This 16-bit channel option is achieved through the concatenation of two 8-bit channels. The PWMCTL register contains three control bits, each of which is used to concatenate a pair of PWM channels into one 16-bit channel. Channels 4 and 5 are concatenated with the CON45 bit, channels 2 and 3 are concatenated with the CON23 bit, and channels 0 and 1 are concatenated with the CON01 bit. NOTE Change these bits only when both corresponding channels are disabled. When channels 4 and 5 are concatenated, channel 4 registers become the high-order bytes of the double byte channel as shown in Figure 15-40. Similarly, when channels 2 and 3 are concatenated, channel 2 registers become the high-order bytes of the double byte channel. When channels 0 and 1 are concatenated, channel 0 registers become the high-order bytes of the double byte channel.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 471
Chapter 15 Pulse-Width Modulator (PWM8B6CV1)
Clock Source 5 High PWMCNT4 Low PWCNT5
Period/Duty Compare
PWM5
Clock Source 3 High PWMCNT2 Low PWCNT3
Period/Duty Compare
PWM3
Clock Source 1 High PWMCNT0 Low PWCNT1
Period/Duty Compare
PWM1
Figure 15-40. PWM 16-Bit Mode
When using the 16-bit concatenated mode, the clock source is determined by the low-order 8-bit channel clock select control bits. That is channel 5 when channels 4 and 5 are concatenated, channel 3 when channels 2 and 3 are concatenated, and channel 1 when channels 0 and 1 are concatenated. The resulting PWM is output to the pins of the corresponding low-order 8-bit channel as also shown in Figure 15-40. The polarity of the resulting PWM output is controlled by the PPOLx bit of the corresponding low-order 8-bit channel as well. After concatenated mode is enabled (CONxx bits set in PWMCTL register), enabling/disabling the corresponding 16-bit PWM channel is controlled by the low-order PWMEx bit. In this case, the high-order bytes PWMEx bits have no effect and their corresponding PWM output is disabled. In concatenated mode, writes to the 16-bit counter by using a 16-bit access or writes to either the low or high-order byte of the counter will reset the 16-bit counter. Reads of the 16-bit counter must be made by 16-bit access to maintain data coherency. Either left aligned or center aligned output mode can be used in concatenated mode and is controlled by the low-order CAEx bit. The high-order CAEx bit has no effect.
MC9S12HZ256 Data Sheet, Rev. 2.05 472 Freescale Semiconductor
Chapter 15 Pulse-Width Modulator (PWM8B6CV1)
Table 15-12 is used to summarize which channels are used to set the various control bits when in 16-bit mode.
Table 15-12. 16-bit Concatenation Mode Summary
CONxx CON45 CON23 CON01 PWMEx PWME5 PWME3 PWME1 PPOLx PPOL5 PPOL3 PPOL1 PCLKx PCLK5 PCLK3 PCLK1 CAEx CAE5 CAE3 CAE1 PWMx Output PWM5 PWM3 PWM1
15.4.2.8
PWM Boundary Cases
Table 15-13 summarizes the boundary conditions for the PWM regardless of the output mode (left aligned or center aligned) and 8-bit (normal) or 16-bit (concatenation):
Table 15-13. PWM Boundary Cases
PWMDTYx 0x0000 (indicates no duty) 0x0000 (indicates no duty) XX XX >= PWMPERx >= PWMPERx
1
PWMPERx >0x0000 >0x0000 0x00001 (indicates no period) 0x00001 (indicates no period) XX XX
PPOLx 1 0 1 0 1 0
PWMx Output Always Low Always High Always High Always Low Always High Always Low
Counter = 0x0000 and does not count.
15.5
Resets
The reset state of each individual bit is listed within the register description section (see Section 15.3, "Memory Map and Register Definition," which details the registers and their bit-fields. All special functions or modes which are initialized during or just following reset are described within this section. * The 8-bit up/down counter is configured as an up counter out of reset. * All the channels are disabled and all the counters don't count.
15.6
Interrupts
The PWM8B6C module has only one interrupt which is generated at the time of emergency shutdown, if the corresponding enable bit (PWMIE) is set. This bit is the enable for the interrupt. The interrupt flag PWMIF is set whenever the input level of the PWM5 channel changes while PWM5ENA=1 or when PWMENA is being asserted while the level at PWM5 is active. A description of the registers involved and affected due to this interrupt is explained in Section 15.3.2.15, "PWM Shutdown Register (PWMSDN)."
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 473
Chapter 15 Pulse-Width Modulator (PWM8B6CV1)
MC9S12HZ256 Data Sheet, Rev. 2.05 474 Freescale Semiconductor
Chapter 16 Timer Module (TIM16B8CV1)
16.1 Introduction
The basic timer consists of a 16-bit, software-programmable counter driven by a seven-stage programmable prescaler. This timer can be used for many purposes, including input waveform measurements while simultaneously generating an output waveform. Pulse widths can vary from microseconds to many seconds. This timer contains 8 complete input capture/output compare channels and one pulse accumulator. The input capture function is used to detect a selected transition edge and record the time. The output compare function is used for generating output signals or for timer software delays. The 16-bit pulse accumulator is used to operate as a simple event counter or a gated time accumulator. The pulse accumulator shares timer channel 7 when in event mode. A full access for the counter registers or the input capture/output compare registers should take place in one clock cycle. Accessing high byte and low byte separately for all of these registers may not yield the same result as accessing them in one word.
16.1.1
Features
The TIM16B8C includes these distinctive features: * Eight input capture/output compare channels. * Clock prescaling. * 16-bit counter. * 16-bit pulse accumulator.
16.1.2
Stop: Freeze: Wait: Normal:
Modes of Operation
Timer is off because clocks are stopped. Timer counter keep on running, unless TSFRZ in TSCR (0x0006) is set to 1. Counters keep on running, unless TSWAI in TSCR (0x0006) is set to 1. Timer counter keep on running, unless TEN in TSCR (0x0006) is cleared to 0.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 475
Chapter 16 Timer Module (TIM16B8CV1)
16.1.3
Block Diagrams
Channel 0 Input capture Output compare Channel 1 Input capture Output compare Channel 2 Input capture Output compare Channel 3 Input capture Output compare Registers Channel 4 Input capture Output compare Channel 5 Input capture Output compare
Bus clock
Prescaler
IOC0
16-bit Counter
IOC1
Timer overflow interrupt Timer channel 0 interrupt
IOC2
IOC3
IOC4
IOC5
Timer channel 7 interrupt
Channel 6 Input capture Output compare 16-bit Pulse accumulator Channel 7 Input capture Output compare
IOC6
PA overflow interrupt PA input interrupt
IOC7
Figure 16-1. TIM16B8C Block Diagram
MC9S12HZ256 Data Sheet, Rev. 2.05 476 Freescale Semiconductor
Chapter 16 Timer Module (TIM16B8CV1)
TIMCLK (Timer clock)
CLK1 CLK0
4:1 MUX
PACLK / 256
Prescaled clock (PCLK)
PACLK / 65536
Clock select (PAMOD) PACLK
Edge detector
PT7
Intermodule Bus
Interrupt
PACNT
MUX
Divide by 64
M clock
Figure 16-2. 16-Bit Pulse Accumulator Block Diagram
16-bit Main Timer
PTn
Edge detector
Set CnF Interrupt
TCn Input Capture Reg.
Figure 16-3. Interrupt Flag Setting
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 477
Chapter 16 Timer Module (TIM16B8CV1)
PULSE ACCUMULATOR CHANNEL 7 OUTPUT COMPARE OM7 OL7 OC7M7
PAD
Figure 16-4. Channel 7 Output Compare/Pulse Accumulator Logic
NOTE For more information see the respective functional descriptions in Section 16.4, "Functional Description," of this document.
16.2
External Signal Description
The TIM16B8C module has a total of eight external pins.
16.2.1
IOC7 -- Input Capture and Output Compare Channel 7 Pin
This pin serves as input capture or output compare for channel 7. This can also be configured as pulse accumulator input.
16.2.2
IOC6 -- Input Capture and Output Compare Channel 6 Pin
This pin serves as input capture or output compare for channel 6.
16.2.3
IOC5 -- Input Capture and Output Compare Channel 5 Pin
This pin serves as input capture or output compare for channel 5.
16.2.4
IOC4 -- Input Capture and Output Compare Channel 4 Pin
This pin serves as input capture or output compare for channel 4. Pin
16.2.5
IOC3 -- Input Capture and Output Compare Channel 3 Pin
This pin serves as input capture or output compare for channel 3.
MC9S12HZ256 Data Sheet, Rev. 2.05 478 Freescale Semiconductor
Chapter 16 Timer Module (TIM16B8CV1)
16.2.6
IOC2 -- Input Capture and Output Compare Channel 2 Pin
This pin serves as input capture or output compare for channel 2.
16.2.7
IOC1 -- Input Capture and Output Compare Channel 1 Pin
This pin serves as input capture or output compare for channel 1.
16.2.8
IOC0 -- Input Capture and Output Compare Channel 0 Pin
NOTE For the description of interrupts see Section 16.6, "Interrupts".
This pin serves as input capture or output compare for channel 0.
16.3
Memory Map and Register Definition
This section provides a detailed description of all memory and registers.
16.3.1
Module Memory Map
The memory map for the TIM16B8C module is given below in Table 16-1. The address listed for each register is the address offset. The total address for each register is the sum of the base address for the TIM16B8C module and the address offset for each register.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 479
Chapter 16 Timer Module (TIM16B8CV1)
Table 16-1. TIM16B8C Memory Map
Address Offset 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C 0x000D 0x000E 0x000F 0x0010 0x0011 0x0012 0x0013 0x0014 0x0015 0x0016 0x0017 0x0018 0x0019 0x001A 0x001B 0x001C 0x001D 0x001E 0x001F 0x0020 0x0021 0x0022 0x0023 0x002D
1 2
Use Timer Input Capture/Output Compare Select (TIOS) Timer Compare Force Register (CFORC) Output Compare 7 Mask Register (OC7M) Output Compare 7 Data Register (OC7D) Timer Count Register (TCNT(hi)) Timer Count Register (TCNT(lo)) Timer System Control Register1 (TSCR1) Timer Toggle Overflow Register (TTOV) Timer Control Register1 (TCTL1) Timer Control Register2 (TCTL2) Timer Control Register3 (TCTL3) Timer Control Register4 (TCTL4) Timer Interrupt Enable Register (TIE) Timer System Control Register2 (TSCR2) Main Timer Interrupt Flag1 (TFLG1) Main Timer Interrupt Flag2 (TFLG2) Timer Input Capture/Output Compare Register 0 (TC0(hi)) Timer Input Capture/Output Compare Register 0 (TC0(lo)) Timer Input Capture/Output Compare Register 1 (TC1(hi)) Timer Input Capture/Output Compare Register 1 (TC1(lo)) Timer Input Capture/Output Compare Register 2 (TC2(hi)) Timer Input Capture/Output Compare Register 2 (TC2(lo)) Timer Input Capture/Output Compare Register 3 (TC3(hi)) Timer Input Capture/Output Compare Register 3 (TC3(lo)) Timer Input Capture/Output Compare Register4 (TC4(hi)) Timer Input Capture/Output Compare Register 4 (TC4(lo)) Timer Input Capture/Output Compare Register 5 (TC5(hi)) Timer Input Capture/Output Compare Register 5 (TC5(lo)) Timer Input Capture/Output Compare Register 6 (TC6(hi)) Timer Input Capture/Output Compare Register 6 (TC6(lo)) Timer Input Capture/Output Compare Register 7 (TC7(hi)) Timer Input Capture/Output Compare Register 7 (TC7(lo)) 16-Bit Pulse Accumulator Control Register (PACTL) Pulse Accumulator Flag Register (PAFLG) Pulse Accumulator Count Register (PACNT(hi)) Pulse Accumulator Count Register (PACNT(lo)) Timer Test Register (TIMTST)
Access R/W R/W1 R/W R/W R/W2 R/W2 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W3 R/W3 R/W3 R/W3 R/W3 R/W3 R/W3 R/W3 R/W3 R/W3 R/W3 R/W3 R/W3 R/W3 R/W3 R/W3 R/W R/W R/W R/W --4 R/W2 --4
0x0024 - 0x002C Reserved 0x002E - 0x002F Reserved Always read 0x0000. Only writable in special modes (test_mode = 1). 3 Write to these registers have no meaning or effect during input capture.
MC9S12HZ256 Data Sheet, Rev. 2.05 480 Freescale Semiconductor
Chapter 16 Timer Module (TIM16B8CV1)
4
Write has no effect; return 0 on read
16.3.2
Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order.
Register Name 0x0000 TIOS R W R W R W R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 Bit 0
IOS7
IOS6
IOS5
IOS4
IOS3
IOS2
IOS1
IOS0
0x0001 CFORC 0x0002 OC7M 0x0003 OC7D 0x0004 TCNTH 0x0005 TCNTL 0x0006 TSCR2 0x0007 TTOV 0x0008 TCTL1 0x0009 TCTL2 0x000A TCTL3 0x000B TCTL4
0 FOC7 OC7M7
0 FOC6 OC7M6
0 FOC5 OC7M5
0 FOC4 OC7M4
0 FOC3 OC7M3
0 FOC2 OC7M2
0 FOC1 OC7M1
0 FOC0 OC7M0
OC7D7
OC7D6
OC7D5
OC7D4
OC7D3
OC7D2
OC7D1
OC7D0
TCNT15
TCNT14
TCNT13
TCNT12
TCNT11
TCNT10
TCNT9
TCNT8
TCNT7
TCNT6
TCNT5
TCNT4
TCNT3 0
TCNT2 0
TCNT1 0
TCNT0 0
TEN
TSWAI
TSFRZ
TFFCA
TOV7
TOV6
TOV5
TOV4
TOV3
TOV2
TOV1
TOV0
OM7
OL7
OM6
OL6
OM5
OL5
OM4
OL4
OM3
OL3
OM2
OL2
OM1
OL1
OM0
OL0
EDG7B
EDG7A
EDG6B
EDG6A
EDG5B
EDG5A
EDG4B
EDG4A
EDG3B
EDG3A
EDG2B
EDG2A
EDG1B
EDG1A
EDG0B
EDG0A
= Unimplemented or Reserved
Figure 16-5. TIM16B8C Register Summary
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 481
Chapter 16 Timer Module (TIM16B8CV1)
Register Name 0x000C TIE 0x000D TSCR2 0x000E TFLG1 0x000F TFLG2 R W R W R W R W R 0x0010-0x001F TCxH-TCxL W R W 0x0020 PACTL 0x0021 PAFLG 0x0022 PACNTH 0x0023 PACNTL 0x0024-0x002F Reserved R W R W R W R W R W
Bit 7 C7I
6 C6I 0
5 C5I 0
4 C4I 0
3 C3I
2 C2I
1 C1I
Bit 0 C0I
TOI
TCRE
PR2
PR1
PR0
C7F
C6F 0
C5F 0
C4F 0
C3F 0
C2F 0
C1F 0
C0F 0
TOF
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7 0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PAEN 0
PAMOD 0
PEDGE 0
CLK1 0
CLK0 0
PAOVI
PAI
0
PAOVF
PAIF
PACNT15
PACNT14
PACNT13
PACNT12
PACNT11
PACNT10
PACNT9
PACNT8
PACNT7
PACNT6
PACNT5
PACNT4
PACNT3
PACNT2
PACNT1
PACNT0
= Unimplemented or Reserved
Figure 16-5. TIM16B8C Register Summary (continued)
16.3.2.1
Timer Input Capture/Output Compare Select (TIOS)
7 6 5 4 3 2 1 0
R IOS7 W Reset 0 0 0 0 0 0 0 0 IOS6 IOS5 IOS4 IOS3 IOS2 IOS1 IOS0
Figure 16-6. Timer Input Capture/Output Compare Select (TIOS)
MC9S12HZ256 Data Sheet, Rev. 2.05 482 Freescale Semiconductor
Chapter 16 Timer Module (TIM16B8CV1)
Read: Anytime Write: Anytime
Table 16-2. TIOS Field Descriptions
Field 7:0 IOS[7:0] Description Input Capture or Output Compare Channel Configuration 0 The corresponding channel acts as an input capture. 1 The corresponding channel acts as an output compare.
16.3.2.2
Timer Compare Force Register (CFORC)
7 6 5 4 3 2 1 0
R W Reset
0 FOC7 0
0 FOC6 0
0 FOC5 0
0 FOC4 0
0 FOC3 0
0 FOC2 0
0 FOC1 0
0 FOC0 0
Figure 16-7. Timer Compare Force Register (CFORC)
Read: Anytime but will always return 0x0000 (1 state is transient) Write: Anytime
Table 16-3. CFORC Field Descriptions
Field 7:0 FOC[7:0] Description Force Output Compare Action for Channel 7:0 -- A write to this register with the corresponding data bit(s) set causes the action which is programmed for output compare "x" to occur immediately. The action taken is the same as if a successful comparison had just taken place with the TCx register except the interrupt flag does not get set. Note: A successful channel 7 output compare overrides any channel 6:0 compares. If forced output compare on any channel occurs at the same time as the successful output compare then forced output compare action will take precedence and interrupt flag won't get set.
16.3.2.3
Output Compare 7 Mask Register (OC7M)
7 6 5 4 3 2 1 0
R OC7M7 W Reset 0 0 0 0 0 0 0 0 OC7M6 OC7M5 OC7M4 OC7M3 OC7M2 OC7M1 OC7M0
Figure 16-8. Output Compare 7 Mask Register (OC7M)
Read: Anytime Write: Anytime
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 483
Chapter 16 Timer Module (TIM16B8CV1)
Table 16-4. OC7M Field Descriptions
Field 7:0 OC7M[7:0] Description Output Compare 7 Mask -- Setting the OC7Mx (x ranges from 0 to 6) will set the corresponding port to be an output port when the corresponding TIOSx (x ranges from 0 to 6) bit is set to be an output compare. Note: A successful channel 7 output compare overrides any channel 6:0 compares. For each OC7M bit that is set, the output compare action reflects the corresponding OC7D bit.
16.3.2.4
Output Compare 7 Data Register (OC7D)
7 6 5 4 3 2 1 0
R OC7D7 W Reset 0 0 0 0 0 0 0 0 OC7D6 OC7D5 OC7D4 OC7D3 OC7D2 OC7D1 OC7D0
Figure 16-9. Output Compare 7 Data Register (OC7D)
Read: Anytime Write: Anytime
Table 16-5. OC7D Field Descriptions
Field 7:0 OC7D[7:0] Description Output Compare 7 Data -- A channel 7 output compare can cause bits in the output compare 7 data register to transfer to the timer port data register depending on the output compare 7 mask register.
16.3.2.5
Timer Count Register (TCNT)
15 14 13 12 11 10 9 9
R TCNT15 W Reset 0 0 0 0 0 0 0 0 TCNT14 TCNT13 TCNT12 TCNT11 TCNT10 TCNT9 TCNT8
Figure 16-10. Timer Count Register High (TCNTH)
7 6 5 4 3 2 1 0
R TCNT7 W Reset 0 0 0 0 0 0 0 0 TCNT6 TCNT5 TCNT4 TCNT3 TCNT2 TCNT1 TCNT0
Figure 16-11. Timer Count Register Low (TCNTL)
The 16-bit main timer is an up counter. A full access for the counter register should take place in one clock cycle. A separate read/write for high byte and low byte will give a different result than accessing them as a word.
MC9S12HZ256 Data Sheet, Rev. 2.05 484 Freescale Semiconductor
Chapter 16 Timer Module (TIM16B8CV1)
Read: Anytime Write: Has no meaning or effect in the normal mode; only writable in special modes (test_mode = 1). The period of the first count after a write to the TCNT registers may be a different size because the write is not synchronized with the prescaler clock.
16.3.2.6
Timer System Control Register 1 (TSCR1)
7 6 5 4 3 2 1 0
R TEN W Reset 0 0 0 0 TSWAI TSFRZ TFFCA
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 16-12. Timer System Control Register 1 (TSCR2)
Read: Anytime Write: Anytime
Table 16-6. TSCR1 Field Descriptions
Field 7 TEN Description Timer Enable 0 Disables the main timer, including the counter. Can be used for reducing power consumption. 1 Allows the timer to function normally. If for any reason the timer is not active, there is no /64 clock for the pulse accumulator because the /64 is generated by the timer prescaler. Timer Module Stops While in Wait 0 Allows the timer module to continue running during wait. 1 Disables the timer module when the MCU is in the wait mode. Timer interrupts cannot be used to get the MCU out of wait. TSWAI also affects pulse accumulator. Timer Stops While in Freeze Mode 0 Allows the timer counter to continue running while in freeze mode. 1 Disables the timer counter whenever the MCU is in freeze mode. This is useful for emulation. TSFRZ does not stop the pulse accumulator. Timer Fast Flag Clear All 0 Allows the timer flag clearing to function normally. 1 For TFLG1(0x000E), a read from an input capture or a write to the output compare channel (0x0010-0x001F) causes the corresponding channel flag, CnF, to be cleared. For TFLG2 (0x000F), any access to the TCNT register (0x0004, 0x0005) clears the TOF flag. Any access to the PACNT registers (0x0022, 0x0023) clears the PAOVF and PAIF flags in the PAFLG register (0x0021). This has the advantage of eliminating software overhead in a separate clear sequence. Extra care is required to avoid accidental flag clearing due to unintended accesses.
6 TSWAI
5 TSFRZ
4 TFFCA
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 485
Chapter 16 Timer Module (TIM16B8CV1)
16.3.2.7
Timer Toggle On Overflow Register 1 (TTOV)
7 6 5 4 3 2 1 0
R TOV7 W Reset 0 0 0 0 0 0 0 0 TOV6 TOV5 TOV4 TOV3 TOV2 TOV1 TOV0
Figure 16-13. Timer Toggle On Overflow Register 1 (TTOV)
Read: Anytime Write: Anytime
Table 16-7. TTOV Field Descriptions
Field 7:0 TOV[7:0] Description Toggle On Overflow Bits -- TOVx toggles output compare pin on overflow. This feature only takes effect when in output compare mode. When set, it takes precedence over forced output compare but not channel 7 override events. 0 Toggle output compare pin on overflow feature disabled. 1 Toggle output compare pin on overflow feature enabled.
16.3.2.8
Timer Control Register 1/Timer Control Register 2 (TCTL1/TCTL2)
7 6 5 4 3 2 1 0
R OM7 W Reset 0 0 0 0 0 0 0 0 OL7 OM6 OL6 OM5 OL5 OM4 OL4
Figure 16-14. Timer Control Register 1 (TCTL1)
7 6 5 4 3 2 1 0
R OM3 W Reset 0 0 0 0 0 0 0 0 OL3 OM2 OL2 OM1 OL1 OM0 OL0
Figure 16-15. Timer Control Register 2 (TCTL2)
Read: Anytime Write: Anytime
MC9S12HZ256 Data Sheet, Rev. 2.05 486 Freescale Semiconductor
Chapter 16 Timer Module (TIM16B8CV1)
Table 16-8. TCTL1/TCTL2 Field Descriptions
Field 7:0 OMx Description Output Mode -- These eight pairs of control bits are encoded to specify the output action to be taken as a result of a successful OCx compare. When either OMx or OLx is 1, the pin associated with OCx becomes an output tied to OCx. Note: To enable output action by OMx bits on timer port, the corresponding bit in OC7M should be cleared. Output Level -- These eight pairs of control bits are encoded to specify the output action to be taken as a result of a successful OCx compare. When either OMx or OLx is 1, the pin associated with OCx becomes an output tied to OCx. Note: To enable output action by OLx bits on timer port, the corresponding bit in OC7M should be cleared.
7:0 OLx
Table 16-9. Compare Result Output Action
OMx 0 0 1 1 OLx 0 1 0 1 Action Timer disconnected from output pin logic Toggle OCx output line Clear OCx output line to zero Set OCx output line to one
To operate the 16-bit pulse accumulator independently of input capture or output compare 7 and 0 respectively the user must set the corresponding bits IOSx = 1, OMx = 0 and OLx = 0. OC7M7 in the OC7M register must also be cleared.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 487
Chapter 16 Timer Module (TIM16B8CV1)
16.3.2.9
Timer Control Register 3/Timer Control Register 4 (TCTL3 and TCTL4)
7 6 5 4 3 2 1 0
R EDG7B W Reset 0 0 0 0 0 0 0 0 EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A
Figure 16-16. Timer Control Register 3 (TCTL3)
7 6 5 4 3 2 1 0
R EDG3B W Reset 0 0 0 0 0 0 0 0 EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A
Figure 16-17. Timer Control Register 4 (TCTL4)
Read: Anytime Write: Anytime.
Table 16-10. TCTL3/TCTL4 Field Descriptions
Field 7:0 EDGnB EDGnA Description Input Capture Edge Control -- These eight pairs of control bits configure the input capture edge detector circuits.
Table 16-11. Edge Detector Circuit Configuration
EDGnB 0 0 1 1 EDGnA 0 1 0 1 Configuration Capture disabled Capture on rising edges only Capture on falling edges only Capture on any edge (rising or falling)
MC9S12HZ256 Data Sheet, Rev. 2.05 488 Freescale Semiconductor
Chapter 16 Timer Module (TIM16B8CV1)
16.3.2.10 Timer Interrupt Enable Register (TIE)
7 6 5 4 3 2 1 0
R C7I W Reset 0 0 0 0 0 0 0 0 C6I C5I C4I C3I C2I C1I C0I
Figure 16-18. Timer Interrupt Enable Register (TIE)
Read: Anytime Write: Anytime.
Table 16-12. TIE Field Descriptions
Field 7:0 C7I:C0I Description Input Capture/Output Compare "x" Interrupt Enable -- The bits in TIE correspond bit-for-bit with the bits in the TFLG1 status register. If cleared, the corresponding flag is disabled from causing a hardware interrupt. If set, the corresponding flag is enabled to cause a interrupt.
16.3.2.11 Timer System Control Register 2 (TSCR2)
7 6 5 4 3 2 1 0
R TOI W Reset 0
0
0
0 TCRE PR2 0 PR1 0 PR0 0
0
0
0
0
= Unimplemented or Reserved
Figure 16-19. Timer System Control Register 2 (TSCR2)
Read: Anytime Write: Anytime.
Table 16-13. TSCR2 Field Descriptions
Field 7 TOI 3 TCRE Description Timer Overflow Interrupt Enable 0 Interrupt inhibited. 1 Hardware interrupt requested when TOF flag set. Timer Counter Reset Enable -- This bit allows the timer counter to be reset by a successful output compare 7 event. This mode of operation is similar to an up-counting modulus counter. 0 Counter reset inhibited and counter free runs. 1 Counter reset by a successful output compare 7. If TC7 = 0x0000 and TCRE = 1, TCNT will stay at 0x0000 continuously. If TC7 = 0xFFFF and TCRE = 1, TOF will never be set when TCNT is reset from 0xFFFF to 0x0000. Timer Prescaler Select -- These three bits select the frequency of the timer prescaler clock derived from the Bus Clock as shown in Table 16-14.
2 PR[2:0]
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 489
Chapter 16 Timer Module (TIM16B8CV1)
Table 16-14. Timer Clock Selection
PR2 0 0 0 0 1 1 1 1 PR1 0 0 1 1 0 0 1 1 PR0 0 1 0 1 0 1 0 1 Timer Clock Bus Clock / 1 Bus Clock / 2 Bus Clock / 4 Bus Clock / 8 Bus Clock / 16 Bus Clock / 32 Bus Clock / 64 Bus Clock / 128
NOTE The newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter stages equal zero.
16.3.2.12 Main Timer Interrupt Flag 1 (TFLG1)
7 6 5 4 3 2 1 0
R C7F W Reset 0 0 0 0 0 0 0 0 C6F C5F C4F C3F C2F C1F C0F
Figure 16-20. Main Timer Interrupt Flag 1 (TFLG1)
Read: Anytime Write: Used in the clearing mechanism (set bits cause corresponding bits to be cleared). Writing a zero will not affect current status of the bit.
Table 16-15. TRLG1 Field Descriptions
Field 7:0 C[7:0]F Description Input Capture/Output Compare Channel "x" Flag -- These flags are set when an input capture or output compare event occurs. Clear a channel flag by writing one to it. When TFFCA bit in TSCR register is set, a read from an input capture or a write into an output compare channel (0x0010-0x001F) will cause the corresponding channel flag CxF to be cleared.
MC9S12HZ256 Data Sheet, Rev. 2.05 490 Freescale Semiconductor
Chapter 16 Timer Module (TIM16B8CV1)
16.3.2.13 Main Timer Interrupt Flag 2 (TFLG2)
7 6 5 4 3 2 1 0
R TOF W Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Unimplemented or Reserved
Figure 16-21. Main Timer Interrupt Flag 2 (TFLG2)
TFLG2 indicates when interrupt conditions have occurred. To clear a bit in the flag register, write the bit to one. Read: Anytime Write: Used in clearing mechanism (set bits cause corresponding bits to be cleared). Any access to TCNT will clear TFLG2 register if the TFFCA bit in TSCR register is set.
Table 16-16. TRLG2 Field Descriptions
Field 7 TOF Description Timer Overflow Flag -- Set when 16-bit free-running timer overflows from 0xFFFF to 0x0000. This bit is cleared automatically by a write to the TFLG2 register with bit 7 set. (See also TCRE control bit explanation.)
16.3.2.14 Timer Input Capture/Output Compare Registers High and Low 0-7 (TCxH and TCxL)
15 14 13 12 11 10 9 0
R Bit 15 W Reset 0 0 0 0 0 0 0 0 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Figure 16-22. Timer Input Capture/Output Compare Register x High (TCxH)
7 6 5 4 3 2 1 0
R Bit 7 W Reset 0 0 0 0 0 0 0 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Figure 16-23. Timer Input Capture/Output Compare Register x Low (TCxL)
Depending on the TIOS bit for the corresponding channel, these registers are used to latch the value of the free-running counter when a defined transition is sensed by the corresponding input capture edge detector or to trigger an output action for output compare. Read: Anytime
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 491
Chapter 16 Timer Module (TIM16B8CV1)
Write: Anytime for output compare function.Writes to these registers have no meaning or effect during input capture. All timer input capture/output compare registers are reset to 0x0000. NOTE Read/Write access in byte mode for high byte should takes place before low byte otherwise it will give a different result.
16.3.2.15 16-Bit Pulse Accumulator Control Register (PACTL)
7 6 5 4 3 2 1 0
R W Reset
0 PAEN 0 0 PAMOD 0 PEDGE 0 CLK1 0 CLK0 0 PAOVI 0 PAI 0
Unimplemented or Reserved
Figure 16-24. 16-Bit Pulse Accumulator Control Register (PACTL)
When PAEN is set, the PACT is enabled.The PACT shares the input pin with IOC7. Read: Any time Write: Any time
Table 16-17. PACTL Field Descriptions
Field 6 PAEN Description Pulse Accumulator System Enable -- PAEN is independent from TEN. With timer disabled, the pulse accumulator can function unless pulse accumulator is disabled. 0 16-Bit Pulse Accumulator system disabled. 1 Pulse Accumulator system enabled. Pulse Accumulator Mode -- This bit is active only when the Pulse Accumulator is enabled (PAEN = 1). See Table 16-18. 0 Event counter mode. 1 Gated time accumulation mode. Pulse Accumulator Edge Control -- This bit is active only when the Pulse Accumulator is enabled (PAEN = 1). For PAMOD bit = 0 (event counter mode). See Table 16-18. 0 Falling edges on IOC7 pin cause the count to be incremented. 1 Rising edges on IOC7 pin cause the count to be incremented. For PAMOD bit = 1 (gated time accumulation mode). 0 IOC7 input pin high enables M (bus clock) divided by 64 clock to Pulse Accumulator and the trailing falling edge on IOC7 sets the PAIF flag. 1 IOC7 input pin low enables M (bus clock) divided by 64 clock to Pulse Accumulator and the trailing rising edge on IOC7 sets the PAIF flag. Clock Select Bits -- Refer to Table 16-19.
5 PAMOD
4 PEDGE
3:2 CLK[1:0]
MC9S12HZ256 Data Sheet, Rev. 2.05 492 Freescale Semiconductor
Chapter 16 Timer Module (TIM16B8CV1)
Table 16-17. PACTL Field Descriptions (continued)
Field 1 PAOVI 0 PAI Pulse Accumulator Overflow Interrupt Enable 0 Interrupt inhibited. 1 Interrupt requested if PAOVF is set. Pulse Accumulator Input Interrupt Enable 0 Interrupt inhibited. 1 Interrupt requested if PAIF is set. Description
Table 16-18. Pin Action
PAMOD 0 0 1 1 PEDGE 0 1 0 1 Pin Action Falling edge Rising edge Div. by 64 clock enabled with pin high level Div. by 64 clock enabled with pin low level
NOTE If the timer is not active (TEN = 0 in TSCR), there is no divide-by-64 because the /64 clock is generated by the timer prescaler.
Table 16-19. Timer Clock Selection
CLK1 0 0 1 1 CLK0 0 1 0 1 Timer Clock Use timer prescaler clock as timer counter clock Use PACLK as input to timer counter clock Use PACLK/256 as timer counter clock frequency Use PACLK/65536 as timer counter clock frequency
For the description of PACLK please refer Figure 16-24. If the pulse accumulator is disabled (PAEN = 0), the prescaler clock from the timer is always used as an input clock to the timer counter. The change from one selected clock to the other happens immediately after these bits are written.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 493
Chapter 16 Timer Module (TIM16B8CV1)
16.3.2.16 Pulse Accumulator Flag Register (PAFLG)
7 6 5 4 3 2 1 0
R W Reset
0
0
0
0
0
0 PAOVF PAIF 0
0
0
0
0
0
0
0
Unimplemented or Reserved
Figure 16-25. Pulse Accumulator Flag Register (PAFLG)
Read: Anytime Write: Anytime When the TFFCA bit in the TSCR register is set, any access to the PACNT register will clear all the flags in the PAFLG register.
Table 16-20. PAFLG Field Descriptions
Field 1 PAOVF 0 PAIF Description Pulse Accumulator Overflow Flag -- Set when the 16-bit pulse accumulator overflows from 0xFFFF to 0x0000. This bit is cleared automatically by a write to the PAFLG register with bit 1 set. Pulse Accumulator Input edge Flag -- Set when the selected edge is detected at the IOC7 input pin.In event mode the event edge triggers PAIF and in gated time accumulation mode the trailing edge of the gate signal at the IOC7 input pin triggers PAIF. This bit is cleared by a write to the PAFLG register with bit 0 set. Any access to the PACNT register will clear all the flags in this register when TFFCA bit in register TSCR(0x0006) is set.
MC9S12HZ256 Data Sheet, Rev. 2.05 494 Freescale Semiconductor
Chapter 16 Timer Module (TIM16B8CV1)
16.3.2.17 Pulse Accumulators Count Registers (PACNT)
15 14 13 12 11 10 9 0
R PACNT15 W Reset 0 0 0 0 0 0 0 0 PACNT14 PACNT13 PACNT12 PACNT11 PACNT10 PACNT9 PACNT8
Figure 16-26. Pulse Accumulator Count Register High (PACNTH)
7 6 5 4 3 2 1 0
R PACNT7 W Reset 0 0 0 0 0 0 0 0 PACNT6 PACNT5 PACNT4 PACNT3 PACNT2 PACNT1 PACNT0
Figure 16-27. Pulse Accumulator Count Register Low (PACNTL)
Read: Anytime Write: Anytime These registers contain the number of active input edges on its input pin since the last reset. When PACNT overflows from 0xFFFF to 0x0000, the Interrupt flag PAOVF in PAFLG (0x0021) is set. Full count register access should take place in one clock cycle. A separate read/write for high byte and low byte will give a different result than accessing them as a word. NOTE Reading the pulse accumulator counter registers immediately after an active edge on the pulse accumulator input pin may miss the last count because the input has to be synchronized with the bus clock first.
16.4
Functional Description
This section provides a complete functional description of the timer TIM16B8C block. Please refer to the detailed timer block diagram in Figure 16-28 as necessary.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 495
Chapter 16 Timer Module (TIM16B8CV1)
Bus Clock
CLK[1:0] PR[2:1:0] PACLK PACLK/256 PACLK/65536
channel 7 output compare
MUX TCRE CxI CxF
PRESCALER
TCNT(hi):TCNT(lo) CLEAR COUNTER 16-BIT COUNTER TE CHANNEL 0 16-BIT COMPARATOR TC0 EDG0A EDG0B EDGE DETECT C0F OM:OL0 TOV0
TOF TOI
INTERRUPT LOGIC
TOF
C0F
CH. 0 CAPTURE
IOC0 PIN LOGIC CH. 0COMPARE
IOC0 PIN
IOC0 C1F
OM:OL1 TOV1 CH. 1 CAPTURE IOC1 PIN LOGIC CH. 1 COMPARE IOC1 PIN
CHANNEL 1 16-BIT COMPARATOR TC1 EDG1A EDG1B EDGE DETECT C1F
CHANNEL2
IOC1
CHANNEL7 16-BIT COMPARATOR TC7 EDG7A EDG7B EDGE DETECT C7F OM:O73 TOV7
C7F
CH.7 CAPTURE IOC7 PIN PA INPUT LOGIC CH. 7 COMPARE IOC7 PIN
IOC7
PAOVF
PACNT(hi):PACNT(lo)
PEDGE PAE
EDGE DETECT
PACLK/65536 PACLK/256 INTERRUPT REQUEST PAOVI PAOVF
16-BIT COUNTER PACLK PAMOD INTERRUPT LOGIC DIVIDE-BY-64 PAI PAIF PAIF
Bus Clock
PAOVF PAOVI
Figure 16-28. Detailed Timer Block Diagram
16.4.1
Prescaler
The prescaler divides the bus clock by 1,2,4,8,16,32,64 or 128. The prescaler select bits, PR[2:0], select the prescaler divisor. PR[2:0] are in timer system control register 2 (TSCR2).
MC9S12HZ256 Data Sheet, Rev. 2.05 496 Freescale Semiconductor
Chapter 16 Timer Module (TIM16B8CV1)
16.4.2
Input Capture
Clearing the I/O (input/output) select bit, IOSx, configures channel x as an input capture channel. The input capture function captures the time at which an external event occurs. When an active edge occurs on the pin of an input capture channel, the timer transfers the value in the timer counter into the timer channel registers, TCx. The minimum pulse width for the input capture input is greater than two bus clocks. An input capture on channel x sets the CxF flag. The CxI bit enables the CxF flag to generate interrupt requests.
16.4.3
Output Compare
Setting the I/O select bit, IOSx, configures channel x as an output compare channel. The output compare function can generate a periodic pulse with a programmable polarity, duration, and frequency. When the timer counter reaches the value in the channel registers of an output compare channel, the timer can set, clear, or toggle the channel pin. An output compare on channel x sets the CxF flag. The CxI bit enables the CxF flag to generate interrupt requests. The output mode and level bits, OMx and OLx, select set, clear, toggle on output compare. Clearing both OMx and OLx disconnects the pin from the output logic. Setting a force output compare bit, FOCx, causes an output compare on channel x. A forced output compare does not set the channel flag. A successful output compare on channel 7 overrides output compares on all other output compare channels. The output compare 7 mask register masks the bits in the output compare 7 data register. The timer counter reset enable bit, TCRE, enables channel 7 output compares to reset the timer counter. A channel 7 output compare can reset the timer counter even if the IOC7 pin is being used as the pulse accumulator input. Writing to the timer port bit of an output compare pin does not affect the pin state. The value written is stored in an internal latch. When the pin becomes available for general-purpose output, the last value written to the bit appears at the pin.
16.4.4
Pulse Accumulator
The pulse accumulator (PACNT) is a 16-bit counter that can operate in two modes: Event counter mode -- Counting edges of selected polarity on the pulse accumulator input pin, PAI. Gated time accumulation mode -- Counting pulses from a divide-by-64 clock. The PAMOD bit selects the mode of operation. The minimum pulse width for the PAI input is greater than two bus clocks.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 497
Chapter 16 Timer Module (TIM16B8CV1)
16.4.5
Event Counter Mode
Clearing the PAMOD bit configures the PACNT for event counter operation. An active edge on the IOC7 pin increments the pulse accumulator counter. The PEDGE bit selects falling edges or rising edges to increment the count. NOTE The PACNT input and timer channel 7 use the same pin IOC7. To use the IOC7, disconnect it from the output logic by clearing the channel 7 output mode and output level bits, OM7 and OL7. Also clear the channel 7 output compare 7 mask bit, OC7M7. The Pulse Accumulator counter register reflect the number of active input edges on the PACNT input pin since the last reset. The PAOVF bit is set when the accumulator rolls over from 0xFFFF to 0x0000. The pulse accumulator overflow interrupt enable bit, PAOVI, enables the PAOVF flag to generate interrupt requests. NOTE The pulse accumulator counter can operate in event counter mode even when the timer enable bit, TEN, is clear.
16.4.6
Gated Time Accumulation Mode
Setting the PAMOD bit configures the pulse accumulator for gated time accumulation operation. An active level on the PACNT input pin enables a divided-by-64 clock to drive the pulse accumulator. The PEDGE bit selects low levels or high levels to enable the divided-by-64 clock. The trailing edge of the active level at the IOC7 pin sets the PAIF. The PAI bit enables the PAIF flag to generate interrupt requests. The pulse accumulator counter register reflect the number of pulses from the divided-by-64 clock since the last reset. NOTE The timer prescaler generates the divided-by-64 clock. If the timer is not active, there is no divided-by-64 clock.
16.5
Resets
The reset state of each individual bit is listed within Section 16.3, "Memory Map and Register Definition" which details the registers and their bit fields.
16.6
Interrupts
This section describes interrupts originated by the TIM16B8C block. Table 16-21 lists the interrupts generated by the TIM16B8C to communicate with the MCU.
MC9S12HZ256 Data Sheet, Rev. 2.05 498 Freescale Semiconductor
Chapter 16 Timer Module (TIM16B8CV1)
Table 16-21. TIM16B8CV1 Interrupts
Interrupt C[7:0]F PAOVI PAOVF TOF
1
Offset1 -- -- -- --
Vector1 -- -- -- --
Priority1 -- -- -- --
Source Timer Channel 7-0 Pulse Accumulator Input Pulse Accumulator Overflow Timer Overflow
Description Active high timer channel interrupts 7-0 Active high pulse accumulator input interrupt Pulse accumulator overflow interrupt Timer Overflow interrupt
Chip Dependent.
The TIM16B8C uses a total of 11 interrupt vectors. The interrupt vector offsets and interrupt numbers are chip dependent.
16.6.1
Channel [7:0] Interrupt (C[7:0]F)
This active high outputs will be asserted by the module to request a timer channel 7 - 0 interrupt to be serviced by the system controller.
16.6.2
Pulse Accumulator Input Interrupt (PAOVI)
This active high output will be asserted by the module to request a timer pulse accumulator input interrupt to be serviced by the system controller.
16.6.3
Pulse Accumulator Overflow Interrupt (PAOVF)
This active high output will be asserted by the module to request a timer pulse accumulator overflow interrupt to be serviced by the system controller.
16.6.4
Timer Overflow Interrupt (TOF)
This active high output will be asserted by the module to request a timer overflow interrupt to be serviced by the system controller.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 499
Chapter 16 Timer Module (TIM16B8CV1)
MC9S12HZ256 Data Sheet, Rev. 2.05 500 Freescale Semiconductor
Chapter 17 Dual Output Voltage Regulator (VREG3V3V2)
17.1 Introduction
The VREG3V3 is a dual output voltage regulator providing two separate 2.5 V (typical) supplies differing in the amount of current that can be sourced. The regulator input voltage range is from 3.3 V up to 5 V (typical).
17.1.1
Features
The block VREG3V3 includes these distinctive features: * Two parallel, linear voltage regulators -- Bandgap reference * Low-voltage detect (LVD) with low-voltage interrupt (LVI) * Power-on reset (POR) * Low-voltage reset (LVR)
17.1.2
Modes of Operation
There are three modes VREG3V3 can operate in: * Full-performance mode (FPM) (MCU is not in stop mode) The regulator is active, providing the nominal supply voltage of 2.5 V with full current sourcing capability at both outputs. Features LVD (low-voltage detect), LVR (low-voltage reset), and POR (power-on reset) are available. * Reduced-power mode (RPM) (MCU is in stop mode) The purpose is to reduce power consumption of the device. The output voltage may degrade to a lower value than in full-performance mode, additionally the current sourcing capability is substantially reduced. Only the POR is available in this mode, LVD and LVR are disabled. * Shutdown mode Controlled by VREGEN (see device overview chapter for connectivity of VREGEN). This mode is characterized by minimum power consumption. The regulator outputs are in a high impedance state, only the POR feature is available, LVD and LVR are disabled. This mode must be used to disable the chip internal regulator VREG3V3, i.e., to bypass the VREG3V3 to use external supplies.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 501
Chapter 17 Dual Output Voltage Regulator (VREG3V3V2)
17.1.3
Block Diagram
Figure 17-1 shows the function principle of VREG3V3 by means of a block diagram. The regulator core REG consists of two parallel sub-blocks, REG1 and REG2, providing two independent output voltages.
REG2 VDDR VDDA REG
VDDPLL VSSPLL
REG1
VDD
LVD
LVR
LVR
POR
POR
VSSA
VSS
VREGEN
CTRL LVI
REG: Regulator Core LVD: Low Voltage Detect CTRL: Regulator Control LVR: Low Voltage Reset POR: Power-on Reset PIN
Figure 17-1. VREG3V3 Block Diagram
MC9S12HZ256 Data Sheet, Rev. 2.05 502 Freescale Semiconductor
Chapter 17 Dual Output Voltage Regulator (VREG3V3V2)
17.2
External Signal Description
Due to the nature of VREG3V3 being a voltage regulator providing the chip internal power supply voltages most signals are power supply signals connected to pads. Table 17-1 shows all signals of VREG3V3 associated with pins.
Table 17-1. VREG3V3 -- Signal Properties
Name VDDR VDDA VSSA VDD VSS VDDPLL VSSPLL VREGEN (optional) Port -- -- -- -- -- -- -- -- Function VREG3V3 power input (positive supply) VREG3V3 quiet input (positive supply) VREG3V3 quiet input (ground) VREG3V3 primary output (positive supply) VREG3V3 primary output (ground) VREG3V3 secondary output (positive supply) VREG3V3 secondary output (ground) VREG3V3 (Optional) Regulator Enable Reset State -- -- -- -- -- -- -- -- Pull Up -- -- -- -- -- -- -- --
NOTE Check device overview chapter for connectivity of the signals.
17.2.1
VDDR -- Regulator Power Input
Signal VDDR is the power input of VREG3V3. All currents sourced into the regulator loads flow through this pin. A chip external decoupling capacitor (100 nF...220 nF, X7R ceramic) between VDDR and VSSR can smoothen ripple on VDDR. For entering Shutdown Mode, pin VDDR should also be tied to ground on devices without a VREGEN pin.
17.2.2
VDDA, VSSA -- Regulator Reference Supply
Signals VDDA/VSSA which are supposed to be relatively quiet are used to supply the analog parts of the regulator. Internal precision reference circuits are supplied from these signals. A chip external decoupling capacitor (100 nF...220 nF, X7R ceramic) between VDDA and VSSA can further improve the quality of this supply.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 503
Chapter 17 Dual Output Voltage Regulator (VREG3V3V2)
17.2.3
VDD, VSS -- Regulator Output1 (Core Logic)
Signals VDD/VSS are the primary outputs of VREG3V3 that provide the power supply for the core logic. These signals are connected to device pins to allow external decoupling capacitors (100 nF...220 nF, X7R ceramic). In Shutdown Mode an external supply at VDD/VSS can replace the voltage regulator.
17.2.4
VDDPLL, VSSPLL -- Regulator Output2 (PLL)
Signals VDDPLL/VSSPLL are the secondary outputs of VREG3V3 that provide the power supply for the PLL and oscillator. These signals are connected to device pins to allow external decoupling capacitors (100 nF...220 nF, X7R ceramic). In Shutdown Mode an external supply at VDDPLL/VSSPLL can replace the voltage regulator.
17.2.5
VREGEN -- Optional Regulator Enable
This optional signal is used to shutdown VREG3V3. In that case VDD/VSS and VDDPLL/VSSPLL must be provided externally. Shutdown Mode is entered with VREGEN being low. If VREGEN is high, the VREG3V3 is either in Full Performance Mode or in Reduced Power Mode. For the connectivity of VREGEN see device overview chapter. NOTE Switching from FPM or RPM to shutdown of VREG3V3 and vice versa is not supported while the MCU is powered.
17.3
Memory Map and Register Definition
This subsection provides a detailed description of all registers accessible in VREG3V3.
17.3.1
Module Memory Map
Figure 17-2 provides an overview of all used registers.
Table 17-2. VREG3V3 Memory Map
Address Offset 0x0000 Use VREG3V3 Control Register (VREGCTRL) Access R/W
MC9S12HZ256 Data Sheet, Rev. 2.05 504 Freescale Semiconductor
Chapter 17 Dual Output Voltage Regulator (VREG3V3V2)
17.3.2
Register Descriptions
The following paragraphs describe, in address order, all the VREG3V3 registers and their individual bits.
17.3.2.1
VREG3V3 -- Control Register (VREGCTRL)
The VREGCTRL register allows to separately enable features of VREG3V3.
7 6 5 4 3 2 1 0
R W Reset
0
0
0
0
0
LVDS LVIE LVIF 0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 17-2. VREG3V3 -- Control Register (VREGCTRL) Table 17-3. MCCTL1 Field Descriptions
Field 2 LVDS 1 LVIE 0 LVIF Description Low-Voltage Detect Status Bit -- This read-only status bit reflects the input voltage. Writes have no effect. 0 Input voltage VDDA is above level VLVID or RPM or shutdown mode. 1 Input voltage VDDA is below level VLVIA and FPM. Low-Voltage Interrupt Enable Bit 0 Interrupt request is disabled. 1 Interrupt will be requested whenever LVIF is set. Low-Voltage Interrupt Flag -- LVIF is set to 1 when LVDS status bit changes. This flag can only be cleared by writing a 1. Writing a 0 has no effect. If enabled (LVIE = 1), LVIF causes an interrupt request. 0 No change in LVDS bit. 1 LVDS bit has changed.
NOTE On entering the Reduced Power Mode the LVIF is not cleared by the VREG3V3.
17.4
Functional Description
Block VREG3V3 is a voltage regulator as depicted in Figure 17-1. The regulator functional elements are the regulator core (REG), a low-voltage detect module (LVD), a power-on reset module (POR) and a low-voltage reset module (LVR). There is also the regulator control block (CTRL) which represents the interface to the digital core logic but also manages the operating modes of VREG3V3.
17.4.1
REG -- Regulator Core
VREG3V3, respectively its regulator core has two parallel, independent regulation loops (REG1 and REG2) that differ only in the amount of current that can be sourced to the connected loads. Therefore, only REG1 providing the supply at VDD/VSS is explained. The principle is also valid for REG2.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 505
Chapter 17 Dual Output Voltage Regulator (VREG3V3V2)
The regulator is a linear series regulator with a bandgap reference in its Full Performance Mode and a voltage clamp in Reduced Power Mode. All load currents flow from input VDDR to VSS or VSSPLL, the reference circuits are connected to VDDA and VSSA.
17.4.2
Full-Performance Mode
In Full Performance Mode, a fraction of the output voltage (VDD) and the bandgap reference voltage are fed to an operational amplifier. The amplified input voltage difference controls the gate of an output driver which basically is a large NMOS transistor connected to the output.
17.4.3
Reduced-Power Mode
In Reduced Power Mode, the driver gate is connected to a buffered fraction of the input voltage (VDDR). The operational amplifier and the bandgap are disabled to reduce power consumption.
17.4.4
LVD -- Low-Voltage Detect
sub-block LVD is responsible for generating the low-voltage interrupt (LVI). LVD monitors the input voltage (VDDA-VSSA) and continuously updates the status flag LVDS. Interrupt flag LVIF is set whenever status flag LVDS changes its value. The LVD is available in FPM and is inactive in Reduced Power Mode and Shutdown Mode.
17.4.5
POR -- Power-On Reset
This functional block monitors output VDD. If VDD is below VPORD, signal POR is high, if it exceeds VPORD, the signal goes low. The transition to low forces the CPU in the power-on sequence. Due to its role during chip power-up this module must be active in all operating modes of VREG3V3.
17.4.6
LVR -- Low-Voltage Reset
Block LVR monitors the primary output voltage VDD. If it drops below the assertion level (VLVRA) signal LVR asserts and when rising above the deassertion level (VLVRD) signal LVR negates again. The LVR function is available only in Full Performance Mode.
17.4.7
CTRL -- Regulator Control
This part contains the register block of VREG3V3 and further digital functionality needed to control the operating modes. CTRL also represents the interface to the digital core logic.
MC9S12HZ256 Data Sheet, Rev. 2.05 506 Freescale Semiconductor
Chapter 17 Dual Output Voltage Regulator (VREG3V3V2)
17.5
Resets
This subsection describes how VREG3V3 controls the reset of the MCU.The reset values of registers and signals are provided in Section 17.3, "Memory Map and Register Definition". Possible reset sources are listed in Table 17-4.
Table 17-4. VREG3V3 -- Reset Sources
Reset Source Power-on reset Low-voltage reset Always active Available only in Full Performance Mode Local Enable
17.5.1
Power-On Reset
During chip power-up the digital core may not work if its supply voltage VDD is below the POR deassertion level (VPORD). Therefore, signal POR which forces the other blocks of the device into reset is kept high until VDD exceeds VPORD. Then POR becomes low and the reset generator of the device continues the start-up sequence. The power-on reset is active in all operation modes of VREG3V3.
17.5.2
Low-Voltage Reset
For details on low-voltage reset see Section 17.4.6, "LVR -- Low-Voltage Reset".
17.6
Interrupts
This subsection describes all interrupts originated by VREG3V3. The interrupt vectors requested by VREG3V3 are listed in Table 17-5. Vector addresses and interrupt priorities are defined at MCU level.
Table 17-5. VREG3V3 -- Interrupt Vectors
Interrupt Source Low Voltage Interrupt (LVI) Local Enable LVIE = 1; Available only in Full Performance Mode
17.6.1
LVI -- Low-Voltage Interrupt
In FPM VREG3V3 monitors the input voltage VDDA. Whenever VDDA drops below level VLVIA the status bit LVDS is set to 1. Vice versa, LVDS is reset to 0 when VDDA rises above level VLVID. An interrupt, indicated by flag LVIF = 1, is triggered by any change of the status bit LVDS if interrupt enable bit LVIE = 1. NOTE On entering the Reduced Power Mode, the LVIF is not cleared by the VREG3V3.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 507
Chapter 17 Dual Output Voltage Regulator (VREG3V3V2)
MC9S12HZ256 Data Sheet, Rev. 2.05 508 Freescale Semiconductor
Chapter 18 Background Debug Module (BDMV4)
18.1 Introduction
This section describes the functionality of the background debug module (BDM) sub-block of the HCS12 core platform. A block diagram of the BDM is shown in Figure 18-1.
HOST SYSTEM BKGD 16-BIT SHIFT REGISTER
ADDRESS ENTAG BDMACT TRACE INSTRUCTION DECODE AND EXECUTION BUS INTERFACE AND CONTROL LOGIC DATA CLOCKS
SDV ENBDM
STANDARD BDM FIRMWARE LOOKUP TABLE
CLKSW
Figure 18-1. BDM Block Diagram
The background debug module (BDM) sub-block is a single-wire, background debug system implemented in on-chip hardware for minimal CPU intervention. All interfacing with the BDM is done via the BKGD pin. BDMV4 has enhanced capability for maintaining synchronization between the target and host while allowing more flexibility in clock rates. This includes a sync signal to show the clock rate and a handshake signal to indicate when an operation is complete. The system is backwards compatible with older external interfaces.
18.1.1
* * * * * *
Features
Single-wire communication with host development system BDMV4 (and BDM2): Enhanced capability for allowing more flexibility in clock rates BDMV4: SYNC command to determine communication rate BDMV4: GO_UNTIL command BDMV4: Hardware handshake protocol to increase the performance of the serial communication Active out of reset in special single-chip mode
MC9S12HZ256 Data Sheet, Rev. 2.05
Freescale Semiconductor
509
Chapter 18 Background Debug Module (BDMV4)
* * * * * * *
Nine hardware commands using free cycles, if available, for minimal CPU intervention Hardware commands not requiring active BDM 15 firmware commands execute from the standard BDM firmware lookup table Instruction tagging capability Software control of BDM operation during wait mode Software selectable clocks When secured, hardware commands are allowed to access the register space in special single-chip mode, if the FLASH and EEPROM erase tests fail.
18.1.2
Modes of Operation
BDM is available in all operating modes but must be enabled before firmware commands are executed. Some system peripherals may have a control bit which allows suspending the peripheral function during background debug mode.
18.1.2.1
Regular Run Modes
All of these operations refer to the part in run mode. The BDM does not provide controls to conserve power during run mode. * Normal operation General operation of the BDM is available and operates the same in all normal modes. * Special single-chip mode In special single-chip mode, background operation is enabled and active out of reset. This allows programming a system with blank memory. * Special peripheral mode BDM is enabled and active immediately out of reset. BDM can be disabled by clearing the BDMACT bit in the BDM status (BDMSTS) register. The BDM serial system should not be used in special peripheral mode. * Emulation modes General operation of the BDM is available and operates the same as in normal modes.
18.1.2.2
Secure Mode Operation
If the part is in secure mode, the operation of the BDM is reduced to a small subset of its regular run mode operation. Secure operation prevents access to FLASH or EEPROM other than allowing erasure.
18.2
External Signal Description
A single-wire interface pin is used to communicate with the BDM system. Two additional pins are used for instruction tagging. These pins are part of the multiplexed external bus interface (MEBI) sub-block and all interfacing between the MEBI and BDM is done within the core interface boundary. Functional descriptions of the pins are provided below for completeness.
MC9S12HZ256 Data Sheet, Rev. 2.05 510 Freescale Semiconductor
Chapter 18 Background Debug Module (BDMV4)
* * * * *
BKGD -- Background interface pin TAGHI -- High byte instruction tagging pin TAGLO -- Low byte instruction tagging pin BKGD and TAGHI share the same pin. TAGLO and LSTRB share the same pin. NOTE Generally these pins are shared as described, but it is best to check the device overview chapter to make certain. All MCUs at the time of this writing have followed this pin sharing scheme.
18.2.1
BKGD -- Background Interface Pin
Debugging control logic communicates with external devices serially via the single-wire background interface pin (BKGD). During reset, this pin is a mode select input which selects between normal and special modes of operation. After reset, this pin becomes the dedicated serial interface pin for the background debug mode.
18.2.2
TAGHI -- High Byte Instruction Tagging Pin
This pin is used to tag the high byte of an instruction. When instruction tagging is on, a logic 0 at the falling edge of the external clock (ECLK) tags the high half of the instruction word being read into the instruction queue.
18.2.3
TAGLO -- Low Byte Instruction Tagging Pin
This pin is used to tag the low byte of an instruction. When instruction tagging is on and low strobe is enabled, a logic 0 at the falling edge of the external clock (ECLK) tags the low half of the instruction word being read into the instruction queue.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 511
Chapter 18 Background Debug Module (BDMV4)
18.3
Memory Map and Register Definition
A summary of the registers associated with the BDM is shown in Figure 18-2. Registers are accessed by host-driven communications to the BDM hardware using READ_BD and WRITE_BD commands. Detailed descriptions of the registers and associated bits are given in the subsections that follow.
18.3.1
Module Memory Map
Table 18-1. INT Memory Map
Register Address Reserved BDM Status Register (BDMSTS) Reserved BDM CCR Holding Register (BDMCCR) 7 8- BDM Internal Register Position (BDMINR) Reserved Use Access -- R/W -- R/W R --
MC9S12HZ256 Data Sheet, Rev. 2.05 512 Freescale Semiconductor
Chapter 18 Background Debug Module (BDMV4)
18.3.2
Register Name Reserved
Register Descriptions
Bit 7 R W R W R W R W R W R W R W R W R W R W R W R W X 6 X 5 X 4 X 3 X 2 X 1 0 Bit 0 0
BDMSTS
ENBDM X
BDMACT
ENTAG X
SDV
TRACE
CLKSW X
UNSEC
0
Reserved
X
X
X
X
X
Reserved
X
X
X
X
X
X
X
X
Reserved
X
X
X
X
X
X
X
X
Reserved
X
X
X
X
X
X
X
X
BDMCCR
CCR7 0
CCR6 REG14
CCR5 REG13
CCR4 REG12
CCR3 REG11
CCR2 0
CCR1 0
CCR0 0
BDMINR
Reserved
0
0
0
0
0
0
0
0
Reserved
0
0
0
0
0
0
0
0
Reserved
X
X
X
X
X
X
X
X
Reserved
X
X
X
X
X
X
X
X
= Unimplemented, Reserved X = Indeterminate 0
= Implemented (do not alter) = Always read zero
Figure 18-2. BDM Register Summary
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 513
Chapter 18 Background Debug Module (BDMV4)
18.3.2.1
BDM Status Register (BDMSTS)
7 6 5 4 3 2 1 0
R ENBDM W Reset: Special single-chip mode: Special peripheral mode: All other modes: 11 0 0 0
BDMACT ENTAG
SDV
TRACE CLKSW
UNSEC
0
1 1 1 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
02 0 0 0
0 0 0 0
= Unimplemented or Reserved
= Implemented (do not alter)
Figure 18-3. BDM Status Register (BDMSTS)
Note:
1
ENBDM is read as "1" by a debugging environment in Special single-chip mode when the device is not secured or secured but fully erased (Flash and EEPROM).This is because the ENBDM bit is set by the standard firmware before a BDM command can be fully transmitted and executed. UNSEC is read as "1" by a debugging environment in Special single-chip mode when the device is secured and fully erased, else it is "0" and can only be read if not secure (see also bit description).
2
Read: All modes through BDM operation Write: All modes but subject to the following: * BDMACT can only be set by BDM hardware upon entry into BDM. It can only be cleared by the standard BDM firmware lookup table upon exit from BDM active mode. * CLKSW can only be written via BDM hardware or standard BDM firmware write commands. * All other bits, while writable via BDM hardware or standard BDM firmware write commands, should only be altered by the BDM hardware or standard firmware lookup table as part of BDM command execution. * ENBDM should only be set via a BDM hardware command if the BDM firmware commands are needed. (This does not apply in special single-chip mode).
Table 18-2. BDMSTS Field Descriptions
Field 7 ENBDM Description Enable BDM -- This bit controls whether the BDM is enabled or disabled. When enabled, BDM can be made active to allow firmware commands to be executed. When disabled, BDM cannot be made active but BDM hardware commands are allowed. 0 BDM disabled 1 BDM enabled Note: ENBDM is set by the firmware immediately out of reset in special single-chip mode. In secure mode, this bit will not be set by the firmware until after the EEPROM and FLASH erase verify tests are complete. BDM Active Status -- This bit becomes set upon entering BDM. The standard BDM firmware lookup table is then enabled and put into the memory map. BDMACT is cleared by a carefully timed store instruction in the standard BDM firmware as part of the exit sequence to return to user code and remove the BDM memory from the map. 0 BDM not active 1 BDM active
6 BDMACT
MC9S12HZ256 Data Sheet, Rev. 2.05 514 Freescale Semiconductor
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Table 18-2. BDMSTS Field Descriptions (continued)
Field 5 ENTAG Description Tagging Enable -- This bit indicates whether instruction tagging in enabled or disabled. It is set when the TAGGO command is executed and cleared when BDM is entered. The serial system is disabled and the tag function enabled 16 cycles after this bit is written. BDM cannot process serial commands while tagging is active. 0 Tagging not enabled or BDM active 1 Tagging enabled Shift Data Valid -- This bit is set and cleared by the BDM hardware. It is set after data has been transmitted as part of a firmware read command or after data has been received as part of a firmware write command. It is cleared when the next BDM command has been received or BDM is exited. SDV is used by the standard BDM firmware to control program flow execution. 0 Data phase of command not complete 1 Data phase of command is complete TRACE1 BDM Firmware Command is Being Executed -- This bit gets set when a BDM TRACE1 firmware command is first recognized. It will stay set as long as continuous back-to-back TRACE1 commands are executed. This bit will get cleared when the next command that is not a TRACE1 command is recognized. 0 TRACE1 command is not being executed 1 TRACE1 command is being executed Clock Switch -- The CLKSW bit controls which clock the BDM operates with. It is only writable from a hardware BDM command. A 150 cycle delay at the clock speed that is active during the data portion of the command will occur before the new clock source is guaranteed to be active. The start of the next BDM command uses the new clock for timing subsequent BDM communications. Table 18-3 shows the resulting BDM clock source based on the CLKSW and the PLLSEL (Pll select from the clock and reset generator) bits. Note: The BDM alternate clock source can only be selected when CLKSW = 0 and PLLSEL = 1. The BDM serial interface is now fully synchronized to the alternate clock source, when enabled. This eliminates frequency restriction on the alternate clock which was required on previous versions. Refer to the device overview section to determine which clock connects to the alternate clock source input. Note: If the acknowledge function is turned on, changing the CLKSW bit will cause the ACK to be at the new rate for the write command which changes it. Unsecure -- This bit is only writable in special single-chip mode from the BDM secure firmware and always gets reset to zero. It is in a zero state as secure mode is entered so that the secure BDM firmware lookup table is enabled and put into the memory map along with the standard BDM firmware lookup table. The secure BDM firmware lookup table verifies that the on-chip EEPROM and FLASH EEPROM are erased. This being the case, the UNSEC bit is set and the BDM program jumps to the start of the standard BDM firmware lookup table and the secure BDM firmware lookup table is turned off. If the erase test fails, the UNSEC bit will not be asserted. 0 System is in a secured mode 1 System is in a unsecured mode Note: When UNSEC is set, security is off and the user can change the state of the secure bits in the on-chip FLASH EEPROM. Note that if the user does not change the state of the bits to "unsecured" mode, the system will be secured again when it is next taken out of reset.
4 SDV
3 TRACE
2 CLKSW
1 UNSEC
Table 18-3. BDM Clock Sources
PLLSEL 0 0 CLKSW 0 1 Bus clock Bus clock BDMCLK
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Table 18-3. BDM Clock Sources
PLLSEL 1 1 CLKSW 0 1 BDMCLK Alternate clock (refer to the device overview chapter to determine the alternate clock source) Bus clock dependent on the PLL
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18.3.2.2
BDM CCR Holding Register (BDMCCR)
7 6 5 4 3 2 1 0
R CCR7 W Reset 0 0 0 0 0 0 0 0 CCR6 CCR5 CCR4 CCR3 CCR2 CCR1 CCR0
Figure 18-4. BDM CCR Holding Register (BDMCCR)
Read: All modes Write: All modes NOTE When BDM is made active, the CPU stores the value of the CCR register in the BDMCCR register. However, out of special single-chip reset, the BDMCCR is set to 0xD8 and not 0xD0 which is the reset value of the CCR register. When entering background debug mode, the BDM CCR holding register is used to save the contents of the condition code register of the user's program. It is also used for temporary storage in the standard BDM firmware mode. The BDM CCR holding register can be written to modify the CCR value.
18.3.2.3
BDM Internal Register Position Register (BDMINR)
7 6 5 4 3 2 1 0
R W Reset
0
REG14
REG13
REG12
REG11
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 18-5. BDM Internal Register Position (BDMINR)
Read: All modes Write: Never
Table 18-4. BDMINR Field Descriptions
Field Description
6:3 Internal Register Map Position -- These four bits show the state of the upper five bits of the base address for REG[14:11] the system's relocatable register block. BDMINR is a shadow of the INITRG register which maps the register block to any 2K byte space within the first 32K bytes of the 64K byte address space.
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18.4
Functional Description
The BDM receives and executes commands from a host via a single wire serial interface. There are two types of BDM commands, namely, hardware commands and firmware commands. Hardware commands are used to read and write target system memory locations and to enter active background debug mode, see Section 18.4.3, "BDM Hardware Commands." Target system memory includes all memory that is accessible by the CPU. Firmware commands are used to read and write CPU resources and to exit from active background debug mode, see Section 18.4.4, "Standard BDM Firmware Commands." The CPU resources referred to are the accumulator (D), X index register (X), Y index register (Y), stack pointer (SP), and program counter (PC). Hardware commands can be executed at any time and in any mode excluding a few exceptions as highlighted, see Section 18.4.3, "BDM Hardware Commands." Firmware commands can only be executed when the system is in active background debug mode (BDM).
18.4.1
Security
If the user resets into special single-chip mode with the system secured, a secured mode BDM firmware lookup table is brought into the map overlapping a portion of the standard BDM firmware lookup table. The secure BDM firmware verifies that the on-chip EEPROM and FLASH EEPROM are erased. This being the case, the UNSEC bit will get set. The BDM program jumps to the start of the standard BDM firmware and the secured mode BDM firmware is turned off and all BDM commands are allowed. If the EEPROM or FLASH do not verify as erased, the BDM firmware sets the ENBDM bit, without asserting UNSEC, and the firmware enters a loop. This causes the BDM hardware commands to become enabled, but does not enable the firmware commands. This allows the BDM hardware to be used to erase the EEPROM and FLASH. After execution of the secure firmware, regardless of the results of the erase tests, the CPU registers, INITEE and PPAGE, will no longer be in their reset state.
18.4.2
Enabling and Activating BDM
The system must be in active BDM to execute standard BDM firmware commands. BDM can be activated only after being enabled. BDM is enabled by setting the ENBDM bit in the BDM status (BDMSTS) register. The ENBDM bit is set by writing to the BDM status (BDMSTS) register, via the single-wire interface, using a hardware command such as WRITE_BD_BYTE. After being enabled, BDM is activated by one of the following1: * Hardware BACKGROUND command * BDM external instruction tagging mechanism * CPU BGND instruction * Breakpoint sub-block's force or tag mechanism2 When BDM is activated, the CPU finishes executing the current instruction and then begins executing the firmware in the standard BDM firmware lookup table. When BDM is activated by the breakpoint
1. BDM is enabled and active immediately out of special single-chip reset. 2. This method is only available on systems that have a a breakpoint or a debug sub-block. MC9S12HZ256 Data Sheet, Rev. 2.05 518 Freescale Semiconductor
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sub-block, the type of breakpoint used determines if BDM becomes active before or after execution of the next instruction. NOTE If an attempt is made to activate BDM before being enabled, the CPU resumes normal instruction execution after a brief delay. If BDM is not enabled, any hardware BACKGROUND commands issued are ignored by the BDM and the CPU is not delayed. In active BDM, the BDM registers and standard BDM firmware lookup table are mapped to addresses 0xFF00 to 0xFFFF. BDM registers are mapped to addresses 0xFF00 to 0xFF07. The BDM uses these registers which are readable anytime by the BDM. However, these registers are not readable by user programs.
18.4.3
BDM Hardware Commands
Hardware commands are used to read and write target system memory locations and to enter active background debug mode. Target system memory includes all memory that is accessible by the CPU such as on-chip RAM, EEPROM, FLASH EEPROM, I/O and control registers, and all external memory. Hardware commands are executed with minimal or no CPU intervention and do not require the system to be in active BDM for execution, although they can continue to be executed in this mode. When executing a hardware command, the BDM sub-block waits for a free CPU bus cycle so that the background access does not disturb the running application program. If a free cycle is not found within 128 clock cycles, the CPU is momentarily frozen so that the BDM can steal a cycle. When the BDM finds a free cycle, the operation does not intrude on normal CPU operation provided that it can be completed in a single cycle. However, if an operation requires multiple cycles the CPU is frozen until the operation is complete, even though the BDM found a free cycle.
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The BDM hardware commands are listed in Table 18-5.
Table 18-5. Hardware Commands
Command BACKGROUND ACK_ENABLE ACK_DISABLE READ_BD_BYTE READ_BD_WORD READ_BYTE READ_WORD WRITE_BD_BYTE WRITE_BD_WORD WRITE_BYTE WRITE_WORD Opcode (hex) 90 D5 D6 E4 EC E0 E8 C4 CC C0 C8 Data None None None 16-bit address 16-bit data out 16-bit address 16-bit data out 16-bit address 16-bit data out 16-bit address 16-bit data out 16-bit address 16-bit data in 16-bit address 16-bit data in 16-bit address 16-bit data in 16-bit address 16-bit data in Description Enter background mode if firmware is enabled. If enabled, an ACK will be issued when the part enters active background mode. Enable handshake. Issues an ACK pulse after the command is executed. Disable handshake. This command does not issue an ACK pulse. Read from memory with standard BDM firmware lookup table in map. Odd address data on low byte; even address data on high byte. Read from memory with standard BDM firmware lookup table in map. Must be aligned access. Read from memory with standard BDM firmware lookup table out of map. Odd address data on low byte; even address data on high byte. Read from memory with standard BDM firmware lookup table out of map. Must be aligned access. Write to memory with standard BDM firmware lookup table in map. Odd address data on low byte; even address data on high byte. Write to memory with standard BDM firmware lookup table in map. Must be aligned access. Write to memory with standard BDM firmware lookup table out of map. Odd address data on low byte; even address data on high byte. Write to memory with standard BDM firmware lookup table out of map. Must be aligned access.
NOTE: If enabled, ACK will occur when data is ready for transmission for all BDM READ commands and will occur after the write is complete for all BDM WRITE commands.
The READ_BD and WRITE_BD commands allow access to the BDM register locations. These locations are not normally in the system memory map but share addresses with the application in memory. To distinguish between physical memory locations that share the same address, BDM memory resources are enabled just for the READ_BD and WRITE_BD access cycle. This allows the BDM to access BDM locations unobtrusively, even if the addresses conflict with the application memory map.
18.4.4
Standard BDM Firmware Commands
Firmware commands are used to access and manipulate CPU resources. The system must be in active BDM to execute standard BDM firmware commands, see Section 18.4.2, "Enabling and Activating BDM." Normal instruction execution is suspended while the CPU executes the firmware located in the standard BDM firmware lookup table. The hardware command BACKGROUND is the usual way to activate BDM. As the system enters active BDM, the standard BDM firmware lookup table and BDM registers become visible in the on-chip memory map at 0xFF00-0xFFFF, and the CPU begins executing the standard BDM
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firmware. The standard BDM firmware watches for serial commands and executes them as they are received. The firmware commands are shown in Table 18-6.
Table 18-6. Firmware Commands
Command1 READ_NEXT READ_PC READ_D READ_X READ_Y READ_SP WRITE_NEXT WRITE_PC WRITE_D WRITE_X WRITE_Y WRITE_SP GO GO_UNTIL2 TRACE1 TAGGO
1
Opcode (hex) 62 63 64 65 66 67 42 43 44 45 46 47 08 0C 10 18
Data 16-bit data out 16-bit data out 16-bit data out 16-bit data out 16-bit data out 16-bit data out 16-bit data in 16-bit data in 16-bit data in 16-bit data in 16-bit data in 16-bit data in None None None None
Description Increment X by 2 (X = X + 2), then read word X points to. Read program counter. Read D accumulator. Read X index register. Read Y index register. Read stack pointer. Increment X by 2 (X = X + 2), then write word to location pointed to by X. Write program counter. Write D accumulator. Write X index register. Write Y index register. Write stack pointer. Go to user program. If enabled, ACK will occur when leaving active background mode. Go to user program. If enabled, ACK will occur upon returning to active background mode. Execute one user instruction then return to active BDM. If enabled, ACK will occur upon returning to active background mode. Enable tagging and go to user program. There is no ACK pulse related to this command.
If enabled, ACK will occur when data is ready for transmission for all BDM READ commands and will occur after the write is complete for all BDM WRITE commands. 2 Both WAIT (with clocks to the S12 CPU core disabled) and STOP disable the ACK function. The GO_UNTIL command will not get an Acknowledge if one of these two CPU instructions occurs before the "UNTIL" instruction. This can be a problem for any instruction that uses ACK, but GO_UNTIL is a lot more difficult for the development tool to time-out.
18.4.5
BDM Command Structure
Hardware and firmware BDM commands start with an 8-bit opcode followed by a 16-bit address and/or a 16-bit data word depending on the command. All the read commands return 16 bits of data despite the byte or word implication in the command name. NOTE 8-bit reads return 16-bits of data, of which, only one byte will contain valid data. If reading an even address, the valid data will appear in the MSB. If reading an odd address, the valid data will appear in the LSB.
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NOTE 16-bit misaligned reads and writes are not allowed. If attempted, the BDM will ignore the least significant bit of the address and will assume an even address from the remaining bits. For hardware data read commands, the external host must wait 150 bus clock cycles after sending the address before attempting to obtain the read data. This is to be certain that valid data is available in the BDM shift register, ready to be shifted out. For hardware write commands, the external host must wait 150 bus clock cycles after sending the data to be written before attempting to send a new command. This is to avoid disturbing the BDM shift register before the write has been completed. The 150 bus clock cycle delay in both cases includes the maximum 128 cycle delay that can be incurred as the BDM waits for a free cycle before stealing a cycle. For firmware read commands, the external host should wait 44 bus clock cycles after sending the command opcode and before attempting to obtain the read data. This includes the potential of an extra 7 cycles when the access is external with a narrow bus access (+1 cycle) and / or a stretch (+1, 2, or 3 cycles), (7 cycles could be needed if both occur). The 44 cycle wait allows enough time for the requested data to be made available in the BDM shift register, ready to be shifted out. NOTE This timing has increased from previous BDM modules due to the new capability in which the BDM serial interface can potentially run faster than the bus. On previous BDM modules this extra time could be hidden within the serial time. For firmware write commands, the external host must wait 32 bus clock cycles after sending the data to be written before attempting to send a new command. This is to avoid disturbing the BDM shift register before the write has been completed. The external host should wait 64 bus clock cycles after a TRACE1 or GO command before starting any new serial command. This is to allow the CPU to exit gracefully from the standard BDM firmware lookup table and resume execution of the user code. Disturbing the BDM shift register prematurely may adversely affect the exit from the standard BDM firmware lookup table. NOTE If the bus rate of the target processor is unknown or could be changing, it is recommended that the ACK (acknowledge function) be used to indicate when an operation is complete. When using ACK, the delay times are automated. Figure 18-6 represents the BDM command structure. The command blocks illustrate a series of eight bit times starting with a falling edge. The bar across the top of the blocks indicates that the BKGD line idles in the high state. The time for an 8-bit command is 8 x 16 target clock cycles.1
1. Target clock cycles are cycles measured using the target MCU's serial clock rate. See Section 18.4.6, "BDM Serial Interface," and Section 18.3.2.1, "BDM Status Register (BDMSTS)," for information on how serial clock rate is selected. MC9S12HZ256 Data Sheet, Rev. 2.05 522 Freescale Semiconductor
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8 BITS AT 16 TC/BIT HARDWARE READ COMMAND
16 BITS AT 16 TC/BIT ADDRESS
150-BC DELAY
16 BITS AT 16 TC/BIT DATA 150-BC DELAY NEXT COMMAND
HARDWARE WRITE
COMMAND 44-BC DELAY
ADDRESS
DATA
NEXT COMMAND
FIRMWARE READ
COMMAND
DATA 32-BC DELAY
NEXT COMMAND
FIRMWARE WRITE
COMMAND 64-BC DELAY
DATA
NEXT COMMAND
GO, TRACE
COMMAND
NEXT COMMAND
BC = BUS CLOCK CYCLES TC = TARGET CLOCK CYCLES
Figure 18-6. BDM Command Structure
18.4.6
BDM Serial Interface
The BDM communicates with external devices serially via the BKGD pin. During reset, this pin is a mode select input which selects between normal and special modes of operation. After reset, this pin becomes the dedicated serial interface pin for the BDM. The BDM serial interface is timed using the clock selected by the CLKSW bit in the status register see Section 18.3.2.1, "BDM Status Register (BDMSTS)." This clock will be referred to as the target clock in the following explanation. The BDM serial interface uses a clocking scheme in which the external host generates a falling edge on the BKGD pin to indicate the start of each bit time. This falling edge is sent for every bit whether data is transmitted or received. Data is transferred most significant bit (MSB) first at 16 target clock cycles per bit. The interface times out if 512 clock cycles occur between falling edges from the host. The BKGD pin is a pseudo open-drain pin and has an weak on-chip active pull-up that is enabled at all times. It is assumed that there is an external pull-up and that drivers connected to BKGD do not typically drive the high level. Because R-C rise time could be unacceptably long, the target system and host provide brief driven-high (speedup) pulses to drive BKGD to a logic 1. The source of this speedup pulse is the host for transmit cases and the target for receive cases. The timing for host-to-target is shown in Figure 18-7 and that of target-to-host in Figure 18-8 and Figure 18-9. All four cases begin when the host drives the BKGD pin low to generate a falling edge. Because the host and target are operating from separate clocks, it can take the target system up to one full clock cycle to recognize this edge. The target measures delays from this perceived start of the bit time while the host measures delays from the point it actually drove BKGD low to start the bit up to one target
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clock cycle earlier. Synchronization between the host and target is established in this manner at the start of every bit time. Figure 18-7 shows an external host transmitting a logic 1 and transmitting a logic 0 to the BKGD pin of a target system. The host is asynchronous to the target, so there is up to a one clock-cycle delay from the host-generated falling edge to where the target recognizes this edge as the beginning of the bit time. Ten target clock cycles later, the target senses the bit level on the BKGD pin. Internal glitch detect logic requires the pin be driven high no later that eight target clock cycles after the falling edge for a logic 1 transmission. Because the host drives the high speedup pulses in these two cases, the rising edges look like digitally driven signals.
CLOCK TARGET SYSTEM
HOST TRANSMIT 1
HOST TRANSMIT 0 PERCEIVED START OF BIT TIME 10 CYCLES SYNCHRONIZATION UNCERTAINTY TARGET SENSES BIT EARLIEST START OF NEXT BIT
Figure 18-7. BDM Host-to-Target Serial Bit Timing
The receive cases are more complicated. Figure 18-8 shows the host receiving a logic 1 from the target system. Because the host is asynchronous to the target, there is up to one clock-cycle delay from the host-generated falling edge on BKGD to the perceived start of the bit time in the target. The host holds the BKGD pin low long enough for the target to recognize it (at least two target clock cycles). The host must release the low drive before the target drives a brief high speedup pulse seven target clock cycles after the perceived start of the bit time. The host should sample the bit level about 10 target clock cycles after it started the bit time.
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CLOCK TARGET SYSTEM
HOST DRIVE TO BKGD PIN TARGET SYSTEM SPEEDUP PULSE PERCEIVED START OF BIT TIME R-C RISE BKGD PIN
HIGH-IMPEDANCE
HIGH-IMPEDANCE
HIGH-IMPEDANCE
10 CYCLES 10 CYCLES EARLIEST START OF NEXT BIT
HOST SAMPLES BKGD PIN
Figure 18-8. BDM Target-to-Host Serial Bit Timing (Logic 1)
Figure 18-9 shows the host receiving a logic 0 from the target. Because the host is asynchronous to the target, there is up to a one clock-cycle delay from the host-generated falling edge on BKGD to the start of the bit time as perceived by the target. The host initiates the bit time but the target finishes it. Because the target wants the host to receive a logic 0, it drives the BKGD pin low for 13 target clock cycles then briefly drives it high to speed up the rising edge. The host samples the bit level about 10 target clock cycles after starting the bit time.
CLOCK TARGET SYS.
HOST DRIVE TO BKGD PIN TARGET SYS. DRIVE AND SPEEDUP PULSE PERCEIVED START OF BIT TIME BKGD PIN
HIGH-IMPEDANCE SPEEDUP PULSE
10 CYCLES 10 CYCLES EARLIEST START OF NEXT BIT
HOST SAMPLES BKGD PIN
Figure 18-9. BDM Target-to-Host Serial Bit Timing (Logic 0)
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18.4.7
Serial Interface Hardware Handshake Protocol
BDM commands that require CPU execution are ultimately treated at the MCU bus rate. Because the BDM clock source can be asynchronously related to the bus frequency, when CLKSW = 0, it is very helpful to provide a handshake protocol in which the host could determine when an issued command is executed by the CPU. The alternative is to always wait the amount of time equal to the appropriate number of cycles at the slowest possible rate the clock could be running. This sub-section will describe the hardware handshake protocol. The hardware handshake protocol signals to the host controller when an issued command was successfully executed by the target. This protocol is implemented by a 16 serial clock cycle low pulse followed by a brief speedup pulse in the BKGD pin. This pulse is generated by the target MCU when a command, issued by the host, has been successfully executed (see Figure 18-10). This pulse is referred to as the ACK pulse. After the ACK pulse has finished: the host can start the bit retrieval if the last issued command was a read command, or start a new command if the last command was a write command or a control command (BACKGROUND, GO, GO_UNTIL, or TRACE1). The ACK pulse is not issued earlier than 32 serial clock cycles after the BDM command was issued. The end of the BDM command is assumed to be the 16th tick of the last bit. This minimum delay assures enough time for the host to perceive the ACK pulse. Note also that, there is no upper limit for the delay between the command and the related ACK pulse, because the command execution depends upon the CPU bus frequency, which in some cases could be very slow compared to the serial communication rate. This protocol allows a great flexibility for the POD designers, because it does not rely on any accurate time measurement or short response time to any event in the serial communication.
BDM CLOCK (TARGET MCU)
16 CYCLES TARGET TRANSMITS ACK PULSE HIGH-IMPEDANCE 32 CYCLES SPEEDUP PULSE MINIMUM DELAY FROM THE BDM COMMAND BKGD PIN EARLIEST START OF NEXT BIT HIGH-IMPEDANCE
16th TICK OF THE LAST COMMAD BIT
Figure 18-10. Target Acknowledge Pulse (ACK)
NOTE If the ACK pulse was issued by the target, the host assumes the previous command was executed. If the CPU enters WAIT or STOP prior to executing a hardware command, the ACK pulse will not be issued meaning that the BDM command was not executed. After entering wait or stop mode, the BDM command is no longer pending.
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Figure 18-11 shows the ACK handshake protocol in a command level timing diagram. The READ_BYTE instruction is used as an example. First, the 8-bit instruction opcode is sent by the host, followed by the address of the memory location to be read. The target BDM decodes the instruction. A bus cycle is grabbed (free or stolen) by the BDM and it executes the READ_BYTE operation. Having retrieved the data, the BDM issues an ACK pulse to the host controller, indicating that the addressed byte is ready to be retrieved. After detecting the ACK pulse, the host initiates the byte retrieval process. Note that data is sent in the form of a word and the host needs to determine which is the appropriate byte based on whether the address was odd or even.
TARGET HOST NEW BDM COMMAND HOST BDM ISSUES THE ACK PULSE (OUT OF SCALE) BDM EXECUTES THE READ_BYTE COMMAND TARGET
BKGD PIN
READ_BYTE HOST
BYTE ADDRESS TARGET
(2) BYTES ARE RETRIEVED
BDM DECODES THE COMMAND
Figure 18-11. Handshake Protocol at Command Level
Differently from the normal bit transfer (where the host initiates the transmission), the serial interface ACK handshake pulse is initiated by the target MCU by issuing a falling edge in the BKGD pin. The hardware handshake protocol in Figure 18-10 specifies the timing when the BKGD pin is being driven, so the host should follow this timing constraint in order to avoid the risk of an electrical conflict in the BKGD pin. NOTE The only place the BKGD pin can have an electrical conflict is when one side is driving low and the other side is issuing a speedup pulse (high). Other "highs" are pulled rather than driven. However, at low rates the time of the speedup pulse can become lengthy and so the potential conflict time becomes longer as well. The ACK handshake protocol does not support nested ACK pulses. If a BDM command is not acknowledge by an ACK pulse, the host needs to abort the pending command first in order to be able to issue a new BDM command. When the CPU enters WAIT or STOP while the host issues a command that requires CPU execution (e.g., WRITE_BYTE), the target discards the incoming command due to the WAIT or STOP being detected. Therefore, the command is not acknowledged by the target, which means that the ACK pulse will not be issued in this case. After a certain time the host should decide to abort the ACK sequence in order to be free to issue a new command. Therefore, the protocol should provide a mechanism in which a command, and therefore a pending ACK, could be aborted. NOTE Differently from a regular BDM command, the ACK pulse does not provide a time out. This means that in the case of a WAIT or STOP instruction being executed, the ACK would be prevented from being issued. If not aborted, the ACK would remain pending indefinitely. See the handshake abort procedure described in Section 18.4.8, "Hardware Handshake Abort Procedure."
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18.4.8
Hardware Handshake Abort Procedure
The abort procedure is based on the SYNC command. In order to abort a command, which had not issued the corresponding ACK pulse, the host controller should generate a low pulse in the BKGD pin by driving it low for at least 128 serial clock cycles and then driving it high for one serial clock cycle, providing a speedup pulse. By detecting this long low pulse in the BKGD pin, the target executes the SYNC protocol, see Section 18.4.9, "SYNC -- Request Timed Reference Pulse," and assumes that the pending command and therefore the related ACK pulse, are being aborted. Therefore, after the SYNC protocol has been completed the host is free to issue new BDM commands. Although it is not recommended, the host could abort a pending BDM command by issuing a low pulse in the BKGD pin shorter than 128 serial clock cycles, which will not be interpreted as the SYNC command. The ACK is actually aborted when a falling edge is perceived by the target in the BKGD pin. The short abort pulse should have at least 4 clock cycles keeping the BKGD pin low, in order to allow the falling edge to be detected by the target. In this case, the target will not execute the SYNC protocol but the pending command will be aborted along with the ACK pulse. The potential problem with this abort procedure is when there is a conflict between the ACK pulse and the short abort pulse. In this case, the target may not perceive the abort pulse. The worst case is when the pending command is a read command (i.e., READ_BYTE). If the abort pulse is not perceived by the target the host will attempt to send a new command after the abort pulse was issued, while the target expects the host to retrieve the accessed memory byte. In this case, host and target will run out of synchronism. However, if the command to be aborted is not a read command the short abort pulse could be used. After a command is aborted the target assumes the next falling edge, after the abort pulse, is the first bit of a new BDM command. NOTE The details about the short abort pulse are being provided only as a reference for the reader to better understand the BDM internal behavior. It is not recommended that this procedure be used in a real application. Because the host knows the target serial clock frequency, the SYNC command (used to abort a command) does not need to consider the lower possible target frequency. In this case, the host could issue a SYNC very close to the 128 serial clock cycles length. Providing a small overhead on the pulse length in order to assure the SYNC pulse will not be misinterpreted by the target. See Section 18.4.9, "SYNC -- Request Timed Reference Pulse." Figure 18-12 shows a SYNC command being issued after a READ_BYTE, which aborts the READ_BYTE command. Note that, after the command is aborted a new command could be issued by the host computer. NOTE Figure 18-12 does not represent the signals in a true timing scale
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READ_BYTE CMD IS ABORTED BY THE SYNC REQUEST (OUT OF SCALE)
SYNC RESPONSE FROM THE TARGET (OUT OF SCALE)
BKGD PIN
READ_BYTE HOST
MEMORY ADDRESS TARGET
READ_STATUS HOST TARGET
NEW BDM COMMAND HOST TARGET
BDM DECODE AND STARTS TO EXECUTES THE READ_BYTE CMD
NEW BDM COMMAND
Figure 18-12. ACK Abort Procedure at the Command Level
Figure 18-13 shows a conflict between the ACK pulse and the SYNC request pulse. This conflict could occur if a POD device is connected to the target BKGD pin and the target is already in debug active mode. Consider that the target CPU is executing a pending BDM command at the exact moment the POD is being connected to the BKGD pin. In this case, an ACK pulse is issued along with the SYNC command. In this case, there is an electrical conflict between the ACK speedup pulse and the SYNC pulse. Because this is not a probable situation, the protocol does not prevent this conflict from happening.
AT LEAST 128 CYCLES BDM CLOCK (TARGET MCU) ACK PULSE TARGET MCU DRIVES TO BKGD PIN HOST DRIVES SYNC TO BKGD PIN HOST AND TARGET DRIVE TO BKGD PIN HOST SYNC REQUEST PULSE BKGD PIN HIGH-IMPEDANCE ELECTRICAL CONFLICT
SPEEDUP PULSE
16 CYCLES
Figure 18-13. ACK Pulse and SYNC Request Conflict
NOTE This information is being provided so that the MCU integrator will be aware that such a conflict could eventually occur. The hardware handshake protocol is enabled by the ACK_ENABLE and disabled by the ACK_DISABLE BDM commands. This provides backwards compatibility with the existing POD devices which are not able to execute the hardware handshake protocol. It also allows for new POD devices, that support the hardware handshake protocol, to freely communicate with the target device. If desired, without the need for waiting for the ACK pulse.
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Chapter 18 Background Debug Module (BDMV4)
The commands are described as follows: * ACK_ENABLE -- enables the hardware handshake protocol. The target will issue the ACK pulse when a CPU command is executed by the CPU. The ACK_ENABLE command itself also has the ACK pulse as a response. * ACK_DISABLE -- disables the ACK pulse protocol. In this case, the host needs to use the worst case delay time at the appropriate places in the protocol. The default state of the BDM after reset is hardware handshake protocol disabled. All the read commands will ACK (if enabled) when the data bus cycle has completed and the data is then ready for reading out by the BKGD serial pin. All the write commands will ACK (if enabled) after the data has been received by the BDM through the BKGD serial pin and when the data bus cycle is complete. See Section 18.4.3, "BDM Hardware Commands," and Section 18.4.4, "Standard BDM Firmware Commands," for more information on the BDM commands. The ACK_ENABLE sends an ACK pulse when the command has been completed. This feature could be used by the host to evaluate if the target supports the hardware handshake protocol. If an ACK pulse is issued in response to this command, the host knows that the target supports the hardware handshake protocol. If the target does not support the hardware handshake protocol the ACK pulse is not issued. In this case, the ACK_ENABLE command is ignored by the target because it is not recognized as a valid command. The BACKGROUND command will issue an ACK pulse when the CPU changes from normal to background mode. The ACK pulse related to this command could be aborted using the SYNC command. The GO command will issue an ACK pulse when the CPU exits from background mode. The ACK pulse related to this command could be aborted using the SYNC command. The GO_UNTIL command is equivalent to a GO command with exception that the ACK pulse, in this case, is issued when the CPU enters into background mode. This command is an alternative to the GO command and should be used when the host wants to trace if a breakpoint match occurs and causes the CPU to enter active background mode. Note that the ACK is issued whenever the CPU enters BDM, which could be caused by a breakpoint match or by a BGND instruction being executed. The ACK pulse related to this command could be aborted using the SYNC command. The TRACE1 command has the related ACK pulse issued when the CPU enters background active mode after one instruction of the application program is executed. The ACK pulse related to this command could be aborted using the SYNC command. The TAGGO command will not issue an ACK pulse because this would interfere with the tagging function shared on the same pin.
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Chapter 18 Background Debug Module (BDMV4)
18.4.9
SYNC -- Request Timed Reference Pulse
The SYNC command is unlike other BDM commands because the host does not necessarily know the correct communication speed to use for BDM communications until after it has analyzed the response to the SYNC command. To issue a SYNC command, the host should perform the following steps: 1. Drive the BKGD pin low for at least 128 cycles at the lowest possible BDM serial communication frequency (the lowest serial communication frequency is determined by the crystal oscillator or the clock chosen by CLKSW.) 2. Drive BKGD high for a brief speedup pulse to get a fast rise time (this speedup pulse is typically one cycle of the host clock.) 3. Remove all drive to the BKGD pin so it reverts to high impedance. 4. Listen to the BKGD pin for the sync response pulse. Upon detecting the SYNC request from the host, the target performs the following steps: 1. Discards any incomplete command received or bit retrieved. 2. Waits for BKGD to return to a logic 1. 3. Delays 16 cycles to allow the host to stop driving the high speedup pulse. 4. Drives BKGD low for 128 cycles at the current BDM serial communication frequency. 5. Drives a one-cycle high speedup pulse to force a fast rise time on BKGD. 6. Removes all drive to the BKGD pin so it reverts to high impedance. The host measures the low time of this 128 cycle SYNC response pulse and determines the correct speed for subsequent BDM communications. Typically, the host can determine the correct communication speed within a few percent of the actual target speed and the communication protocol can easily tolerate speed errors of several percent. As soon as the SYNC request is detected by the target, any partially received command or bit retrieved is discarded. This is referred to as a soft-reset, equivalent to a time-out in the serial communication. After the SYNC response, the target will consider the next falling edge (issued by the host) as the start of a new BDM command or the start of new SYNC request. Another use of the SYNC command pulse is to abort a pending ACK pulse. The behavior is exactly the same as in a regular SYNC command. Note that one of the possible causes for a command to not be acknowledged by the target is a host-target synchronization problem. In this case, the command may not have been understood by the target and so an ACK response pulse will not be issued.
18.4.10 Instruction Tracing
When a TRACE1 command is issued to the BDM in active BDM, the CPU exits the standard BDM firmware and executes a single instruction in the user code. As soon as this has occurred, the CPU is forced to return to the standard BDM firmware and the BDM is active and ready to receive a new command. If the TRACE1 command is issued again, the next user instruction will be executed. This facilitates stepping or tracing through the user code one instruction at a time.
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Chapter 18 Background Debug Module (BDMV4)
If an interrupt is pending when a TRACE1 command is issued, the interrupt stacking operation occurs but no user instruction is executed. Upon return to standard BDM firmware execution, the program counter points to the first instruction in the interrupt service routine.
18.4.11 Instruction Tagging
The instruction queue and cycle-by-cycle CPU activity are reconstructible in real time or from trace history that is captured by a logic analyzer. However, the reconstructed queue cannot be used to stop the CPU at a specific instruction. This is because execution already has begun by the time an operation is visible outside the system. A separate instruction tagging mechanism is provided for this purpose. The tag follows program information as it advances through the instruction queue. When a tagged instruction reaches the head of the queue, the CPU enters active BDM rather than executing the instruction. NOTE Tagging is disabled when BDM becomes active and BDM serial commands are not processed while tagging is active. Executing the BDM TAGGO command configures two system pins for tagging. The TAGLO signal shares a pin with the LSTRB signal, and the TAGHI signal shares a pin with the BKGD signal. Table 18-7 shows the functions of the two tagging pins. The pins operate independently, that is the state of one pin does not affect the function of the other. The presence of logic level 0 on either pin at the fall of the external clock (ECLK) performs the indicated function. High tagging is allowed in all modes. Low tagging is allowed only when low strobe is enabled (LSTRB is allowed only in wide expanded modes and emulation expanded narrow mode).
Table 18-7. Tag Pin Function
TAGHI 1 1 0 0 TAGLO 1 0 1 0 Tag No tag Low byte High byte Both bytes
18.4.12 Serial Communication Time-Out
The host initiates a host-to-target serial transmission by generating a falling edge on the BKGD pin. If BKGD is kept low for more than 128 target clock cycles, the target understands that a SYNC command was issued. In this case, the target will keep waiting for a rising edge on BKGD in order to answer the SYNC request pulse. If the rising edge is not detected, the target will keep waiting forever without any time-out limit. Consider now the case where the host returns BKGD to logic one before 128 cycles. This is interpreted as a valid bit transmission, and not as a SYNC request. The target will keep waiting for another falling edge marking the start of a new bit. If, however, a new falling edge is not detected by the target within 512 clock cycles since the last falling edge, a time-out occurs and the current command is discarded without affecting memory or the operating mode of the MCU. This is referred to as a soft-reset.
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Chapter 18 Background Debug Module (BDMV4)
If a read command is issued but the data is not retrieved within 512 serial clock cycles, a soft-reset will occur causing the command to be disregarded. The data is not available for retrieval after the time-out has occurred. This is the expected behavior if the handshake protocol is not enabled. However, consider the behavior where the BDC is running in a frequency much greater than the CPU frequency. In this case, the command could time out before the data is ready to be retrieved. In order to allow the data to be retrieved even with a large clock frequency mismatch (between BDC and CPU) when the hardware handshake protocol is enabled, the time out between a read command and the data retrieval is disabled. Therefore, the host could wait for more then 512 serial clock cycles and continue to be able to retrieve the data from an issued read command. However, as soon as the handshake pulse (ACK pulse) is issued, the time-out feature is re-activated, meaning that the target will time out after 512 clock cycles. Therefore, the host needs to retrieve the data within a 512 serial clock cycles time frame after the ACK pulse had been issued. After that period, the read command is discarded and the data is no longer available for retrieval. Any falling edge of the BKGD pin after the time-out period is considered to be a new command or a SYNC request. Note that whenever a partially issued command, or partially retrieved data, has occurred the time out in the serial communication is active. This means that if a time frame higher than 512 serial clock cycles is observed between two consecutive negative edges and the command being issued or data being retrieved is not complete, a soft-reset will occur causing the partially received command or data retrieved to be disregarded. The next falling edge of the BKGD pin, after a soft-reset has occurred, is considered by the target as the start of a new BDM command, or the start of a SYNC request pulse.
18.4.13 Operation in Wait Mode
The BDM cannot be used in wait mode if the system disables the clocks to the BDM. There is a clearing mechanism associated with the WAIT instruction when the clocks to the BDM (CPU core platform) are disabled. As the clocks restart from wait mode, the BDM receives a soft reset (clearing any command in progress) and the ACK function will be disabled. This is a change from previous BDM modules.
18.4.14 Operation in Stop Mode
The BDM is completely shutdown in stop mode. There is a clearing mechanism associated with the STOP instruction. STOP must be enabled and the part must go into stop mode for this to occur. As the clocks restart from stop mode, the BDM receives a soft reset (clearing any command in progress) and the ACK function will be disabled. This is a change from previous BDM modules.
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Chapter 19 Debug Module (DBGV1)
19.1 Introduction
This section describes the functionality of the debug (DBG) sub-block of the HCS12 core platform. The DBG module is designed to be fully compatible with the existing BKP_HCS12_A module (BKP mode) and furthermore provides an on-chip trace buffer with flexible triggering capability (DBG mode). The DBG module provides for non-intrusive debug of application software. The DBG module is optimized for the HCS12 16-bit architecture.
19.1.1
Features
The DBG module in BKP mode includes these distinctive features: * Full or dual breakpoint mode -- Compare on address and data (full) -- Compare on either of two addresses (dual) * BDM or SWI breakpoint -- Enter BDM on breakpoint (BDM) -- Execute SWI on breakpoint (SWI) * Tagged or forced breakpoint -- Break just before a specific instruction will begin execution (TAG) -- Break on the first instruction boundary after a match occurs (Force) * Single, range, or page address compares -- Compare on address (single) -- Compare on address 256 byte (range) -- Compare on any 16K page (page) * At forced breakpoints compare address on read or write * High and/or low byte data compares * Comparator C can provide an additional tag or force breakpoint (enhancement for BKP mode)
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Chapter 19 Debug Module (DBGV1)
The DBG in DBG mode includes these distinctive features: * Three comparators (A, B, and C) -- Dual mode, comparators A and B used to compare addresses -- Full mode, comparator A compares address and comparator B compares data -- Can be used as trigger and/or breakpoint -- Comparator C used in LOOP1 capture mode or as additional breakpoint * Four capture modes -- Normal mode, change-of-flow information is captured based on trigger specification -- Loop1 mode, comparator C is dynamically updated to prevent redundant change-of-flow storage. -- Detail mode, address and data for all cycles except program fetch (P) and free (f) cycles are stored in trace buffer -- Profile mode, last instruction address executed by CPU is returned when trace buffer address is read * Two types of breakpoint or debug triggers -- Break just before a specific instruction will begin execution (tag) -- Break on the first instruction boundary after a match occurs (force) * BDM or SWI breakpoint -- Enter BDM on breakpoint (BDM) -- Execute SWI on breakpoint (SWI) * Nine trigger modes for comparators A and B --A -- A or B -- A then B -- A and B, where B is data (full mode) -- A and not B, where B is data (full mode) -- Event only B, store data -- A then event only B, store data -- Inside range, A address B -- Outside range, address < or address > B * Comparator C provides an additional tag or force breakpoint when capture mode is not configured in LOOP1 mode. * Sixty-four word (16 bits wide) trace buffer for storing change-of-flow information, event only data and other bus information. -- Source address of taken conditional branches (long, short, bit-conditional, and loop constructs) -- Destination address of indexed JMP, JSR, and CALL instruction. -- Destination address of RTI, RTS, and RTC instructions -- Vector address of interrupts, except for SWI and BDM vectors
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Chapter 19 Debug Module (DBGV1)
-- -- -- --
Data associated with event B trigger modes Detail report mode stores address and data for all cycles except program (P) and free (f) cycles Current instruction address when in profiling mode BGND is not considered a change-of-flow (cof) by the debugger
19.1.2
Modes of Operation
There are two main modes of operation: breakpoint mode and debug mode. Each one is mutually exclusive of the other and selected via a software programmable control bit. In the breakpoint mode there are two sub-modes of operation: * Dual address mode, where a match on either of two addresses will cause the system to enter background debug mode (BDM) or initiate a software interrupt (SWI). * Full breakpoint mode, where a match on address and data will cause the system to enter background debug mode (BDM) or initiate a software interrupt (SWI). In debug mode, there are several sub-modes of operation. * Trigger modes There are many ways to create a logical trigger. The trigger can be used to capture bus information either starting from the trigger or ending at the trigger. Types of triggers (A and B are registers): -- A only -- A or B -- A then B -- Event only B (data capture) -- A then event only B (data capture) -- A and B, full mode -- A and not B, full mode -- Inside range -- Outside range * Capture modes There are several capture modes. These determine which bus information is saved and which is ignored. -- Normal: save change-of-flow program fetches -- Loop1: save change-of-flow program fetches, ignoring duplicates -- Detail: save all bus operations except program and free cycles -- Profile: poll target from external device
19.1.3
Block Diagram
Figure 19-1 is a block diagram of this module in breakpoint mode. Figure 19-2 is a block diagram of this module in debug mode.
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Chapter 19 Debug Module (DBGV1) CLOCKS AND CONTROL SIGNALS CONTROL BLOCK BREAKPOINT MODES AND GENERATION OF SWI, FORCE BDM, AND TAGS CONTROL SIGNALS RESULTS SIGNALS CONTROL BITS READ/WRITE CONTROL BKP CONTROL SIGNALS
......
......
EXPANSION ADDRESS ADDRESS WRITE DATA READ DATA
REGISTER BLOCK BKPCT0
BKPCT1 COMPARE BLOCK BKP READ DATA BUS WRITE DATA BUS BKP0X COMPARATOR EXPANSION ADDRESSES
BKP0H
COMPARATOR
ADDRESS HIGH
ADDRESS LOW BKP0L COMPARATOR EXPANSION ADDRESSES BKP1X COMPARATOR DATA HIGH BKP1H COMPARATOR DATA/ADDRESS HIGH MUX DATA/ADDRESS LOW MUX READ DATA HIGH COMPARATOR READ DATA LOW COMPARATOR ADDRESS HIGH DATA LOW ADDRESS LOW
BKP1L
COMPARATOR
Figure 19-1. DBG Block Diagram in BKP Mode
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Chapter 19 Debug Module (DBGV1)
DBG READ DATA BUS ADDRESS BUS CONTROL WRITE DATA BUS READ DATA BUS READ/WRITE DBG MODE ENABLE CHANGE-OF-FLOW INDICATORS MCU IN BDM DETAIL EVENT ONLY CPU PROGRAM COUNTER STORE POINTER INSTRUCTION LAST CYCLE REGISTER BUS CLOCK M U X 64 x 16 BIT WORD TRACE BUFFER PROFILE CAPTURE MODE TRACE BUFFER OR PROFILING DATA ADDRESS/DATA/CONTROL REGISTERS COMPARATOR A COMPARATOR B COMPARATOR C CONTROL MATCH_A MATCH_B MATCH_C LOOP1 TRACER BUFFER CONTROL LOGIC
TAG FORCE
M U X
WRITE DATA BUS READ DATA BUS
M U X
M U X
LAST INSTRUCTION ADDRESS
PROFILE CAPTURE REGISTER
READ/WRITE
Figure 19-2. DBG Block Diagram in DBG Mode
19.2
External Signal Description
The DBG sub-module relies on the external bus interface (generally the MEBI) when the DBG is matching on the external bus. The tag pins in Table 19-1 (part of the MEBI) may also be a part of the breakpoint operation.
Table 19-1. External System Pins Associated with DBG and MEBI
Pin Name BKGD/MODC/ TAGHI PE3/LSTRB/ TAGLO Pin Functions TAGHI TAGLO Description When instruction tagging is on, a 0 at the falling edge of E tags the high half of the instruction word being read into the instruction queue. In expanded wide mode or emulation narrow modes, when instruction tagging is on and low strobe is enabled, a 0 at the falling edge of E tags the low half of the instruction word being read into the instruction queue.
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Chapter 19 Debug Module (DBGV1)
19.3
Memory Map and Register Definition
A summary of the registers associated with the DBG sub-block is shown in Figure 19-3. Detailed descriptions of the registers and bits are given in the subsections that follow.
19.3.1
Module Memory Map
Table 19-2. DBG Memory Map
Address Offset Debug Control Register (DBGC1) Debug Status and Control Register (DBGSC) Debug Trace Buffer Register High (DBGTBH) Debug Trace Buffer Register Low (DBGTBL) 4 5 6 8 9 A B Debug Count Register (DBGCNT) Debug Comparator C Extended Register (DBGCCX) Debug Comparator C Register High (DBGCCH) Debug Comparator C Register Low (DBGCCL) Debug Control Register 2 (DBGC2) / (BKPCT0) Debug Control Register 3 (DBGC3) / (BKPCT1) Debug Comparator A Extended Register (DBGCAX) / (/BKP0X) Debug Comparator A Register High (DBGCAH) / (BKP0H) Debug Comparator A Register Low (DBGCAL) / (BKP0L) Debug Comparator B Extended Register (DBGCBX) / (BKP1X) E F Debug Comparator B Register High (DBGCBH) / (BKP1H) Debug Comparator B Register Low (DBGCBL) / (BKP1L) Use Access R/W R/W R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
19.3.2
Register Descriptions
This section consists of the DBG register descriptions in address order. Most of the register bits can be written to in either BKP or DBG mode, although they may not have any effect in one of the modes. However, the only bits in the DBG module that can be written while the debugger is armed (ARM = 1) are DBGEN and ARM
Name1 DBGC1 R W R W = Unimplemented or Reserved Bit 7 DBGEN AF 6 ARM BF 5 TRGSEL CF 4 BEGIN 0 3 DBGBRK 2 0 1 Bit 0 CAPMOD
DBGSC
TRG
Figure 19-3. DBG Register Summary
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Chapter 19 Debug Module (DBGV1)
Name1 DBGTBH R W R W R W R W R W R W R W R W R W R W R W R W R W R W
Bit 7 Bit 15
6 Bit 14
5 Bit 13
4 Bit 12
3 Bit 11
2 Bit 10
1 Bit 9
Bit 0 Bit 8
DBGTBL
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DBGCNT
TBF
0
CNT
DBGCCX(2)
PAGSEL
EXTCMP
DBGCCH(2)
Bit 15
14
13
12
11
10
9
Bit 8
DBGCCL(2)
Bit 7
6
5
4
3
2
1
Bit 0
DBGC2 BKPCT0 DBGC3 BKPCT1 DBGCAX BKP0X DBGCAH BKP0H DBGCAL BKP0L DBGCBX BKP1X DBGCBH BKP1H DBGCBL BKP1L
BKABEN
FULL
BDM
TAGAB
BKCEN
TAGC
RWCEN
RWC
BKAMBH
BKAMBL
BKBMBH
BKBMBL
RWAEN
RWA
RWBEN
RWB
PAGSEL
EXTCMP
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
PAGSEL
EXTCMP
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
= Unimplemented or Reserved
Figure 19-3. DBG Register Summary (continued)
1
The DBG module is designed for backwards compatibility to existing BKP modules. Register and bit names have changed from the BKP module. This column shows the DBG register name, as well as the BKP register name for reference. 2 Comparator C can be used to enhance the BKP mode by providing a third breakpoint.
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Chapter 19 Debug Module (DBGV1)
19.3.2.1
Debug Control Register 1 (DBGC1)
NOTE All bits are used in DBG mode only.
7 6 5 4 3 2 1 0
R DBGEN W Reset 0 0 0 0 0 ARM TRGSEL BEGIN DBGBRK
0 CAPMOD 0 0 0
= Unimplemented or Reserved
Figure 19-4. Debug Control Register (DBGC1)
NOTE This register cannot be written if BKP mode is enabled (BKABEN in DBGC2 is set).
Table 19-3. DBGC1 Field Descriptions
Field 7 DBGEN Description DBG Mode Enable Bit -- The DBGEN bit enables the DBG module for use in DBG mode. This bit cannot be set if the MCU is in secure mode. 0 DBG mode disabled 1 DBG mode enabled Arm Bit -- The ARM bit controls whether the debugger is comparing and storing data in the trace buffer. See Section 19.4.2.4, "Arming the DBG Module," for more information. 0 Debugger unarmed 1 Debugger armed Note: This bit cannot be set if the DBGEN bit is not also being set at the same time. For example, a write of 01 to DBGEN[7:6] will be interpreted as a write of 00. Trigger Selection Bit -- The TRGSEL bit controls the triggering condition for comparators A and B in DBG mode. It serves essentially the same function as the TAGAB bit in the DBGC2 register does in BKP mode. See Section 19.4.2.1.2, "Trigger Selection," for more information. TRGSEL may also determine the type of breakpoint based on comparator A and B if enabled in DBG mode (DBGBRK = 1). Please refer to Section 19.4.3.1, "Breakpoint Based on Comparator A and B." 0 Trigger on any compare address match 1 Trigger before opcode at compare address gets executed (tagged-type) Begin/End Trigger Bit -- The BEGIN bit controls whether the trigger begins or ends storing of data in the trace buffer. See Section 19.4.2.8.1, "Storing with Begin-Trigger," and Section 19.4.2.8.2, "Storing with End-Trigger," for more details. 0 Trigger at end of stored data 1 Trigger before storing data
6 ARM
5 TRGSEL
4 BEGIN
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Chapter 19 Debug Module (DBGV1)
Table 19-3. DBGC1 Field Descriptions (continued)
Field 3 DBGBRK Description DBG Breakpoint Enable Bit -- The DBGBRK bit controls whether the debugger will request a breakpoint based on comparator A and B to the CPU upon completion of a tracing session. Please refer to Section 19.4.3, "Breakpoints," for further details. 0 CPU break request not enabled 1 CPU break request enabled Capture Mode Field -- See Table 19-4 for capture mode field definitions. In LOOP1 mode, the debugger will automatically inhibit redundant entries into capture memory. In detail mode, the debugger is storing address and data for all cycles except program fetch (P) and free (f) cycles. In profile mode, the debugger is returning the address of the last instruction executed by the CPU on each access of trace buffer address. Refer to Section 19.4.2.6, "Capture Modes," for more information.
1:0 CAPMOD
Table 19-4. CAPMOD Encoding
CAPMOD 00 01 10 11 Description Normal LOOP1 DETAIL PROFILE
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Chapter 19 Debug Module (DBGV1)
19.3.2.2
Debug Status and Control Register (DBGSC)
7 6 5 4 3 2 1 0
R W Reset
AF
BF
CF
0 TRG
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 19-5. Debug Status and Control Register (DBGSC) Table 19-5. DBGSC Field Descriptions
Field 7 AF Description Trigger A Match Flag -- The AF bit indicates if trigger A match condition was met since arming. This bit is cleared when ARM in DBGC1 is written to a 1 or on any write to this register. 0 Trigger A did not match 1 Trigger A match Trigger B Match Flag -- The BF bit indicates if trigger B match condition was met since arming.This bit is cleared when ARM in DBGC1 is written to a 1 or on any write to this register. 0 Trigger B did not match 1 Trigger B match Comparator C Match Flag -- The CF bit indicates if comparator C match condition was met since arming.This bit is cleared when ARM in DBGC1 is written to a 1 or on any write to this register. 0 Comparator C did not match 1 Comparator C match Trigger Mode Bits -- The TRG bits select the trigger mode of the DBG module as shown Table 19-6. See Section 19.4.2.5, "Trigger Modes," for more detail.
6 BF
5 CF
3:0 TRG
Table 19-6. Trigger Mode Encoding
TRG Value 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1111 Meaning A only A or B A then B Event only B A then event only B A and B (full mode) A and Not B (full mode) Inside range Outside range Reserved (Defaults to A only)
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Chapter 19 Debug Module (DBGV1)
19.3.2.3
Debug Trace Buffer Register (DBGTB)
15 14 13 12 11 10 9 8
R W Reset
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
u
u
u
u
u
u
u
u
= Unimplemented or Reserved
Figure 19-6. Debug Trace Buffer Register High (DBGTBH)
7 6 5 4 3 2 1 0
R W Reset
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
u
u
u
u
u
u
u
u
= Unimplemented or Reserved
Figure 19-7. Debug Trace Buffer Register Low (DBGTBL) Table 19-7. DBGTB Field Descriptions
Field 15:0 Description Trace Buffer Data Bits -- The trace buffer data bits contain the data of the trace buffer. This register can be read only as a word read. Any byte reads or misaligned access of these registers will return 0 and will not cause the trace buffer pointer to increment to the next trace buffer address. The same is true for word reads while the debugger is armed. In addition, this register may appear to contain incorrect data if it is not read with the same capture mode bit settings as when the trace buffer data was recorded (See Section 19.4.2.9, "Reading Data from Trace Buffer"). Because reads will reflect the contents of the trace buffer RAM, the reset state is undefined.
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Chapter 19 Debug Module (DBGV1)
19.3.2.4
Debug Count Register (DBGCNT)
7 6 5 4 3 2 1 0
R W Reset
TBF
0
CNT
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 19-8. Debug Count Register (DBGCNT) Table 19-8. DBGCNT Field Descriptions
Field 7 TBF 5:0 CNT Description Trace Buffer Full -- The TBF bit indicates that the trace buffer has stored 64 or more words of data since it was last armed. If this bit is set, then all 64 words will be valid data, regardless of the value in CNT[5:0]. The TBF bit is cleared when ARM in DBGC1 is written to a 1. Count Value -- The CNT bits indicate the number of valid data words stored in the trace buffer. Table 19-9 shows the correlation between the CNT bits and the number of valid data words in the trace buffer. When the CNT rolls over to 0, the TBF bit will be set and incrementing of CNT will continue if DBG is in end-trigger mode. The DBGCNT register is cleared when ARM in DBGC1 is written to a 1.
Table 19-9. CNT Decoding Table
TBF 0 0 0 CNT 000000 000001 000010 .. .. 111110 111111 000000 Description No data valid 1 word valid 2 words valid .. .. 62 words valid 63 words valid 64 words valid; if BEGIN = 1, the ARM bit will be cleared. A breakpoint will be generated if DBGBRK = 1 64 words valid, oldest data has been overwritten by most recent data
0 1
1
000001 .. .. 111111
MC9S12HZ256 Data Sheet, Rev. 2.05 546 Freescale Semiconductor
Chapter 19 Debug Module (DBGV1)
19.3.2.5
Debug Comparator C Extended Register (DBGCCX)
7 6 5 4 3 2 1 0
R PAGSEL W Reset 0 0 0 0 0 0 0 0 EXTCMP
Figure 19-9. Debug Comparator C Extended Register (DBGCCX) Table 19-10. DBGCCX Field Descriptions
Field 7:6 PAGSEL Description Page Selector Field -- In both BKP and DBG mode, PAGSEL selects the type of paging as shown in Table 19-11. DPAGE and EPAGE are not yet implemented so the value in bit 7 will be ignored (i.e., PAGSEL values of 10 and 11 will be interpreted as values of 00 and 01, respectively). Comparator C Extended Compare Bits -- The EXTCMP bits are used as comparison address bits as shown in Table 19-11 along with the appropriate PPAGE, DPAGE, or EPAGE signal from the core. Note: Comparator C can be used when the DBG module is configured for BKP mode. Extended addressing comparisons for comparator C use PAGSEL and will operate differently to the way that comparator A and B operate in BKP mode.
5:0 EXTCMP
Table 19-11. PAGSEL Decoding1
PAGSEL 00 01 103 112
1 2
Description Normal (64k) PPAGE (256 -- 16K pages) DPAGE (reserved) (256 -- 4K pages) EPAGE (reserved) (256 -- 1K pages)
EXTCMP Not used EXTCMP[5:0] is compared to address bits [21:16]2 EXTCMP[3:0] is compared to address bits [19:16] EXTCMP[1:0] is compared to address bits [17:16]
Comment No paged memory PPAGE[7:0] / XAB[21:14] becomes address bits [21:14]1 DPAGE / XAB[21:14] becomes address bits [19:12] EPAGE / XAB[21:14] becomes address bits [17:10]
See Figure 19-10. Current HCS12 implementations have PPAGE limited to 6 bits. Therefore, EXTCMP[5:4] should be set to 00. 3 Data page (DPAGE) and Extra page (EPAGE) are reserved for implementation on devices that support paged data and extra space.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 547
Chapter 19 Debug Module (DBGV1)
DBGCXX PAGSEL 7 6 0 5 0 4 3 EXTCMP 2 1 BIT 0 BIT 15
DBGCXH[15:12] BIT 14 BIT 13 BIT 12 BKP/DBG MODE
9 8
SEE NOTE 1 PORTK/XAB XAB21 XAB20 XAB19 XAB18 XAB17 XAB16 XAB15 XAB14
PPAGE
PIX7
PIX6
PIX5
PIX4
PIX3
PIX2
PIX1
PIX0
SEE NOTE 2 NOTES: 1. In BKP and DBG mode, PAGSEL selects the type of paging as shown in Table 19-11. 2. Current HCS12 implementations are limited to six PPAGE bits, PIX[5:0]. Therefore, EXTCMP[5:4] = 00.
Figure 19-10. Comparator C Extended Comparison in BKP/DBG Mode
19.3.2.6
Debug Comparator C Register (DBGCC)
15 14 13 12 11 10
R W Reset
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 19-11. Debug Comparator C Register High (DBGCCH)
7 6 5 4 3 2 1 0
R W Reset
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 19-12. Debug Comparator C Register Low (DBGCCL) Table 19-12. DBGCC Field Descriptions
Field 15:0 Description Comparator C Compare Bits -- The comparator C compare bits control whether comparator C will compare the address bus bits [15:0] to a logic 1 or logic 0. See Table 19-13. 0 Compare corresponding address bit to a logic 0 1 Compare corresponding address bit to a logic 1 Note: This register will be cleared automatically when the DBG module is armed in LOOP1 mode.
MC9S12HZ256 Data Sheet, Rev. 2.05 548 Freescale Semiconductor
Chapter 19 Debug Module (DBGV1)
Table 19-13. Comparator C Compares
PAGSEL x0 x1 EXTCMP Compare No compare EXTCMP[5:0] = XAB[21:16] High-Byte Compare DBGCCH[7:0] = AB[15:8] DBGCCH[7:0] = XAB[15:14],AB[13:8]
19.3.2.7
Debug Control Register 2 (DBGC2)
7 6 5 4 3 2 1 0
R W Reset
1
BKABEN1 0
FULL 0
BDM 0
TAGAB 0
BKCEN2 0
TAGC2 0
RWCEN2 0
RWC2 0
When BKABEN is set (BKP mode), all bits in DBGC2 are available. When BKABEN is cleared and DBG is used in DBG mode, bits FULL and TAGAB have no meaning. 2 These bits can be used in BKP mode and DBG mode (when capture mode is not set in LOOP1) to provide a third breakpoint.
Figure 19-13. Debug Control Register 2 (DBGC2) Table 19-14. DBGC2 Field Descriptions
Field 7 BKABEN Description Breakpoint Using Comparator A and B Enable -- This bit enables the breakpoint capability using comparator A and B, when set (BKP mode) the DBGEN bit in DBGC1 cannot be set. 0 Breakpoint module off 1 Breakpoint module on Full Breakpoint Mode Enable -- This bit controls whether the breakpoint module is in dual mode or full mode. In full mode, comparator A is used to match address and comparator B is used to match data. See Section 19.4.1.2, "Full Breakpoint Mode," for more details. 0 Dual address mode enabled 1 Full breakpoint mode enabled Background Debug Mode Enable -- This bit determines if the breakpoint causes the system to enter background debug mode (BDM) or initiate a software interrupt (SWI). 0 Go to software interrupt on a break request 1 Go to BDM on a break request Comparator A/B Tag Select -- This bit controls whether the breakpoint will cause a break on the next instruction boundary (force) or on a match that will be an executable opcode (tagged). Non-executed opcodes cannot cause a tagged breakpoint. 0 On match, break at the next instruction boundary (force) 1 On match, break if/when the instruction is about to be executed (tagged) Breakpoint Comparator C Enable Bit -- This bit enables the breakpoint capability using comparator C. 0 Comparator C disabled for breakpoint 1 Comparator C enabled for breakpoint Note: This bit will be cleared automatically when the DBG module is armed in loop1 mode. Comparator C Tag Select -- This bit controls whether the breakpoint will cause a break on the next instruction boundary (force) or on a match that will be an executable opcode (tagged). Non-executed opcodes cannot cause a tagged breakpoint. 0 On match, break at the next instruction boundary (force) 1 On match, break if/when the instruction is about to be executed (tagged)
6 FULL
5 BDM
4 TAGAB
3 BKCEN
2 TAGC
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Chapter 19 Debug Module (DBGV1)
Table 19-14. DBGC2 Field Descriptions (continued)
Field 1 RWCEN Description Read/Write Comparator C Enable Bit -- The RWCEN bit controls whether read or write comparison is enabled for comparator C. RWCEN is not useful for tagged breakpoints. 0 Read/Write is not used in comparison 1 Read/Write is used in comparison Read/Write Comparator C Value Bit -- The RWC bit controls whether read or write is used in compare for comparator C. The RWC bit is not used if RWCEN = 0. 0 Write cycle will be matched 1 Read cycle will be matched
0 RWC
19.3.2.8
Debug Control Register 3 (DBGC3)
7 6 5 4 3 2 1 0
R W Reset
1 2
BKAMBH1 0
BKAMBL1 0
BKBMBH2 0
BKBMBL2 0
RWAEN 0
RWA 0
RWBEN 0
RWB 0
In DBG mode, BKAMBH:BKAMBL has no meaning and are forced to 0's. In DBG mode, BKBMBH:BKBMBL are used in full mode to qualify data.
Figure 19-14. Debug Control Register 3 (DBGC3) Table 19-15. DBGC3 Field Descriptions
Field Description
7:6 Breakpoint Mask High Byte for First Address -- In dual or full mode, these bits may be used to mask (disable) BKAMB[H:L] the comparison of the high and/or low bytes of the first address breakpoint. The functionality is as given in Table 19-16. The x:0 case is for a full address compare. When a program page is selected, the full address compare will be based on bits for a 20-bit compare. The registers used for the compare are {DBGCAX[5:0], DBGCAH[5:0], DBGCAL[7:0]}, where DBGAX[5:0] corresponds to PPAGE[5:0] or extended address bits [19:14] and CPU address [13:0]. When a program page is not selected, the full address compare will be based on bits for a 16-bit compare. The registers used for the compare are {DBGCAH[7:0], DBGCAL[7:0]} which corresponds to CPU address [15:0]. Note: This extended address compare scheme causes an aliasing problem in BKP mode in which several physical addresses may match with a single logical address. This problem may be avoided by using DBG mode to generate breakpoints. The 1:0 case is not sensible because it would ignore the high order address and compare the low order and expansion addresses. Logic forces this case to compare all address lines (effectively ignoring the BKAMBH control bit). The 1:1 case is useful for triggering a breakpoint on any access to a particular expansion page. This only makes sense if a program page is being accessed so that the breakpoint trigger will occur only if DBGCAX compares.
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Chapter 19 Debug Module (DBGV1)
Table 19-15. DBGC3 Field Descriptions (continued)
Field Description
5:4 Breakpoint Mask High Byte and Low Byte of Data (Second Address) -- In dual mode, these bits may be BKBMB[H:L] used to mask (disable) the comparison of the high and/or low bytes of the second address breakpoint. The functionality is as given in Table 19-17. The x:0 case is for a full address compare. When a program page is selected, the full address compare will be based on bits for a 20-bit compare. The registers used for the compare are {DBGCBX[5:0], DBGCBH[5:0], DBGCBL[7:0]} where DBGCBX[5:0] corresponds to PPAGE[5:0] or extended address bits [19:14] and CPU address [13:0]. When a program page is not selected, the full address compare will be based on bits for a 16-bit compare. The registers used for the compare are {DBGCBH[7:0], DBGCBL[7:0]} which corresponds to CPU address [15:0]. Note: This extended address compare scheme causes an aliasing problem in BKP mode in which several physical addresses may match with a single logical address. This problem may be avoided by using DBG mode to generate breakpoints. The 1:0 case is not sensible because it would ignore the high order address and compare the low order and expansion addresses. Logic forces this case to compare all address lines (effectively ignoring the BKBMBH control bit). The 1:1 case is useful for triggering a breakpoint on any access to a particular expansion page. This only makes sense if a program page is being accessed so that the breakpoint trigger will occur only if DBGCBX compares. In full mode, these bits may be used to mask (disable) the comparison of the high and/or low bytes of the data breakpoint. The functionality is as given in Table 19-18. 3 RWAEN Read/Write Comparator A Enable Bit -- The RWAEN bit controls whether read or write comparison is enabled for comparator A. See Section 19.4.2.1.1, "Read or Write Comparison," for more information. This bit is not useful for tagged operations. 0 Read/Write is not used in comparison 1 Read/Write is used in comparison Read/Write Comparator A Value Bit -- The RWA bit controls whether read or write is used in compare for comparator A. The RWA bit is not used if RWAEN = 0. 0 Write cycle will be matched 1 Read cycle will be matched Read/Write Comparator B Enable Bit -- The RWBEN bit controls whether read or write comparison is enabled for comparator B. See Section 19.4.2.1.1, "Read or Write Comparison," for more information. This bit is not useful for tagged operations. 0 Read/Write is not used in comparison 1 Read/Write is used in comparison Read/Write Comparator B Value Bit -- The RWB bit controls whether read or write is used in compare for comparator B. The RWB bit is not used if RWBEN = 0. 0 Write cycle will be matched 1 Read cycle will be matched Note: RWB and RWBEN are not used in full mode.
2 RWA
1 RWBEN
0 RWB
Table 19-16. Breakpoint Mask Bits for First Address
BKAMBH:BKAMBL x:0 0:1 1:1
1
Address Compare Full address compare 256 byte address range 16K byte address range
DBGCAX Yes1 Yes1 Yes
1
DBGCAH Yes Yes No
DBGCAL Yes No No
If PPAGE is selected.
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Chapter 19 Debug Module (DBGV1)
Table 19-17. Breakpoint Mask Bits for Second Address (Dual Mode)
BKBMBH:BKBMBL x:0 0:1 1:1
1
Address Compare Full address compare 256 byte address range 16K byte address range
DBGCBX Yes
1
DBGCBH Yes Yes No
DBGCBL Yes No No
Yes1 Yes1
If PPAGE is selected.
Table 19-18. Breakpoint Mask Bits for Data Breakpoints (Full Mode)
BKBMBH:BKBMBL 0:0 0:1 1:0 1:1
1
Data Compare High and low byte compare High byte Low byte No compare
DBGCBX No No
1 1
DBGCBH Yes Yes No No
DBGCBL Yes No Yes No
No1 No1
Expansion addresses for breakpoint B are not applicable in this mode.
MC9S12HZ256 Data Sheet, Rev. 2.05 552 Freescale Semiconductor
Chapter 19 Debug Module (DBGV1)
19.3.2.9
Debug Comparator A Extended Register (DBGCAX)
7 6 5 4 3 2 1 0
R PAGSEL W Reset 0 0 0 0 0 0 0 0 EXTCMP
Figure 19-15. Debug Comparator A Extended Register (DBGCAX) Table 19-19. DBGCAX Field Descriptions
Field 7:6 PAGSEL Description Page Selector Field -- If DBGEN is set in DBGC1, then PAGSEL selects the type of paging as shown in Table 19-20. DPAGE and EPAGE are not yet implemented so the value in bit 7 will be ignored (i.e., PAGSEL values of 10 and 11 will be interpreted as values of 00 and 01, respectively). In BKP mode, PAGSEL has no meaning and EXTCMP[5:0] are compared to address bits [19:14] if the address is in the FLASH/ROM memory space. 5:0 EXTCMP Comparator A Extended Compare Bits -- The EXTCMP bits are used as comparison address bits as shown in Table 19-20 along with the appropriate PPAGE, DPAGE, or EPAGE signal from the core.
Table 19-20. Comparator A or B Compares
Mode BKP
1
EXTCMP Compare No compare EXTCMP[5:0] = XAB[19:14] No compare EXTCMP[5:0] = XAB[21:16]
High-Byte Compare DBGCxH[7:0] = AB[15:8] DBGCxH[5:0] = AB[13:8] DBGCxH[7:0] = AB[15:8] DBGCxH[7:0] = XAB[15:14], AB[13:8]
Not FLASH/ROM access FLASH/ROM access PAGSEL = 00 PAGSEL = 01
DBG2
1 2
See Figure 19-16. See Figure 19-10 (note that while this figure provides extended comparisons for comparator C, the figure also pertains to comparators A and B in DBG mode only).
PAGSEL DBGCXX 0 0 5 4 EXTCMP 3 2 1 BIT 0
PORTK/XAB
XAB21
XAB20
XAB19
XAB18
XAB17
XAB16
XAB15
XAB14
PPAGE
PIX7
PIX6
PIX5
PIX4
PIX3
PIX2
PIX1
PIX0
SEE NOTE 2 NOTES: 1. In BKP mode, PAGSEL has no functionality. Therefore, set PAGSEL to 00 (reset state). 2. Current HCS12 implementations are limited to six PPAGE bits, PIX[5:0].
Figure 19-16. Comparators A and B Extended Comparison in BKP Mode
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 553
BKP MODE
SEE NOTE 1
Chapter 19 Debug Module (DBGV1)
19.3.2.10 Debug Comparator A Register (DBGCA)
15 14 13 12 11 10 9 8
R Bit 15 W Reset 0 0 0 0 0 0 0 0 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Figure 19-17. Debug Comparator A Register High (DBGCAH)
7 6 5 4 3 2 1 0
R Bit 7 W Reset 0 0 0 0 0 0 0 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Figure 19-18. Debug Comparator A Register Low (DBGCAL) Table 19-21. DBGCA Field Descriptions
Field 15:0 15:0 Description Comparator A Compare Bits -- The comparator A compare bits control whether comparator A compares the address bus bits [15:0] to a logic 1 or logic 0. See Table 19-20. 0 Compare corresponding address bit to a logic 0 1 Compare corresponding address bit to a logic 1
19.3.2.11 Debug Comparator B Extended Register (DBGCBX)
7 6 5 4 3 2 1 0
R PAGSEL W Reset 0 0 0 0 0 0 0 0 EXTCMP
Figure 19-19. Debug Comparator B Extended Register (DBGCBX) Table 19-22. DBGCBX Field Descriptions
Field 7:6 PAGSEL Description Page Selector Field -- If DBGEN is set in DBGC1, then PAGSEL selects the type of paging as shown in Table 19-11. DPAGE and EPAGE are not yet implemented so the value in bit 7 will be ignored (i.e., PAGSEL values of 10 and 11 will be interpreted as values of 00 and 01, respectively.) In BKP mode, PAGSEL has no meaning and EXTCMP[5:0] are compared to address bits [19:14] if the address is in the FLASH/ROM memory space. 5:0 EXTCMP Comparator B Extended Compare Bits -- The EXTCMP bits are used as comparison address bits as shown in Table 19-11 along with the appropriate PPAGE, DPAGE, or EPAGE signal from the core. Also see Table 19-20.
MC9S12HZ256 Data Sheet, Rev. 2.05 554 Freescale Semiconductor
Chapter 19 Debug Module (DBGV1)
19.3.2.12 Debug Comparator B Register (DBGCB)
15 14 13 12 11 10 9 8
R Bit 15 W Reset 0 0 0 0 0 0 0 0 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Figure 19-20. Debug Comparator B Register High (DBGCBH)
7 6 5 4 3 2 1 0
R Bit 7 W Reset 0 0 0 0 0 0 0 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Figure 19-21. Debug Comparator B Register Low (DBGCBL) Table 19-23. DBGCB Field Descriptions
Field 15:0 15:0 Description Comparator B Compare Bits -- The comparator B compare bits control whether comparator B compares the address bus bits [15:0] or data bus bits [15:0] to a logic 1 or logic 0. See Table 19-20. 0 Compare corresponding address bit to a logic 0, compares to data if in Full mode 1 Compare corresponding address bit to a logic 1, compares to data if in Full mode
19.4
Functional Description
This section provides a complete functional description of the DBG module. The DBG module can be configured to run in either of two modes, BKP or DBG. BKP mode is enabled by setting BKABEN in DBGC2. DBG mode is enabled by setting DBGEN in DBGC1. Setting BKABEN in DBGC2 overrides the DBGEN in DBGC1 and prevents DBG mode. If the part is in secure mode, DBG mode cannot be enabled.
19.4.1
DBG Operating in BKP Mode
In BKP mode, the DBG will be fully backwards compatible with the existing BKP_ST12_A module. The DBGC2 register has four additional bits that were not available on existing BKP_ST12_A modules. As long as these bits are written to either all 1s or all 0s, they should be transparent to the user. All 1s would enable comparator C to be used as a breakpoint, but tagging would be enabled. The match address register would be all 0s if not modified by the user. Therefore, code executing at address 0x0000 would have to occur before a breakpoint based on comparator C would happen. The DBG module in BKP mode supports two modes of operation: dual address mode and full breakpoint mode. Within each of these modes, forced or tagged breakpoint types can be used. Forced breakpoints occur at the next instruction boundary if a match occurs and tagged breakpoints allow for breaking just before the tagged instruction executes. The action taken upon a successful match can be to either place the CPU in background debug mode or to initiate a software interrupt.
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Chapter 19 Debug Module (DBGV1)
The breakpoint can operate in dual address mode or full breakpoint mode. Each of these modes is discussed in the subsections below.
19.4.1.1
Dual Address Mode
When dual address mode is enabled, two address breakpoints can be set. Each breakpoint can cause the system to enter background debug mode or to initiate a software interrupt based upon the state of BDM in DBGC2 being logic 1 or logic 0, respectively. BDM requests have a higher priority than SWI requests. No data breakpoints are allowed in this mode. TAGAB in DBGC2 selects whether the breakpoint mode is forced or tagged. The BKxMBH:L bits in DBGC3 select whether or not the breakpoint is matched exactly or is a range breakpoint. They also select whether the address is matched on the high byte, low byte, both bytes, and/or memory expansion. The RWx and RWxEN bits in DBGC3 select whether the type of bus cycle to match is a read, write, or read/write when performing forced breakpoints.
19.4.1.2
Full Breakpoint Mode
Full breakpoint mode requires a match on address and data for a breakpoint to occur. Upon a successful match, the system will enter background debug mode or initiate a software interrupt based upon the state of BDM in DBGC2 being logic 1 or logic 0, respectively. BDM requests have a higher priority than SWI requests. R/W matches are also allowed in this mode. TAGAB in DBGC2 selects whether the breakpoint mode is forced or tagged. When TAGAB is set in DBGC2, only addresses are compared and data is ignored. The BKAMBH:L bits in DBGC3 select whether or not the breakpoint is matched exactly, is a range breakpoint, or is in page space. The BKBMBH:L bits in DBGC3 select whether the data is matched on the high byte, low byte, or both bytes. RWA and RWAEN bits in DBGC2 select whether the type of bus cycle to match is a read or a write when performing forced breakpoints. RWB and RWBEN bits in DBGC2 are not used in full breakpoint mode. NOTE The full trigger mode is designed to be used for either a word access or a byte access, but not both at the same time. Confusing trigger operation (seemingly false triggers or no trigger) can occur if the trigger address occurs in the user program as both byte and word accesses.
19.4.1.3
Breakpoint Priority
Breakpoint operation is first determined by the state of the BDM module. If the BDM module is already active, meaning the CPU is executing out of BDM firmware, breakpoints are not allowed. In addition, while executing a BDM TRACE command, tagging into BDM is not allowed. If BDM is not active, the breakpoint will give priority to BDM requests over SWI requests. This condition applies to both forced and tagged breakpoints. In all cases, BDM related breakpoints will have priority over those generated by the Breakpoint sub-block. This priority includes breakpoints enabled by the TAGLO and TAGHI external pins of the system that interface with the BDM directly and whose signal information passes through and is used by the breakpoint sub-block.
MC9S12HZ256 Data Sheet, Rev. 2.05 556 Freescale Semiconductor
Chapter 19 Debug Module (DBGV1)
NOTE BDM should not be entered from a breakpoint unless the ENABLE bit is set in the BDM. Even if the ENABLE bit in the BDM is cleared, the CPU actually executes the BDM firmware code. It checks the ENABLE and returns if ENABLE is not set. If the BDM is not serviced by the monitor then the breakpoint would be re-asserted when the BDM returns to normal CPU flow. There is no hardware to enforce restriction of breakpoint operation if the BDM is not enabled. When program control returns from a tagged breakpoint through an RTI or a BDM GO command, it will return to the instruction whose tag generated the breakpoint. Unless breakpoints are disabled or modified in the service routine or active BDM session, the instruction will be tagged again and the breakpoint will be repeated. In the case of BDM breakpoints, this situation can also be avoided by executing a TRACE1 command before the GO to increment the program flow past the tagged instruction.
19.4.1.4
Using Comparator C in BKP Mode
The original BKP_ST12_A module supports two breakpoints. The DBG_ST12_A module can be used in BKP mode and allow a third breakpoint using comparator C. Four additional bits, BKCEN, TAGC, RWCEN, and RWC in DBGC2 in conjunction with additional comparator C address registers, DBGCCX, DBGCCH, and DBGCCL allow the user to set up a third breakpoint. Using PAGSEL in DBGCCX for expanded memory will work differently than the way paged memory is done using comparator A and B in BKP mode. See Section 19.3.2.5, "Debug Comparator C Extended Register (DBGCCX)," for more information on using comparator C.
19.4.2
DBG Operating in DBG Mode
Enabling the DBG module in DBG mode, allows the arming, triggering, and storing of data in the trace buffer and can be used to cause CPU breakpoints. The DBG module is made up of three main blocks, the comparators, trace buffer control logic, and the trace buffer. NOTE In general, there is a latency between the triggering event appearing on the bus and being detected by the DBG circuitry. In general, tagged triggers will be more predictable than forced triggers.
19.4.2.1
Comparators
The DBG contains three comparators, A, B, and C. Comparator A compares the core address bus with the address stored in DBGCAH and DBGCAL. Comparator B compares the core address bus with the address stored in DBGCBH and DBGCBL except in full mode, where it compares the data buses to the data stored in DBGCBH and DBGCBL. Comparator C can be used as a breakpoint generator or as the address comparison unit in the loop1 mode. Matches on comparator A, B, and C are signaled to the trace buffer
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Chapter 19 Debug Module (DBGV1)
control (TBC) block. When PAGSEL = 01, registers DBGCAX, DBGCBX, and DBGCCX are used to match the upper addresses as shown in Table 19-11. NOTE If a tagged-type C breakpoint is set at the same address as an A/B tagged-type trigger (including the initial entry in an inside or outside range trigger), the C breakpoint will have priority and the trigger will not be recognized. 19.4.2.1.1 Read or Write Comparison
Read or write comparisons are useful only with TRGSEL = 0, because only opcodes should be tagged as they are "read" from memory. RWAEN and RWBEN are ignored when TRGSEL = 1. In full modes ("A and B" and "A and not B") RWAEN and RWA are used to select read or write comparisons for both comparators A and B. Table 19-24 shows the effect for RWAEN, RWA, and RW on the DBGCB comparison conditions. The RWBEN and RWB bits are not used and are ignored in full modes.
Table 19-24. Read or Write Comparison Logic Table
RWAEN bit 0 0 1 1 1 1 RWA bit x x 0 0 1 1 RW signal 0 1 0 1 0 1 Comment Write data bus Read data bus Write data bus No data bus compare since RW=1 No data bus compare since RW=0 Read data bus
19.4.2.1.2
Trigger Selection
The TRGSEL bit in DBGC1 is used to determine the triggering condition in DBG mode. TRGSEL applies to both trigger A and B except in the event only trigger modes. By setting TRGSEL, the comparators A and B will qualify a match with the output of opcode tracking logic and a trigger occurs before the tagged instruction executes (tagged-type trigger). With the TRGSEL bit cleared, a comparator match forces a trigger when the matching condition occurs (force-type trigger). NOTE If the TRGSEL is set, the address stored in the comparator match address registers must be an opcode address for the trigger to occur.
19.4.2.2
Trace Buffer Control (TBC)
The TBC is the main controller for the DBG module. Its function is to decide whether data should be stored in the trace buffer based on the trigger mode and the match signals from the comparator. The TBC also determines whether a request to break the CPU should occur.
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Chapter 19 Debug Module (DBGV1)
19.4.2.3
Begin- and End-Trigger
The definitions of begin- and end-trigger as used in the DBG module are as follows: * Begin-trigger: Storage in trace buffer occurs after the trigger and continues until 64 locations are filled. * End-trigger: Storage in trace buffer occurs until the trigger, with the least recent data falling out of the trace buffer if more than 64 words are collected.
19.4.2.4
Arming the DBG Module
In DBG mode, arming occurs by setting DBGEN and ARM in DBGC1. The ARM bit in DBGC1 is cleared when the trigger condition is met in end-trigger mode or when the Trace Buffer is filled in begin-trigger mode. The TBC logic determines whether a trigger condition has been met based on the trigger mode and the trigger selection.
19.4.2.5
Trigger Modes
The DBG module supports nine trigger modes. The trigger modes are encoded as shown in Table 19-6. The trigger mode is used as a qualifier for either starting or ending the storing of data in the trace buffer. When the match condition is met, the appropriate flag A or B is set in DBGSC. Arming the DBG module clears the A, B, and C flags in DBGSC. In all trigger modes except for the event-only modes and DETAIL capture mode, change-of-flow addresses are stored in the trace buffer. In the event-only modes only the value on the data bus at the trigger event B will be stored. In DETAIL capture mode address and data for all cycles except program fetch (P) and free (f) cycles are stored in trace buffer. 19.4.2.5.1 A Only
In the A only trigger mode, if the match condition for A is met, the A flag in DBGSC is set and a trigger occurs. 19.4.2.5.2 A or B
In the A or B trigger mode, if the match condition for A or B is met, the corresponding flag in DBGSC is set and a trigger occurs. 19.4.2.5.3 A then B
In the A then B trigger mode, the match condition for A must be met before the match condition for B is compared. When the match condition for A or B is met, the corresponding flag in DBGSC is set. The trigger occurs only after A then B have matched. NOTE When tagging and using A then B, if addresses A and B are close together, then B may not complete the trigger sequence. This occurs when A and B are in the instruction queue at the same time. Basically the A trigger has not yet occurred, so the B instruction is not tagged. Generally, if address B is at
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Chapter 19 Debug Module (DBGV1)
least six addresses higher than address A (or B is lower than A) and there are not changes of flow to put these in the queue at the same time, then this operation should trigger properly. 19.4.2.5.4 Event-Only B (Store Data)
In the event-only B trigger mode, if the match condition for B is met, the B flag in DBGSC is set and a trigger occurs. The event-only B trigger mode is considered a begin-trigger type and the BEGIN bit in DBGC1 is ignored. Event-only B is incompatible with instruction tagging (TRGSEL = 1), and thus the value of TRGSEL is ignored. Please refer to Section 19.4.2.7, "Storage Memory," for more information. This trigger mode is incompatible with the detail capture mode so the detail capture mode will have priority. TRGSEL and BEGIN will not be ignored and this trigger mode will behave as if it were "B only". 19.4.2.5.5 A then Event-Only B (Store Data)
In the A then event-only B trigger mode, the match condition for A must be met before the match condition for B is compared, after the A match has occurred, a trigger occurs each time B matches. When the match condition for A or B is met, the corresponding flag in DBGSC is set. The A then event-only B trigger mode is considered a begin-trigger type and BEGIN in DBGC1 is ignored. TRGSEL in DBGC1 applies only to the match condition for A. Please refer to Section 19.4.2.7, "Storage Memory," for more information. This trigger mode is incompatible with the detail capture mode so the detail capture mode will have priority. TRGSEL and BEGIN will not be ignored and this trigger mode will be the same as A then B. 19.4.2.5.6 A and B (Full Mode)
In the A and B trigger mode, comparator A compares to the address bus and comparator B compares to the data bus. In the A and B trigger mode, if the match condition for A and B happen on the same bus cycle, both the A and B flags in the DBGSC register are set and a trigger occurs. If TRGSEL = 1, only matches from comparator A are used to determine if the trigger condition is met and comparator B matches are ignored. If TRGSEL = 0, full-word data matches on an odd address boundary (misaligned access) do not work unless the access is to a RAM that manages misaligned accesses in a single clock cycle (which is typical of RAM modules used in HCS12 MCUs). 19.4.2.5.7 A and Not B (Full Mode)
In the A and not B trigger mode, comparator A compares to the address bus and comparator B compares to the data bus. In the A and not B trigger mode, if the match condition for A and not B happen on the same bus cycle, both the A and B flags in DBGSC are set and a trigger occurs. If TRGSEL = 1, only matches from comparator A are used to determine if the trigger condition is met and comparator B matches are ignored. As described in Section 19.4.2.5.6, "A and B (Full Mode)," full-word data compares on misaligned accesses will not match expected data (and thus will cause a trigger in this mode) unless the access is to a RAM that manages misaligned accesses in a single clock cycle.
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Chapter 19 Debug Module (DBGV1)
19.4.2.5.8
Inside Range (A address B)
In the inside range trigger mode, if the match condition for A and B happen on the same bus cycle, both the A and B flags in DBGSC are set and a trigger occurs. If a match condition on only A or only B occurs no flags are set. If TRGSEL = 1, the inside range is accurate only to word boundaries. If TRGSEL = 0, an aligned word access which straddles the range boundary will cause a trigger only if the aligned address is within the range. 19.4.2.5.9 Outside Range (address < A or address > B)
In the outside range trigger mode, if the match condition for A or B is met, the corresponding flag in DBGSC is set and a trigger occurs. If TRGSEL = 1, the outside range is accurate only to word boundaries. If TRGSEL = 0, an aligned word access which straddles the range boundary will cause a trigger only if the aligned address is outside the range. 19.4.2.5.10 Control Bit Priorities The definitions of some of the control bits are incompatible with each other. Table 19-25 and the notes associated with it summarize how these incompatibilities are managed: * Read/write comparisons are not compatible with TRGSEL = 1. Therefore, RWAEN and RWBEN are ignored. * Event-only trigger modes are always considered a begin-type trigger. See Section 19.4.2.8.1, "Storing with Begin-Trigger," and Section 19.4.2.8.2, "Storing with End-Trigger." * Detail capture mode has priority over the event-only trigger/capture modes. Therefore, event-only modes have no meaning in detail mode and their functions default to similar trigger modes.
Table 19-25. Resolution of Mode Conflicts
Normal / Loop1 Mode Tag A only A or B A then B Event-only B A then event-only B A and B (full mode) A and not B (full mode) Inside range Outside range 1 2 5 5 6 6 1, 3 4 5 5 6 6 3 4 Force Tag Force Detail
1 -- Ignored -- same as force 2 -- Ignored for comparator B 3 -- Reduces to effectively "B only" 4 -- Works same as A then B 5 -- Reduces to effectively "A only" -- B not compared 6 -- Only accurate to word boundaries
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Chapter 19 Debug Module (DBGV1)
19.4.2.6
Capture Modes
The DBG in DBG mode can operate in four capture modes. These modes are described in the following subsections. 19.4.2.6.1 Normal Mode
In normal mode, the DBG module uses comparator A and B as triggering devices. Change-of-flow information or data will be stored depending on TRG in DBGSC. 19.4.2.6.2 Loop1 Mode
The intent of loop1 mode is to prevent the trace buffer from being filled entirely with duplicate information from a looping construct such as delays using the DBNE instruction or polling loops using BRSET/BRCLR instructions. Immediately after address information is placed in the trace buffer, the DBG module writes this value into the C comparator and the C comparator is placed in ignore address mode. This will prevent duplicate address entries in the trace buffer resulting from repeated bit-conditional branches. Comparator C will be cleared when the ARM bit is set in loop1 mode to prevent the previous contents of the register from interfering with loop1 mode operation. Breakpoints based on comparator C are disabled. Loop1 mode only inhibits duplicate source address entries that would typically be stored in most tight looping constructs. It will not inhibit repeated entries of destination addresses or vector addresses, because repeated entries of these would most likely indicate a bug in the user's code that the DBG module is designed to help find. NOTE In certain very tight loops, the source address will have already been fetched again before the C comparator is updated. This results in the source address being stored twice before further duplicate entries are suppressed. This condition occurs with branch-on-bit instructions when the branch is fetched by the first P-cycle of the branch or with loop-construct instructions in which the branch is fetched with the first or second P cycle. See examples below:
LOOP INCX ; 1-byte instruction fetched by 1st P-cycle of BRCLR BRCLR CMPTMP,#$0c,LOOP ; the BRCLR instruction also will be fetched by 1st P-cycle of BRCLR * A,LOOP2 ; 2-byte instruction fetched by 1st P-cycle of DBNE ; 1-byte instruction fetched by 2nd P-cycle of DBNE ; this instruction also fetched by 2nd P-cycle of DBNE
LOOP2 BRN NOP DBNE
NOTE Loop1 mode does not support paged memory, and inhibits duplicate entries in the trace buffer based solely on the CPU address. There is a remote possibility of an erroneous address match if program flow alternates between paged and unpaged memory space.
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Chapter 19 Debug Module (DBGV1)
19.4.2.6.3
Detail Mode
In the detail mode, address and data for all cycles except program fetch (P) and free (f) cycles are stored in trace buffer. This mode is intended to supply additional information on indexed, indirect addressing modes where storing only the destination address would not provide all information required for a user to determine where his code was in error. 19.4.2.6.4 Profile Mode
This mode is intended to allow a host computer to poll a running target and provide a histogram of program execution. Each read of the trace buffer address will return the address of the last instruction executed. The DBGCNT register is not incremented and the trace buffer does not get filled. The ARM bit is not used and all breakpoints and all other debug functions will be disabled.
19.4.2.7
Storage Memory
The storage memory is a 64 words deep by 16-bits wide dual port RAM array. The CPU accesses the RAM array through a single memory location window (DBGTBH:DBGTBL). The DBG module stores trace information in the RAM array in a circular buffer format. As data is read via the CPU, a pointer into the RAM will increment so that the next CPU read will receive fresh information. In all trigger modes except for event-only and detail capture mode, the data stored in the trace buffer will be change-of-flow addresses. change-of-flow addresses are defined as follows: * Source address of conditional branches (long, short, BRSET, and loop constructs) taken * Destination address of indexed JMP, JSR, and CALL instruction * Destination address of RTI, RTS, and RTC instructions * Vector address of interrupts except for SWI and BDM vectors In the event-only trigger modes only the 16-bit data bus value corresponding to the event is stored. In the detail capture mode, address and then data are stored for all cycles except program fetch (P) and free (f) cycles.
19.4.2.8
19.4.2.8.1
Storing Data in Memory Storage Buffer
Storing with Begin-Trigger
Storing with begin-trigger can be used in all trigger modes. When DBG mode is enabled and armed in the begin-trigger mode, data is not stored in the trace buffer until the trigger condition is met. As soon as the trigger condition is met, the DBG module will remain armed until 64 words are stored in the trace buffer. If the trigger is at the address of the change-of-flow instruction the change-of-flow associated with the trigger event will be stored in the trace buffer. 19.4.2.8.2 Storing with End-Trigger
Storing with end-trigger cannot be used in event-only trigger modes. When DBG mode is enabled and armed in the end-trigger mode, data is stored in the trace buffer until the trigger condition is met. When the trigger condition is met, the DBG module will become de-armed and no more data will be stored. If
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Chapter 19 Debug Module (DBGV1)
the trigger is at the address of a change-of-flow address the trigger event will not be stored in the trace buffer.
19.4.2.9
Reading Data from Trace Buffer
The data stored in the trace buffer can be read using either the background debug module (BDM) module or the CPU provided the DBG module is enabled and not armed. The trace buffer data is read out first-in first-out. By reading CNT in DBGCNT the number of valid words can be determined. CNT will not decrement as data is read from DBGTBH:DBGTBL. The trace buffer data is read by reading DBGTBH:DBGTBL with a 16-bit read. Each time DBGTBH:DBGTBL is read, a pointer in the DBG will be incremented to allow reading of the next word. Reading the trace buffer while the DBG module is armed will return invalid data and no shifting of the RAM pointer will occur. NOTE The trace buffer should be read with the DBG module enabled and in the same capture mode that the data was recorded. The contents of the trace buffer counter register (DBGCNT) are resolved differently in detail mode verses the other modes and may lead to incorrect interpretation of the trace buffer data.
19.4.3
Breakpoints
There are two ways of getting a breakpoint in DBG mode. One is based on the trigger condition of the trigger mode using comparator A and/or B, and the other is using comparator C. External breakpoints generated using the TAGHI and TAGLO external pins are disabled in DBG mode.
19.4.3.1
Breakpoint Based on Comparator A and B
A breakpoint request to the CPU can be enabled by setting DBGBRK in DBGC1. The value of BEGIN in DBGC1 determines when the breakpoint request to the CPU will occur. When BEGIN in DBGC1 is set, begin-trigger is selected and the breakpoint request will not occur until the trace buffer is filled with 64 words. When BEGIN in DBGC1 is cleared, end-trigger is selected and the breakpoint request will occur immediately at the trigger cycle. There are two types of breakpoint requests supported by the DBG module, tagged and forced. Tagged breakpoints are associated with opcode addresses and allow breaking just before a specific instruction executes. Forced breakpoints are not associated with opcode addresses and allow breaking at the next instruction boundary. The type of breakpoint based on comparators A and B is determined by TRGSEL in the DBGC1 register (TRGSEL = 1 for tagged breakpoint, TRGSEL = 0 for forced breakpoint). Table 19-26 illustrates the type of breakpoint that will occur based on the debug run.
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Chapter 19 Debug Module (DBGV1)
Table 19-26. Breakpoint Setup
BEGIN 0 0 0 0 1 1 1 1 TRGSEL 0 0 1 1 0 0 1 1 DBGBRK 0 1 0 1 0 1 0 1 Type of Debug Run Fill trace buffer until trigger address (no CPU breakpoint -- keep running) Fill trace buffer until trigger address, then a forced breakpoint request occurs Fill trace buffer until trigger opcode is about to execute (no CPU breakpoint -- keep running) Fill trace buffer until trigger opcode about to execute, then a tagged breakpoint request occurs Start trace buffer at trigger address (no CPU breakpoint -- keep running) Start trace buffer at trigger address, a forced breakpoint request occurs when trace buffer is full Start trace buffer at trigger opcode (no CPU breakpoint -- keep running) Start trace buffer at trigger opcode, a forced breakpoint request occurs when trace buffer is full
19.4.3.2
Breakpoint Based on Comparator C
A breakpoint request to the CPU can be created if BKCEN in DBGC2 is set. Breakpoints based on a successful comparator C match can be accomplished regardless of the mode of operation for comparator A or B, and do not affect the status of the ARM bit. TAGC in DBGC2 is used to select either tagged or forced breakpoint requests for comparator C. Breakpoints based on comparator C are disabled in LOOP1 mode. NOTE Because breakpoints cannot be disabled when the DBG is armed, one must be careful to avoid an "infinite breakpoint loop" when using tagged-type C breakpoints while the DBG is armed. If BDM breakpoints are selected, executing a TRACE1 instruction before the GO instruction is the recommended way to avoid re-triggering a breakpoint if one does not wish to de-arm the DBG. If SWI breakpoints are selected, disarming the DBG in the SWI interrupt service routine is the recommended way to avoid re-triggering a breakpoint.
19.5
Resets
The DBG module is disabled after reset. The DBG module cannot cause a MCU reset.
19.6
Interrupts
The DBG contains one interrupt source. If a breakpoint is requested and BDM in DBGC2 is cleared, an SWI interrupt will be generated.
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Chapter 20 Interrupt (INTV1)
20.1 Introduction
This section describes the functionality of the interrupt (INT) sub-block of the S12 core platform. A block diagram of the interrupt sub-block is shown in Figure 20-1.
INT
WRITE DATA BUS
HPRIO (OPTIONAL)
HIGHEST PRIORITY I-INTERRUPT
INTERRUPTS XMASK IMASK INTERRUPT INPUT REGISTERS AND CONTROL REGISTERS READ DATA BUS
WAKEUP HPRIO VECTOR
QUALIFIED INTERRUPTS
INTERRUPT PENDING RESET FLAGS VECTOR REQUEST PRIORITY DECODER VECTOR ADDRESS
Figure 20-1. INT Block Diagram
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Chapter 20 Interrupt (INTV1)
The interrupt sub-block decodes the priority of all system exception requests and provides the applicable vector for processing the exception. The INT supports I-bit maskable and X-bit maskable interrupts, a non-maskable unimplemented opcode trap, a non-maskable software interrupt (SWI) or background debug mode request, and three system reset vector requests. All interrupt related exception requests are managed by the interrupt sub-block (INT).
20.1.1
Features
The INT includes these features: * Provides two to 122 I-bit maskable interrupt vectors (0xFF00-0xFFF2) * Provides one X-bit maskable interrupt vector (0xFFF4) * Provides a non-maskable software interrupt (SWI) or background debug mode request vector (0xFFF6) * Provides a non-maskable unimplemented opcode trap (TRAP) vector (0xFFF8) * Provides three system reset vectors (0xFFFA-0xFFFE) (reset, CMR, and COP) * Determines the appropriate vector and drives it onto the address bus at the appropriate time * Signals the CPU that interrupts are pending * Provides control registers which allow testing of interrupts * Provides additional input signals which prevents requests for servicing I and X interrupts * Wakes the system from stop or wait mode when an appropriate interrupt occurs or whenever XIRQ is active, even if XIRQ is masked * Provides asynchronous path for all I and X interrupts, (0xFF00-0xFFF4) * (Optional) selects and stores the highest priority I interrupt based on the value written into the HPRIO register
20.1.2
Modes of Operation
The functionality of the INT sub-block in various modes of operation is discussed in the subsections that follow. * Normal operation The INT operates the same in all normal modes of operation. * Special operation Interrupts may be tested in special modes through the use of the interrupt test registers. * Emulation modes The INT operates the same in emulation modes as in normal modes. * Low power modes See Section 20.4.1, "Low-Power Modes," for details
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Chapter 20 Interrupt (INTV1)
20.2
External Signal Description
Most interfacing with the interrupt sub-block is done within the core. However, the interrupt does receive direct input from the multiplexed external bus interface (MEBI) sub-block of the core for the IRQ and XIRQ pin data.
20.3
Memory Map and Register Definition
Detailed descriptions of the registers and associated bits are given in the subsections that follow.
20.3.1
Module Memory Map
Table 20-1. INT Memory Map
Address Offset 0x0015 0x0016 0x001F Use Interrupt Test Control Register (ITCR) Interrupt Test Registers (ITEST) Highest Priority Interrupt (Optional) (HPRIO) Access R/W R/W R/W
20.3.2
20.3.2.1
Register Descriptions
Interrupt Test Control Register
7 6 5 4 3 2 1 0
R W Reset
0
0
0 WRTINT ADR3 1 ADR2 1 ADR1 1 ADR0 1
0
0
0
0
= Unimplemented or Reserved
Figure 20-2. Interrupt Test Control Register (ITCR)
Read: See individual bit descriptions Write: See individual bit descriptions
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Chapter 20 Interrupt (INTV1)
Table 20-2. ITCR Field Descriptions
Field 4 WRTINT Description Write to the Interrupt Test Registers Read: anytime Write: only in special modes and with I-bit mask and X-bit mask set. 0 Disables writes to the test registers; reads of the test registers will return the state of the interrupt inputs. 1 Disconnect the interrupt inputs from the priority decoder and use the values written into the ITEST registers instead. Note: Any interrupts which are pending at the time that WRTINT is set will remain until they are overwritten. Test Register Select Bits Read: anytime Write: anytime These bits determine which test register is selected on a read or write. The hexadecimal value written here will be the same as the upper nibble of the lower byte of the vector selects. That is, an "F" written into ADR[3:0] will select vectors 0xFFFE-0xFFF0 while a "7" written to ADR[3:0] will select vectors 0xFF7E-0xFF70.
3:0 ADR[3:0]
20.3.2.2
Interrupt Test Registers
7 6 5 4 3 2 1 0
R INTE W Reset 0 0 0 0 0 0 0 0 INTC INTA INT8 INT6 INT4 INT2 INT0
= Unimplemented or Reserved
Figure 20-3. Interrupt TEST Registers (ITEST)
Read: Only in special modes. Reads will return either the state of the interrupt inputs of the interrupt sub-block (WRTINT = 0) or the values written into the TEST registers (WRTINT = 1). Reads will always return 0s in normal modes. Write: Only in special modes and with WRTINT = 1 and CCR I mask = 1.
Table 20-3. ITEST Field Descriptions
Field 7:0 INT[E:0] Description Interrupt TEST Bits -- These registers are used in special modes for testing the interrupt logic and priority independent of the system configuration. Each bit is used to force a specific interrupt vector by writing it to a logic 1 state. Bits are named INTE through INT0 to indicate vectors 0xFFxE through 0xFFx0. These bits can be written only in special modes and only with the WRTINT bit set (logic 1) in the interrupt test control register (ITCR). In addition, I interrupts must be masked using the I bit in the CCR. In this state, the interrupt input lines to the interrupt sub-block will be disconnected and interrupt requests will be generated only by this register. These bits can also be read in special modes to view that an interrupt requested by a system block (such as a peripheral block) has reached the INT module. There is a test register implemented for every eight interrupts in the overall system. All of the test registers share the same address and are individually selected using the value stored in the ADR[3:0] bits of the interrupt test control register (ITCR). Note: When ADR[3:0] have the value of 0x000F, only bits 2:0 in the ITEST register will be accessible. That is, vectors higher than 0xFFF4 cannot be tested using the test registers and bits 7:3 will always read as a logic 0. If ADR[3:0] point to an unimplemented test register, writes will have no effect and reads will always return a logic 0 value.
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Chapter 20 Interrupt (INTV1)
20.3.2.3
Highest Priority I Interrupt (Optional)
7 6 5 4 3 2 1 0
R PSEL7 W Reset 1 1 1 1 0 0 1 PSEL6 PSEL5 PSEL4 PSEL3 PSEL2 PSEL1
0
0
= Unimplemented or Reserved
Figure 20-4. Highest Priority I Interrupt Register (HPRIO)
Read: Anytime Write: Only if I mask in CCR = 1
Table 20-4. HPRIO Field Descriptions
Field 7:1 PSEL[7:1] Description Highest Priority I Interrupt Select Bits -- The state of these bits determines which I-bit maskable interrupt will be promoted to highest priority (of the I-bit maskable interrupts). To promote an interrupt, the user writes the least significant byte of the associated interrupt vector address to this register. If an unimplemented vector address or a non I-bit masked vector address (value higher than 0x00F2) is written, IRQ (0xFFF2) will be the default highest priority interrupt.
20.4
Functional Description
The interrupt sub-block processes all exception requests made by the CPU. These exceptions include interrupt vector requests and reset vector requests. Each of these exception types and their overall priority level is discussed in the subsections below.
20.4.1
Low-Power Modes
The INT does not contain any user-controlled options for reducing power consumption. The operation of the INT in low-power modes is discussed in the following subsections.
20.4.1.1
Operation in Run Mode
The INT does not contain any options for reducing power in run mode.
20.4.1.2
Operation in Wait Mode
Clocks to the INT can be shut off during system wait mode and the asynchronous interrupt path will be used to generate the wake-up signal upon recognition of a valid interrupt or any XIRQ request.
20.4.1.3
Operation in Stop Mode
Clocks to the INT can be shut off during system stop mode and the asynchronous interrupt path will be used to generate the wake-up signal upon recognition of a valid interrupt or any XIRQ request.
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Chapter 20 Interrupt (INTV1)
20.5
Resets
The INT supports three system reset exception request types: normal system reset or power-on-reset request, crystal monitor reset request, and COP watchdog reset request. The type of reset exception request must be decoded by the system and the proper request made to the core. The INT will then provide the service routine address for the type of reset requested.
20.6
Interrupts
As shown in the block diagram in Figure 20-1, the INT contains a register block to provide interrupt status and control, an optional highest priority I interrupt (HPRIO) block, and a priority decoder to evaluate whether pending interrupts are valid and assess their priority.
20.6.1
Interrupt Registers
The INT registers are accessible only in special modes of operation and function as described in Section 20.3.2.1, "Interrupt Test Control Register," and Section 20.3.2.2, "Interrupt Test Registers," previously.
20.6.2
Highest Priority I-Bit Maskable Interrupt
When the optional HPRIO block is implemented, the user is allowed to promote a single I-bit maskable interrupt to be the highest priority I interrupt. The HPRIO evaluates all interrupt exception requests and passes the HPRIO vector to the priority decoder if the highest priority I interrupt is active. RTI replaces the promoted interrupt source.
20.6.3
Interrupt Priority Decoder
The priority decoder evaluates all interrupts pending and determines their validity and priority. When the CPU requests an interrupt vector, the decoder will provide the vector for the highest priority interrupt request. Because the vector is not supplied until the CPU requests it, it is possible that a higher priority interrupt request could override the original exception that caused the CPU to request the vector. In this case, the CPU will receive the highest priority vector and the system will process this exception instead of the original request. NOTE Care must be taken to ensure that all exception requests remain active until the system begins execution of the applicable service routine; otherwise, the exception request may not be processed. If for any reason the interrupt source is unknown (e.g., an interrupt request becomes inactive after the interrupt has been recognized but prior to the vector request), the vector address will default to that of the last valid interrupt that existed during the particular interrupt sequence. If the CPU requests an interrupt vector when there has never been a pending interrupt request, the INT will provide the software interrupt (SWI) vector address.
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Chapter 20 Interrupt (INTV1)
20.7
Exception Priority
The priority (from highest to lowest) and address of all exception vectors issued by the INT upon request by the CPU is shown in Table 20-5.
Table 20-5. Exception Vector Map and Priority
Vector Address 0xFFFE-0xFFFF 0xFFFC-0xFFFD 0xFFFA-0xFFFB 0xFFF8-0xFFF9 0xFFF6-0xFFF7 0xFFF4-0xFFF5 0xFFF2-0xFFF3 0xFFF0-0xFF00 System reset Crystal monitor reset COP reset Unimplemented opcode trap Software interrupt instruction (SWI) or BDM vector request XIRQ signal IRQ signal Device-specific I-bit maskable interrupt sources (priority in descending order) Source
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Chapter 20 Interrupt (INTV1)
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Chapter 21 Multiplexed External Bus Interface (MEBIV3)
21.1 Introduction
This section describes the functionality of the multiplexed external bus interface (MEBI) sub-block of the S12 core platform. The functionality of the module is closely coupled with the S12 CPU and the memory map controller (MMC) sub-blocks. Figure 21-1 is a block diagram of the MEBI. In Figure 21-1, the signals on the right hand side represent pins that are accessible externally. On some chips, these may not all be bonded out. The MEBI sub-block of the core serves to provide access and/or visibility to internal core data manipulation operations including timing reference information at the external boundary of the core and/or system. Depending upon the system operating mode and the state of bits within the control registers of the MEBI, the internal 16-bit read and write data operations will be represented in 8-bit or 16-bit accesses externally. Using control information from other blocks within the system, the MEBI will determine the appropriate type of data access to be generated.
21.1.1
Features
The block name includes these distinctive features: * External bus controller with four 8-bit ports A,B, E, and K * Data and data direction registers for ports A, B, E, and K when used as general-purpose I/O * Control register to enable/disable alternate functions on ports E and K * Mode control register * Control register to enable/disable pull resistors on ports A, B, E, and K * Control register to enable/disable reduced output drive on ports A, B, E, and K * Control register to configure external clock behavior * Control register to configure IRQ pin operation * Logic to capture and synchronize external interrupt pin inputs
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Chapter 21 Multiplexed External Bus Interface (MEBIV3)
REGS
Port K
ADDR
PK[7:0]/ECS/XCS/X[19:14]
Internal Bus
Data[15:0]
EXT BUS I/F CTL
ADDR DATA
Port A
Addr[19:0]
PA[7:0]/A[15:8]/ D[15:8]/D[7:0]
(Control)
Port B
ADDR
PB[7:0]/A[7:0]/ D[7:0]
DATA
PE[7:2]/NOACC/ IPIPE1/MODB/CLKTO IPIPE0/MODA/ ECLK/ LSTRB/TAGLO R/W PE1/IRQ PE0/XIRQ
ECLK CTL
CPU pipe info IRQ interrupt XIRQ interrupt
PIPE CTL IRQ CTL TAG CTL
mode
BDM tag info
Port E
BKGD
BKGD/MODC/TAGHI
Control signal(s) Data signal (unidirectional) Data signal (bidirectional) Data bus (unidirectional) Data bus (bidirectional)
Figure 21-1. MEBI Block Diagram
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Chapter 21 Multiplexed External Bus Interface (MEBIV3)
21.1.2
*
Modes of Operation
*
*
*
*
*
*
*
Normal expanded wide mode Ports A and B are configured as a 16-bit multiplexed address and data bus and port E provides bus control and status signals. This mode allows 16-bit external memory and peripheral devices to be interfaced to the system. Normal expanded narrow mode Ports A and B are configured as a 16-bit address bus and port A is multiplexed with 8-bit data. Port E provides bus control and status signals. This mode allows 8-bit external memory and peripheral devices to be interfaced to the system. Normal single-chip mode There is no external expansion bus in this mode. The processor program is executed from internal memory. Ports A, B, K, and most of E are available as general-purpose I/O. Special single-chip mode This mode is generally used for debugging single-chip operation, boot-strapping, or security related operations. The active background mode is in control of CPU execution and BDM firmware is waiting for additional serial commands through the BKGD pin. There is no external expansion bus after reset in this mode. Emulation expanded wide mode Developers use this mode for emulation systems in which the users target application is normal expanded wide mode. Emulation expanded narrow mode Developers use this mode for emulation systems in which the users target application is normal expanded narrow mode. Special test mode Ports A and B are configured as a 16-bit multiplexed address and data bus and port E provides bus control and status signals. In special test mode, the write protection of many control bits is lifted so that they can be thoroughly tested without needing to go through reset. Special peripheral mode This mode is intended for Freescale Semiconductor factory testing of the system. The CPU is inactive and an external (tester) bus master drives address, data, and bus control signals.
21.2
External Signal Description
In typical implementations, the MEBI sub-block of the core interfaces directly with external system pins. Some pins may not be bonded out in all implementations. Table 21-1 outlines the pin names and functions and gives a brief description of their operation reset state of these pins and associated pull-ups or pull-downs is dependent on the mode of operation and on the integration of this block at the chip level (chip dependent).
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 577
Chapter 21 Multiplexed External Bus Interface (MEBIV3)
.
Table 21-1. External System Pins Associated With MEBI
Pin Name Pin Functions MODC BKGD TAGHI Description At the rising edge on RESET, the state of this pin is registered into the MODC bit to set the mode. (This pin always has an internal pullup.) Pseudo open-drain communication pin for the single-wire background debug mode. There is an internal pull-up resistor on this pin. When instruction tagging is on, a 0 at the falling edge of E tags the high half of the instruction word being read into the instruction queue. General-purpose I/O pins, see PORTA and DDRA registers. High-order address lines multiplexed during ECLK low. Outputs except in special peripheral mode where they are inputs from an external tester system. High-order bidirectional data lines multiplexed during ECLK high in expanded wide modes, special peripheral mode, and visible internal accesses (IVIS = 1) in emulation expanded narrow mode. Direction of data transfer is generally indicated by R/W. Alternate high-order and low-order bytes of the bidirectional data lines multiplexed during ECLK high in expanded narrow modes and narrow accesses in wide modes. Direction of data transfer is generally indicated by R/W. General-purpose I/O pins, see PORTB and DDRB registers. Low-order address lines multiplexed during ECLK low. Outputs except in special peripheral mode where they are inputs from an external tester system. Low-order bidirectional data lines multiplexed during ECLK high in expanded wide modes, special peripheral mode, and visible internal accesses (with IVIS = 1) in emulation expanded narrow mode. Direction of data transfer is generally indicated by R/W. General-purpose I/O pin, see PORTE and DDRE registers. CPU No Access output. Indicates whether the current cycle is a free cycle. Only available in expanded modes. At the rising edge of RESET, the state of this pin is registered into the MODB bit to set the mode. General-purpose I/O pin, see PORTE and DDRE registers. Instruction pipe status bit 1, enabled by PIPOE bit in PEAR. System clock test output. Only available in special modes. PIPOE = 1 overrides this function. The enable for this function is in the clock module. At the rising edge on RESET, the state of this pin is registered into the MODA bit to set the mode. General-purpose I/O pin, see PORTE and DDRE registers. Instruction pipe status bit 0, enabled by PIPOE bit in PEAR.
BKGD/MODC/ TAGHI
PA7/A15/D15/D7 thru PA0/A8/D8/D0
PA7-PA0 A15-A8 D15-D8
D15/D7 thru D8/D0 PB7/A7/D7 thru PB0/A0/D0 PB7-PB0 A7-A0 D7-D0
PE7/NOACC
PE7 NOACC
PE6/IPIPE1/ MODB/CLKTO
MODB PE6 IPIPE1 CLKTO
PE5/IPIPE0/MODA
MODA PE5 IPIPE0
MC9S12HZ256 Data Sheet, Rev. 2.05 578 Freescale Semiconductor
Chapter 21 Multiplexed External Bus Interface (MEBIV3)
Table 21-1. External System Pins Associated With MEBI (continued)
Pin Name PE4/ECLK Pin Functions PE4 ECLK Description General-purpose I/O pin, see PORTE and DDRE registers. Bus timing reference clock, can operate as a free-running clock at the system clock rate or to produce one low-high clock per visible access, with the high period stretched for slow accesses. ECLK is controlled by the NECLK bit in PEAR, the IVIS bit in MODE, and the ESTR bit in EBICTL. General-purpose I/O pin, see PORTE and DDRE registers. Low strobe bar, 0 indicates valid data on D7-D0. In special peripheral mode, this pin is an input indicating the size of the data transfer (0 = 16-bit; 1 = 8-bit). In expanded wide mode or emulation narrow modes, when instruction tagging is on and low strobe is enabled, a 0 at the falling edge of E tags the low half of the instruction word being read into the instruction queue. General-purpose I/O pin, see PORTE and DDRE registers. Read/write, indicates the direction of internal data transfers. This is an output except in special peripheral mode where it is an input. General-purpose input-only pin, can be read even if IRQ enabled. Maskable interrupt request, can be level sensitive or edge sensitive. General-purpose input-only pin. Non-maskable interrupt input. General-purpose I/O pin, see PORTK and DDRK registers. Emulation chip select General-purpose I/O pin, see PORTK and DDRK registers. External data chip select General-purpose I/O pins, see PORTK and DDRK registers. Memory expansion addresses
PE3/LSTRB/ TAGLO
PE3 LSTRB SZ8 TAGLO
PE2/R/W
PE2 R/W
PE1/IRQ
PE1 IRQ
PE0/XIRQ
PE0 XIRQ
PK7/ECS
PK7 ECS
PK6/XCS
PK6 XCS
PK5/X19 thru PK0/X14
PK5-PK0 X19-X14
Detailed descriptions of these pins can be found in the device overview chapter.
21.3
Memory Map and Register Definition
A summary of the registers associated with the MEBI sub-block is shown in Table 21-2. Detailed descriptions of the registers and bits are given in the subsections that follow. On most chips the registers are mappable. Therefore, the upper bits may not be all 0s as shown in the table and descriptions.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 579
Chapter 21 Multiplexed External Bus Interface (MEBIV3)
21.3.1
Module Memory Map
Table 21-2. MEBI Memory Map
Address Offset 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C 0x000D 0x000E 0x000F 0x001E 0x00032 0x00033 Port A Data Register (PORTA) Port B Data Register (PORTB) Data Direction Register A (DDRA) Data Direction Register B (DDRB) Reserved Reserved Reserved Reserved Port E Data Register (PORTE) Data Direction Register E (DDRE) Port E Assignment Register (PEAR) Mode Register (MODE) Pull Control Register (PUCR) Reduced Drive Register (RDRIV) External Bus Interface Control Register (EBICTL) Reserved IRQ Control Register (IRQCR) Port K Data Register (PORTK) Data Direction Register K (DDRK) Use Access R/W R/W R/W R/W R R R R R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W
21.3.2
21.3.2.1
Register Descriptions
Port A Data Register (PORTA)
7 6 5 4 3 2 1 0
R Bit 7 W Reset Single Chip 0 PA7 0 PA6 AB/DB14 0 PA5 AB/DB13 0 PA4 AB/DB12 0 PA3 AB/DB11 0 PA2 AB/DB10 0 PA1 AB/DB9 AB9 and DB9/DB1 0 PA0 AB/DB8 AB8 and DB8/DB0 6 5 4 3 2 1 Bit 0
Expanded Wide, Emulation Narrow with AB/DB15 IVIS, and Peripheral
Expanded Narrow AB15 and AB14 and AB13 and AB12 and AB11 and AB10 and DB15/DB7 DB14/DB6 DB13/DB5 DB12/DB4 DB11/DB3 DB10/DB2
Figure 21-2. Port A Data Register (PORTA)
MC9S12HZ256 Data Sheet, Rev. 2.05 580 Freescale Semiconductor
Chapter 21 Multiplexed External Bus Interface (MEBIV3)
Read: Anytime when register is in the map Write: Anytime when register is in the map Port A bits 7 through 0 are associated with address lines A15 through A8 respectively and data lines D15/D7 through D8/D0 respectively. When this port is not used for external addresses such as in single-chip mode, these pins can be used as general-purpose I/O. Data direction register A (DDRA) determines the primary direction of each pin. DDRA also determines the source of data for a read of PORTA. This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these accesses will be echoed externally. NOTE To ensure that you read the value present on the PORTA pins, always wait at least one cycle after writing to the DDRA register before reading from the PORTA register.
21.3.2.2
Port B Data Register (PORTB)
7 6 5 4 3 2 1 0
R Bit 7 W Reset Single Chip Expanded Wide, Emulation Narrow with IVIS, and Peripheral Expanded Narrow 0 PB7 AB/DB7 AB7 0 PB6 AB/DB6 AB6 0 PB5 AB/DB5 AB5 0 PB4 AB/DB4 AB4 0 PB3 AB/DB3 AB3 0 PB2 AB/DB2 AB2 0 PB1 AB/DB1 AB1 0 PB0 AB/DB0 AB0 6 5 4 3 2 1 Bit 0
Figure 21-3. Port A Data Register (PORTB)
Read: Anytime when register is in the map Write: Anytime when register is in the map Port B bits 7 through 0 are associated with address lines A7 through A0 respectively and data lines D7 through D0 respectively. When this port is not used for external addresses, such as in single-chip mode, these pins can be used as general-purpose I/O. Data direction register B (DDRB) determines the primary direction of each pin. DDRB also determines the source of data for a read of PORTB. This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these accesses will be echoed externally. NOTE To ensure that you read the value present on the PORTB pins, always wait at least one cycle after writing to the DDRB register before reading from the PORTB register.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 581
Chapter 21 Multiplexed External Bus Interface (MEBIV3)
21.3.2.3
Data Direction Register A (DDRA)
7 6 5 4 3 2 1 0
R Bit 7 W Reset 0 0 0 0 0 0 0 0 6 5 4 3 2 1 Bit 0
Figure 21-4. Data Direction Register A (DDRA)
Read: Anytime when register is in the map Write: Anytime when register is in the map This register controls the data direction for port A. When port A is operating as a general-purpose I/O port, DDRA determines the primary direction for each port A pin. A 1 causes the associated port pin to be an output and a 0 causes the associated pin to be a high-impedance input. The value in a DDR bit also affects the source of data for reads of the corresponding PORTA register. If the DDR bit is 0 (input) the buffered pin input state is read. If the DDR bit is 1 (output) the associated port data register bit state is read. This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these accesses will be echoed externally. It is reset to 0x00 so the DDR does not override the three-state control signals.
Table 21-3. DDRA Field Descriptions
Field 7:0 DDRA Description Data Direction Port A 0 Configure the corresponding I/O pin as an input 1 Configure the corresponding I/O pin as an output
MC9S12HZ256 Data Sheet, Rev. 2.05 582 Freescale Semiconductor
Chapter 21 Multiplexed External Bus Interface (MEBIV3)
21.3.2.4
Data Direction Register B (DDRB)
7 6 5 4 3 2 1 0
R Bit 7 W Reset 0 0 0 0 0 0 0 0 6 5 4 3 2 1 Bit 0
Figure 21-5. Data Direction Register B (DDRB)
Read: Anytime when register is in the map Write: Anytime when register is in the map This register controls the data direction for port B. When port B is operating as a general-purpose I/O port, DDRB determines the primary direction for each port B pin. A 1 causes the associated port pin to be an output and a 0 causes the associated pin to be a high-impedance input. The value in a DDR bit also affects the source of data for reads of the corresponding PORTB register. If the DDR bit is 0 (input) the buffered pin input state is read. If the DDR bit is 1 (output) the associated port data register bit state is read. This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these accesses will be echoed externally. It is reset to 0x00 so the DDR does not override the three-state control signals.
Table 21-4. DDRB Field Descriptions
Field 7:0 DDRB Description Data Direction Port B 0 Configure the corresponding I/O pin as an input 1 Configure the corresponding I/O pin as an output
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 583
Chapter 21 Multiplexed External Bus Interface (MEBIV3)
21.3.2.5
Reserved Registers
7 6 5 4 3 2 1 0
R W Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 21-6. Reserved Register
7 6 5 4 3 2 1 0
R W Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 21-7. Reserved Register
7 6 5 4 3 2 1 0
R W Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 21-8. Reserved Register
7 6 5 4 3 2 1 0
R W Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 21-9. Reserved Register
These register locations are not used (reserved). All unused registers and bits in this block return logic 0s when read. Writes to these registers have no effect. These registers are not in the on-chip map in special peripheral mode.
MC9S12HZ256 Data Sheet, Rev. 2.05 584 Freescale Semiconductor
Chapter 21 Multiplexed External Bus Interface (MEBIV3)
21.3.2.6
Port E Data Register (PORTE)
7 6 5 4 3 2 1 0
R Bit 7 W Reset Alternate Pin Function 0 NOACC 0 MODB or IPIPE1 or CLKTO 0 MODA or IPIPE0 0 ECLK 0 LSTRB or TAGLO 0 R/W 6 5 4 3 2
Bit 1
Bit 0
u IRQ
u XIRQ
= Unimplemented or Reserved
u = Unaffected by reset
Figure 21-10. Port E Data Register (PORTE)
Read: Anytime when register is in the map Write: Anytime when register is in the map Port E is associated with external bus control signals and interrupt inputs. These include mode select (MODB/IPIPE1, MODA/IPIPE0), E clock, size (LSTRB/TAGLO), read/write (R/W), IRQ, and XIRQ. When not used for one of these specific functions, port E pins 7:2 can be used as general-purpose I/O and pins 1:0 can be used as general-purpose input. The port E assignment register (PEAR) selects the function of each pin and DDRE determines whether each pin is an input or output when it is configured to be general-purpose I/O. DDRE also determines the source of data for a read of PORTE. Some of these pins have software selectable pull resistors. IRQ and XIRQ can only be pulled up whereas the polarity of the PE7, PE4, PE3, and PE2 pull resistors are determined by chip integration. Please refer to the device overview chapter (Signal Property Summary) to determine the polarity of these resistors. A single control bit enables the pull devices for all of these pins when they are configured as inputs. This register is not in the on-chip map in special peripheral mode or in expanded modes when the EME bit is set. Therefore, these accesses will be echoed externally. NOTE It is unwise to write PORTE and DDRE as a word access. If you are changing port E pins from being inputs to outputs, the data may have extra transitions during the write. It is best to initialize PORTE before enabling as outputs. NOTE To ensure that you read the value present on the PORTE pins, always wait at least one cycle after writing to the DDRE register before reading from the PORTE register.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 585
Chapter 21 Multiplexed External Bus Interface (MEBIV3)
21.3.2.7
Data Direction Register E (DDRE)
7 6 5 4 3 2 1 0
R Bit 7 W Reset 0 0 0 0 0 0 6 5 4 3 Bit 2
0
0
0
0
= Unimplemented or Reserved
Figure 21-11. Data Direction Register E (DDRE)
Read: Anytime when register is in the map Write: Anytime when register is in the map Data direction register E is associated with port E. For bits in port E that are configured as general-purpose I/O lines, DDRE determines the primary direction of each of these pins. A 1 causes the associated bit to be an output and a 0 causes the associated bit to be an input. Port E bit 1 (associated with IRQ) and bit 0 (associated with XIRQ) cannot be configured as outputs. Port E, bits 1 and 0, can be read regardless of whether the alternate interrupt function is enabled. The value in a DDR bit also affects the source of data for reads of the corresponding PORTE register. If the DDR bit is 0 (input) the buffered pin input state is read. If the DDR bit is 1 (output) the associated port data register bit state is read. This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these accesses will be echoed externally. Also, it is not in the map in expanded modes while the EME control bit is set.
Table 21-5. DDRE Field Descriptions
Field 7:2 DDRE Description Data Direction Port E 0 Configure the corresponding I/O pin as an input 1 Configure the corresponding I/O pin as an output Note: It is unwise to write PORTE and DDRE as a word access. If you are changing port E pins from inputs to outputs, the data may have extra transitions during the write. It is best to initialize PORTE before enabling as outputs.
MC9S12HZ256 Data Sheet, Rev. 2.05 586 Freescale Semiconductor
Chapter 21 Multiplexed External Bus Interface (MEBIV3)
21.3.2.8
Port E Assignment Register (PEAR)
7 6 5 4 3 2 1 0
R NOACCE W Reset Special Single Chip Special Test Peripheral Emulation Expanded Narrow Emulation Expanded Wide Normal Single Chip Normal Expanded Narrow Normal Expanded Wide 0 0 0 1 1 0 0 0
0 PIPOE NECLK LSTRE RDWE
0
0
0 0 0 0 0 0 0 0
0 1 0 1 1 0 0 0
0 0 0 0 0 1 0 0
0 1 0 1 1 0 0 0
0 1 0 1 1 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 21-12. Port E Assignment Register (PEAR)
Read: Anytime (provided this register is in the map). Write: Each bit has specific write conditions. Please refer to the descriptions of each bit on the following pages. Port E serves as general-purpose I/O or as system and bus control signals. The PEAR register is used to choose between the general-purpose I/O function and the alternate control functions. When an alternate control function is selected, the associated DDRE bits are overridden. The reset condition of this register depends on the mode of operation because bus control signals are needed immediately after reset in some modes. In normal single-chip mode, no external bus control signals are needed so all of port E is configured for general-purpose I/O. In normal expanded modes, only the E clock is configured for its alternate bus control function and the other bits of port E are configured for general-purpose I/O. As the reset vector is located in external memory, the E clock is required for this access. R/W is only needed by the system when there are external writable resources. If the normal expanded system needs any other bus control signals, PEAR would need to be written before any access that needed the additional signals. In special test and emulation modes, IPIPE1, IPIPE0, E, LSTRB, and R/W are configured out of reset as bus control signals. This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these accesses will be echoed externally.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 587
Chapter 21 Multiplexed External Bus Interface (MEBIV3)
Table 21-6. PEAR Field Descriptions
Field 7 NOACCE Description CPU No Access Output Enable Normal: write once Emulation: write never Special: write anytime 1 The associated pin (port E, bit 7) is general-purpose I/O. 0 The associated pin (port E, bit 7) is output and indicates whether the cycle is a CPU free cycle. This bit has no effect in single-chip or special peripheral modes. Pipe Status Signal Output Enable Normal: write once Emulation: write never Special: write anytime. 0 The associated pins (port E, bits 6:5) are general-purpose I/O. 1 The associated pins (port E, bits 6:5) are outputs and indicate the state of the instruction queue This bit has no effect in single-chip or special peripheral modes. No External E Clock Normal and special: write anytime Emulation: write never 0 The associated pin (port E, bit 4) is the external E clock pin. External E clock is free-running if ESTR = 0 1 The associated pin (port E, bit 4) is a general-purpose I/O pin. External E clock is available as an output in all modes. Low Strobe (LSTRB) Enable Normal: write once Emulation: write never Special: write anytime. 0 The associated pin (port E, bit 3) is a general-purpose I/O pin. 1 The associated pin (port E, bit 3) is configured as the LSTRB bus control output. If BDM tagging is enabled, TAGLO is multiplexed in on the rising edge of ECLK and LSTRB is driven out on the falling edge of ECLK. This bit has no effect in single-chip, peripheral, or normal expanded narrow modes. Note: LSTRB is used during external writes. After reset in normal expanded mode, LSTRB is disabled to provide an extra I/O pin. If LSTRB is needed, it should be enabled before any external writes. External reads do not normally need LSTRB because all 16 data bits can be driven even if the system only needs 8 bits of data. Read/Write Enable Normal: write once Emulation: write never Special: write anytime 0 The associated pin (port E, bit 2) is a general-purpose I/O pin. 1 The associated pin (port E, bit 2) is configured as the R/W pin This bit has no effect in single-chip or special peripheral modes. Note: R/W is used for external writes. After reset in normal expanded mode, R/W is disabled to provide an extra I/O pin. If R/W is needed it should be enabled before any external writes.
5 PIPOE
4 NECLK
3 LSTRE
2 RDWE
MC9S12HZ256 Data Sheet, Rev. 2.05 588 Freescale Semiconductor
Chapter 21 Multiplexed External Bus Interface (MEBIV3)
21.3.2.9
Mode Register (MODE)
7 6 5 4 3 2 1 0
R MODC W Reset Special Single Chip Emulation Expanded Narrow Special Test Emulation Expanded Wide Normal Single Chip Normal Expanded Narrow Peripheral Normal Expanded Wide 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 MODB MODA
0 IVIS
0 EMK EME
0 0 0 0 0 0 0 0
0 1 1 1 0 0 0 0
0 0 0 0 0 0 0 0
0 1 0 1 0 0 0 0
0 1 0 1 0 0 0 0
= Unimplemented or Reserved
Figure 21-13. Mode Register (MODE)
Read: Anytime (provided this register is in the map). Write: Each bit has specific write conditions. Please refer to the descriptions of each bit on the following pages. The MODE register is used to establish the operating mode and other miscellaneous functions (i.e., internal visibility and emulation of port E and K). In special peripheral mode, this register is not accessible but it is reset as shown to system configuration features. Changes to bits in the MODE register are delayed one cycle after the write. This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these accesses will be echoed externally.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 589
Chapter 21 Multiplexed External Bus Interface (MEBIV3)
Table 21-7. MODE Field Descriptions
Field 7:5 MOD[C:A] Description Mode Select Bits -- These bits indicate the current operating mode. If MODA = 1, then MODC, MODB, and MODA are write never. If MODC = MODA = 0, then MODC, MODB, and MODA are writable with the exception that you cannot change to or from special peripheral mode If MODC = 1, MODB = 0, and MODA = 0, then MODC is write never. MODB and MODA are write once, except that you cannot change to special peripheral mode. From normal single-chip, only normal expanded narrow and normal expanded wide modes are available. See Table 21-8 and Table 21-16. 3 IVIS Internal Visibility (for both read and write accesses) -- This bit determines whether internal accesses generate a bus cycle that is visible on the external bus. Normal: write once Emulation: write never Special: write anytime 0 No visibility of internal bus operations on external bus. 1 Internal bus operations are visible on external bus. Emulate Port K Normal: write once Emulation: write never Special: write anytime 0 PORTK and DDRK are in the memory map so port K can be used for general-purpose I/O. 1 If in any expanded mode, PORTK and DDRK are removed from the memory map. In single-chip modes, PORTK and DDRK are always in the map regardless of the state of this bit. In special peripheral mode, PORTK and DDRK are never in the map regardless of the state of this bit. Emulate Port E Normal and Emulation: write never Special: write anytime 0 PORTE and DDRE are in the memory map so port E can be used for general-purpose I/O. 1 If in any expanded mode or special peripheral mode, PORTE and DDRE are removed from the memory map. Removing the registers from the map allows the user to emulate the function of these registers externally. In single-chip modes, PORTE and DDRE are always in the map regardless of the state of this bit.
1 EMK
0 EME
MC9S12HZ256 Data Sheet, Rev. 2.05 590 Freescale Semiconductor
Chapter 21 Multiplexed External Bus Interface (MEBIV3)
Table 21-8. MODC, MODB, and MODA Write Capability1
MODC 0 0 0 0 1 MODB 0 0 1 1 0 MODA 0 1 0 1 0 Mode Special single chip Emulation narrow Special test Emulation wide Normal single chip MODx Write Capability MODC, MODB, and MODA write anytime but not to 1102 No write MODC, MODB, and MODA write anytime but not to 110(2) No write MODC write never, MODB and MODA write once but not to 110 No write No write No write
1 1 1
1 2
0 1 1
1 0 1
Normal expanded narrow Special peripheral Normal expanded wide
No writes to the MOD bits are allowed while operating in a secure mode. For more details, refer to the device overview chapter. If you are in a special single-chip or special test mode and you write to this register, changing to normal single-chip mode, then one allowed write to this register remains. If you write to normal expanded or emulation mode, then no writes remain.
21.3.2.10 Pull Control Register (PUCR)
7 6 5 4 3 2 1 0
R PUPKE W Reset1 1
0
0 PUPEE
0
0 PUPBE PUPAE 0
0
0
1
0
0
0
NOTES: 1. The default value of this parameter is shown. Please refer to the device overview chapter to determine the actual reset state of this register.
= Unimplemented or Reserved
Figure 21-14. Pull Control Register (PUCR)
Read: Anytime (provided this register is in the map). Write: Anytime (provided this register is in the map). This register is used to select pull resistors for the pins associated with the core ports. Pull resistors are assigned on a per-port basis and apply to any pin in the corresponding port that is currently configured as an input. The polarity of these pull resistors is determined by chip integration. Please refer to the device overview chapter to determine the polarity of these resistors.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 591
Chapter 21 Multiplexed External Bus Interface (MEBIV3)
This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these accesses will be echoed externally. NOTE These bits have no effect when the associated pin(s) are outputs. (The pull resistors are inactive.)
Table 21-9. PUCR Field Descriptions
Field 7 PUPKE 4 PUPEE Pull resistors Port K Enable 0 Port K pull resistors are disabled. 1 Enable pull resistors for port K input pins. Pull resistors Port E Enable 0 Port E pull resistors on bits 7, 4:0 are disabled. 1 Enable pull resistors for port E input pins bits 7, 4:0. Note: Pins 5 and 6 of port E have pull resistors which are only enabled during reset. This bit has no effect on these pins. Pull resistors Port B Enable 0 Port B pull resistors are disabled. 1 Enable pull resistors for all port B input pins. Pull resistors Port A Enable 0 Port A pull resistors are disabled. 1 Enable pull resistors for all port A input pins. Description
1 PUPBE 0 PUPAE
21.3.2.11 Reduced Drive Register (RDRIV)
7 6 5 4 3 2 1 0
R RDRK W Reset 0
0
0 RDPE
0
0 RDPB RDPA 0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 21-15. Reduced Drive Register (RDRIV)
Read: Anytime (provided this register is in the map) Write: Anytime (provided this register is in the map) This register is used to select reduced drive for the pins associated with the core ports. This gives reduced power consumption and reduced RFI with a slight increase in transition time (depending on loading). This feature would be used on ports which have a light loading. The reduced drive function is independent of which function is being used on a particular port. This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these accesses will be echoed externally.
MC9S12HZ256 Data Sheet, Rev. 2.05 592 Freescale Semiconductor
Chapter 21 Multiplexed External Bus Interface (MEBIV3)
Table 21-10. RDRIV Field Descriptions
Field 7 RDRK 4 RDPE 1 RDPB 0 RDPA Description Reduced Drive of Port K 0 All port K output pins have full drive enabled. 1 All port K output pins have reduced drive enabled. Reduced Drive of Port E 0 All port E output pins have full drive enabled. 1 All port E output pins have reduced drive enabled. Reduced Drive of Port B 0 All port B output pins have full drive enabled. 1 All port B output pins have reduced drive enabled. Reduced Drive of Ports A 0 All port A output pins have full drive enabled. 1 All port A output pins have reduced drive enabled.
21.3.2.12 External Bus Interface Control Register (EBICTL)
7 6 5 4 3 2 1 0
R W Reset: Peripheral All other modes
0
0
0
0
0
0
0 ESTR
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 1
= Unimplemented or Reserved
Figure 21-16. External Bus Interface Control Register (EBICTL)
Read: Anytime (provided this register is in the map) Write: Refer to individual bit descriptions below The EBICTL register is used to control miscellaneous functions (i.e., stretching of external E clock). This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these accesses will be echoed externally.
Table 21-11. EBICTL Field Descriptions
Field 0 ESTR Description E Clock Stretches -- This control bit determines whether the E clock behaves as a simple free-running clock or as a bus control signal that is active only for external bus cycles. Normal and Emulation: write once Special: write anytime 0 E never stretches (always free running). 1 E stretches high during stretched external accesses and remains low during non-visible internal accesses. This bit has no effect in single-chip modes.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 593
Chapter 21 Multiplexed External Bus Interface (MEBIV3)
21.3.2.13 Reserved Register
7 6 5 4 3 2 1 0
R W Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 21-17. Reserved Register
This register location is not used (reserved). All bits in this register return logic 0s when read. Writes to this register have no effect. This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these accesses will be echoed externally.
21.3.2.14 IRQ Control Register (IRQCR)
7 6 5 4 3 2 1 0
R IRQE W Reset 0 1 IRQEN
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 21-18. IRQ Control Register (IRQCR)
Read: See individual bit descriptions below Write: See individual bit descriptions below
Table 21-12. IRQCR Field Descriptions
Field 7 IRQE Description IRQ Select Edge Sensitive Only Special modes: read or write anytime Normal and Emulation modes: read anytime, write once 0 IRQ configured for low level recognition. 1 IRQ configured to respond only to falling edges. Falling edges on the IRQ pin will be detected anytime IRQE = 1 and will be cleared only upon a reset or the servicing of the IRQ interrupt. External IRQ Enable Normal, emulation, and special modes: read or write anytime 0 External IRQ pin is disconnected from interrupt logic. 1 External IRQ pin is connected to interrupt logic. Note: When IRQEN = 0, the edge detect latch is disabled.
6 IRQEN
MC9S12HZ256 Data Sheet, Rev. 2.05 594 Freescale Semiconductor
Chapter 21 Multiplexed External Bus Interface (MEBIV3)
21.3.2.15 Port K Data Register (PORTK)
7 6 5 4 3 2 1 0
R Bit 7 W Reset Alternate Pin Function 0 ECS 0 XCS 0 XAB19 0 XAB18 0 XAB17 0 XAB16 0 XAB15 0 XAB14 6 5 4 3 2 1 Bit 0
Figure 21-19. Port K Data Register (PORTK)
Read: Anytime Write: Anytime This port is associated with the internal memory expansion emulation pins. When the port is not enabled to emulate the internal memory expansion, the port pins are used as general-purpose I/O. When port K is operating as a general-purpose I/O port, DDRK determines the primary direction for each port K pin. A 1 causes the associated port pin to be an output and a 0 causes the associated pin to be a high-impedance input. The value in a DDR bit also affects the source of data for reads of the corresponding PORTK register. If the DDR bit is 0 (input) the buffered pin input is read. If the DDR bit is 1 (output) the output of the port data register is read. This register is not in the map in peripheral or expanded modes while the EMK control bit in MODE register is set. Therefore, these accesses will be echoed externally. When inputs, these pins can be selected to be high impedance or pulled up, based upon the state of the PUPKE bit in the PUCR register.
Table 21-13. PORTK Field Descriptions
Field 7 Port K, Bit 7 Description Port K, Bit 7 -- This bit is used as an emulation chip select signal for the emulation of the internal memory expansion, or as general-purpose I/O, depending upon the state of the EMK bit in the MODE register. While this bit is used as a chip select, the external bit will return to its de-asserted state (VDD) for approximately 1/4 cycle just after the negative edge of ECLK, unless the external access is stretched and ECLK is free-running (ESTR bit in EBICTL = 0). See the MMC block description chapter for additional details on when this signal will be active. Port K, Bit 6 -- This bit is used as an external chip select signal for most external accesses that are not selected by ECS (see the MMC block description chapter for more details), depending upon the state the of the EMK bit in the MODE register. While this bit is used as a chip select, the external pin will return to its deasserted state (VDD) for approximately 1/4 cycle just after the negative edge of ECLK, unless the external access is stretched and ECLK is free-running (ESTR bit in EBICTL = 0).
6 Port K, Bit 6
5:0 Port K, Bits 5:0 -- These six bits are used to determine which FLASH/ROM or external memory array page Port K, Bits 5:0 is being accessed. They can be viewed as expanded addresses XAB19-XAB14 of the 20-bit address used to access up to1M byte internal FLASH/ROM or external memory array. Alternatively, these bits can be used for general-purpose I/O depending upon the state of the EMK bit in the MODE register.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 595
Chapter 21 Multiplexed External Bus Interface (MEBIV3)
21.3.2.16 Port K Data Direction Register (DDRK)
7 6 5 4 3 2 1 0
R Bit 7 W Reset 0 0 0 0 0 0 0 0 6 5 4 3 2 1 Bit 0
Figure 21-20. Port K Data Direction Register (DDRK)
Read: Anytime Write: Anytime This register determines the primary direction for each port K pin configured as general-purpose I/O. This register is not in the map in peripheral or expanded modes while the EMK control bit in MODE register is set. Therefore, these accesses will be echoed externally.
Table 21-14. EBICTL Field Descriptions
Field 7:0 DDRK Description Data Direction Port K Bits 0 Associated pin is a high-impedance input 1 Associated pin is an output Note: It is unwise to write PORTK and DDRK as a word access. If you are changing port K pins from inputs to outputs, the data may have extra transitions during the write. It is best to initialize PORTK before enabling as outputs. Note: To ensure that you read the correct value from the PORTK pins, always wait at least one cycle after writing to the DDRK register before reading from the PORTK register.
21.4
21.4.1
Functional Description
Detecting Access Type from External Signals
The external signals LSTRB, R/W, and AB0 indicate the type of bus access that is taking place. Accesses to the internal RAM module are the only type of access that would produce LSTRB = AB0 = 1, because the internal RAM is specifically designed to allow misaligned 16-bit accesses in a single cycle. In these cases the data for the address that was accessed is on the low half of the data bus and the data for address + 1 is on the high half of the data bus. This is summarized in Table 21-15.
Table 21-15. Access Type vs. Bus Control Pins
LSTRB 1 0 1 0 0 AB0 0 1 0 1 0 R/W 1 1 0 0 1 Type of Access 8-bit read of an even address 8-bit read of an odd address 8-bit write of an even address 8-bit write of an odd address 16-bit read of an even address
MC9S12HZ256 Data Sheet, Rev. 2.05 596 Freescale Semiconductor
Chapter 21 Multiplexed External Bus Interface (MEBIV3)
Table 21-15. Access Type vs. Bus Control Pins
LSTRB 1 0 1 AB0 1 0 1 R/W 1 0 0 Type of Access 16-bit read of an odd address (low/high data swapped) 16-bit write to an even address 16-bit write to an odd address (low/high data swapped)
21.4.2
Stretched Bus Cycles
In order to allow fast internal bus cycles to coexist in a system with slower external memory resources, the HCS12 supports the concept of stretched bus cycles (module timing reference clocks for timers and baud rate generators are not affected by this stretching). Control bits in the MISC register in the MMC sub-block of the core specify the amount of stretch (0, 1, 2, or 3 periods of the internal bus-rate clock). While stretching, the CPU state machines are all held in their current state. At this point in the CPU bus cycle, write data would already be driven onto the data bus so the length of time write data is valid is extended in the case of a stretched bus cycle. Read data would not be captured by the system until the E clock falling edge. In the case of a stretched bus cycle, read data is not required until the specified setup time before the falling edge of the stretched E clock. The chip selects, and R/W signals remain valid during the period of stretching (throughout the stretched E high time). NOTE The address portion of the bus cycle is not stretched.
21.4.3
Modes of Operation
The operating mode out of reset is determined by the states of the MODC, MODB, and MODA pins during reset (Table 21-16). The MODC, MODB, and MODA bits in the MODE register show the current operating mode and provide limited mode switching during operation. The states of the MODC, MODB, and MODA pins are latched into these bits on the rising edge of the reset signal.
Table 21-16. Mode Selection
MODC 0 0 0 0 1 1 1 1 MODB 0 0 1 1 0 0 1 1 MODA 0 1 0 1 0 1 0 1 Mode Description Special Single Chip, BDM allowed and ACTIVE. BDM is allowed in all other modes but a serial command is required to make BDM active. Emulation Expanded Narrow, BDM allowed Special Test (Expanded Wide), BDM allowed Emulation Expanded Wide, BDM allowed Normal Single Chip, BDM allowed Normal Expanded Narrow, BDM allowed Peripheral; BDM allowed but bus operations would cause bus conflicts (must not be used) Normal Expanded Wide, BDM allowed
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 597
Chapter 21 Multiplexed External Bus Interface (MEBIV3)
There are two basic types of operating modes: 1. Normal modes: Some registers and bits are protected against accidental changes. 2. Special modes: Allow greater access to protected control registers and bits for special purposes such as testing. A system development and debug feature, background debug mode (BDM), is available in all modes. In special single-chip mode, BDM is active immediately after reset. Some aspects of Port E are not mode dependent. Bit 1 of Port E is a general purpose input or the IRQ interrupt input. IRQ can be enabled by bits in the CPU's condition codes register but it is inhibited at reset so this pin is initially configured as a simple input with a pull-up. Bit 0 of Port E is a general purpose input or the XIRQ interrupt input. XIRQ can be enabled by bits in the CPU's condition codes register but it is inhibited at reset so this pin is initially configured as a simple input with a pull-up. The ESTR bit in the EBICTL register is set to one by reset in any user mode. This assures that the reset vector can be fetched even if it is located in an external slow memory device. The PE6/MODB/IPIPE1 and PE5/MODA/IPIPE0 pins act as high-impedance mode select inputs during reset. The following paragraphs discuss the default bus setup and describe which aspects of the bus can be changed after reset on a per mode basis.
21.4.3.1
Normal Operating Modes
These modes provide three operating configurations. Background debug is available in all three modes, but must first be enabled for some operations by means of a BDM background command, then activated. 21.4.3.1.1 Normal Single-Chip Mode
There is no external expansion bus in this mode. All pins of Ports A, B and E are configured as general purpose I/O pins Port E bits 1 and 0 are available as general purpose input only pins with internal pull resistors enabled. All other pins of Port E are bidirectional I/O pins that are initially configured as high-impedance inputs with internal pull resistors enabled. Ports A and B are configured as high-impedance inputs with their internal pull resistors disabled. The pins associated with Port E bits 6, 5, 3, and 2 cannot be configured for their alternate functions IPIPE1, IPIPE0, LSTRB, and R/W while the MCU is in single chip modes. In single chip modes, the associated control bits PIPOE, LSTRE, and RDWE are reset to zero. Writing the opposite state into them in single chip mode does not change the operation of the associated Port E pins. In normal single chip mode, the MODE register is writable one time. This allows a user program to change the bus mode to narrow or wide expanded mode and/or turn on visibility of internal accesses. Port E, bit 4 can be configured for a free-running E clock output by clearing NECLK=0. Typically the only use for an E clock output while the MCU is in single chip modes would be to get a constant speed clock for use in the external application system.
MC9S12HZ256 Data Sheet, Rev. 2.05 598 Freescale Semiconductor
Chapter 21 Multiplexed External Bus Interface (MEBIV3)
21.4.3.1.2
Normal Expanded Wide Mode
In expanded wide modes, Ports A and B are configured as a 16-bit multiplexed address and data bus and Port E bit 4 is configured as the E clock output signal. These signals allow external memory and peripheral devices to be interfaced to the MCU. Port E pins other than PE4/ECLK are configured as general purpose I/O pins (initially high-impedance inputs with internal pull resistors enabled). Control bits PIPOE, NECLK, LSTRE, and RDWE in the PEAR register can be used to configure Port E pins to act as bus control outputs instead of general purpose I/O pins. It is possible to enable the pipe status signals on Port E bits 6 and 5 by setting the PIPOE bit in PEAR, but it would be unusual to do so in this mode. Development systems where pipe status signals are monitored would typically use the special variation of this mode. The Port E bit 2 pin can be reconfigured as the R/W bus control signal by writing "1" to the RDWE bit in PEAR. If the expanded system includes external devices that can be written, such as RAM, the RDWE bit would need to be set before any attempt to write to an external location. If there are no writable resources in the external system, PE2 can be left as a general purpose I/O pin. The Port E bit 3 pin can be reconfigured as the LSTRB bus control signal by writing "1" to the LSTRE bit in PEAR. The default condition of this pin is a general purpose input because the LSTRB function is not needed in all expanded wide applications. The Port E bit 4 pin is initially configured as ECLK output with stretch. The E clock output function depends upon the settings of the NECLK bit in the PEAR register, the IVIS bit in the MODE register and the ESTR bit in the EBICTL register. The E clock is available for use in external select decode logic or as a constant speed clock for use in the external application system. 21.4.3.1.3 Normal Expanded Narrow Mode
This mode is used for lower cost production systems that use 8-bit wide external EPROMs or RAMs. Such systems take extra bus cycles to access 16-bit locations but this may be preferred over the extra cost of additional external memory devices. Ports A and B are configured as a 16-bit address bus and Port A is multiplexed with data. Internal visibility is not available in this mode because the internal cycles would need to be split into two 8-bit cycles. Since the PEAR register can only be written one time in this mode, use care to set all bits to the desired states during the single allowed write. The PE3/LSTRB pin is always a general purpose I/O pin in normal expanded narrow mode. Although it is possible to write the LSTRE bit in PEAR to "1" in this mode, the state of LSTRE is overridden and Port E bit 3 cannot be reconfigured as the LSTRB output. It is possible to enable the pipe status signals on Port E bits 6 and 5 by setting the PIPOE bit in PEAR, but it would be unusual to do so in this mode. LSTRB would also be needed to fully understand system activity. Development systems where pipe status signals are monitored would typically use special expanded wide mode or occasionally special expanded narrow mode.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 599
Chapter 21 Multiplexed External Bus Interface (MEBIV3)
The PE4/ECLK pin is initially configured as ECLK output with stretch. The E clock output function depends upon the settings of the NECLK bit in the PEAR register, the IVIS bit in the MODE register and the ESTR bit in the EBICTL register. In normal expanded narrow mode, the E clock is available for use in external select decode logic or as a constant speed clock for use in the external application system. The PE2/R/W pin is initially configured as a general purpose input with an internal pull resistor enabled but this pin can be reconfigured as the R/W bus control signal by writing "1" to the RDWE bit in PEAR. If the expanded narrow system includes external devices that can be written such as RAM, the RDWE bit would need to be set before any attempt to write to an external location. If there are no writable resources in the external system, PE2 can be left as a general purpose I/O pin. 21.4.3.1.4 Emulation Expanded Wide Mode
In expanded wide modes, Ports A and B are configured as a 16-bit multiplexed address and data bus and Port E provides bus control and status signals. These signals allow external memory and peripheral devices to be interfaced to the MCU. These signals can also be used by a logic analyzer to monitor the progress of application programs. The bus control related pins in Port E (PE7/NOACC, PE6/MODB/IPIPE1, PE5/MODA/IPIPE0, PE4/ECLK, PE3/LSTRB/TAGLO, and PE2/R/W) are all configured to serve their bus control output functions rather than general purpose I/O. Notice that writes to the bus control enable bits in the PEAR register in emulation mode are restricted. 21.4.3.1.5 Emulation Expanded Narrow Mode
Expanded narrow modes are intended to allow connection of single 8-bit external memory devices for lower cost systems that do not need the performance of a full 16-bit external data bus. Accesses to internal resources that have been mapped external (i.e. PORTA, PORTB, DDRA, DDRB, PORTE, DDRE, PEAR, PUCR, RDRIV) will be accessed with a 16-bit data bus on Ports A and B. Accesses of 16-bit external words to addresses which are normally mapped external will be broken into two separate 8-bit accesses using Port A as an 8-bit data bus. Internal operations continue to use full 16-bit data paths. They are only visible externally as 16-bit information if IVIS=1. Ports A and B are configured as multiplexed address and data output ports. During external accesses, address A15, data D15 and D7 are associated with PA7, address A0 is associated with PB0 and data D8 and D0 are associated with PA0. During internal visible accesses and accesses to internal resources that have been mapped external, address A15 and data D15 is associated with PA7 and address A0 and data D0 is associated with PB0. The bus control related pins in Port E (PE7/NOACC, PE6/MODB/IPIPE1, PE5/MODA/IPIPE0, PE4/ECLK, PE3/LSTRB/TAGLO, and PE2/R/W) are all configured to serve their bus control output functions rather than general purpose I/O. Notice that writes to the bus control enable bits in the PEAR register in emulation mode are restricted. The main difference between special modes and normal modes is that some of the bus control and system control signals cannot be written in emulation modes.
MC9S12HZ256 Data Sheet, Rev. 2.05 600 Freescale Semiconductor
Chapter 21 Multiplexed External Bus Interface (MEBIV3)
21.4.3.2
Special Operating Modes
There are two special operating modes that correspond to normal operating modes. These operating modes are commonly used in factory testing and system development. 21.4.3.2.1 Special Single-Chip Mode
When the MCU is reset in this mode, the background debug mode is enabled and active. The MCU does not fetch the reset vector and execute application code as it would in other modes. Instead the active background mode is in control of CPU execution and BDM firmware is waiting for additional serial commands through the BKGD pin. When a serial command instructs the MCU to return to normal execution, the system will be configured as described below unless the reset states of internal control registers have been changed through background commands after the MCU was reset. There is no external expansion bus after reset in this mode. Ports A and B are initially simple bidirectional I/O pins that are configured as high-impedance inputs with internal pull resistors disabled; however, writing to the mode select bits in the MODE register (which is allowed in special modes) can change this after reset. All of the Port E pins (except PE4/ECLK) are initially configured as general purpose high-impedance inputs with internal pull resistors enabled. PE4/ECLK is configured as the E clock output in this mode. The pins associated with Port E bits 6, 5, 3, and 2 cannot be configured for their alternate functions IPIPE1, IPIPE0, LSTRB, and R/W while the MCU is in single chip modes. In single chip modes, the associated control bits PIPOE, LSTRE and RDWE are reset to zero. Writing the opposite value into these bits in single chip mode does not change the operation of the associated Port E pins. Port E, bit 4 can be configured for a free-running E clock output by clearing NECLK=0. Typically the only use for an E clock output while the MCU is in single chip modes would be to get a constant speed clock for use in the external application system. 21.4.3.2.2 Special Test Mode
In expanded wide modes, Ports A and B are configured as a 16-bit multiplexed address and data bus and Port E provides bus control and status signals. In special test mode, the write protection of many control bits is lifted so that they can be thoroughly tested without needing to go through reset.
21.4.3.3
Test Operating Mode
There is a test operating mode in which an external master, such as an I.C. tester, can control the on-chip peripherals. 21.4.3.3.1 Peripheral Mode
This mode is intended for factory testing of the MCU. In this mode, the CPU is inactive and an external (tester) bus master drives address, data and bus control signals in through Ports A, B and E. In effect, the whole MCU acts as if it was a peripheral under control of an external CPU. This allows faster testing of on-chip memory and peripherals than previous testing methods. Since the mode control register is not accessible in peripheral mode, the only way to change to another mode is to reset the MCU into a different
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 601
Chapter 21 Multiplexed External Bus Interface (MEBIV3)
mode. Background debugging should not be used while the MCU is in special peripheral mode as internal bus conflicts between BDM and the external master can cause improper operation of both functions.
21.4.4
Internal Visibility
Internal visibility is available when the MCU is operating in expanded wide modes or emulation narrow mode. It is not available in single-chip, peripheral or normal expanded narrow modes. Internal visibility is enabled by setting the IVIS bit in the MODE register. If an internal access is made while E, R/W, and LSTRB are configured as bus control outputs and internal visibility is off (IVIS=0), E will remain low for the cycle, R/W will remain high, and address, data and the LSTRB pins will remain at their previous state. When internal visibility is enabled (IVIS=1), certain internal cycles will be blocked from going external. During cycles when the BDM is selected, R/W will remain high, data will maintain its previous state, and address and LSTRB pins will be updated with the internal value. During CPU no access cycles when the BDM is not driving, R/W will remain high, and address, data and the LSTRB pins will remain at their previous state. NOTE When the system is operating in a secure mode, internal visibility is not available (i.e., IVIS = 1 has no effect). Also, the IPIPE signals will not be visible, regardless of operating mode. IPIPE1-IPIPE0 will display 0es if they are enabled. In addition, the MOD bits in the MODE control register cannot be written.
21.4.5
Low-Power Options
The MEBI does not contain any user-controlled options for reducing power consumption. The operation of the MEBI in low-power modes is discussed in the following subsections.
21.4.5.1
Operation in Run Mode
The MEBI does not contain any options for reducing power in run mode; however, the external addresses are conditioned to reduce power in single-chip modes. Expanded bus modes will increase power consumption.
21.4.5.2
Operation in Wait Mode
The MEBI does not contain any options for reducing power in wait mode.
21.4.5.3
Operation in Stop Mode
The MEBI will cease to function after execution of a CPU STOP instruction.
MC9S12HZ256 Data Sheet, Rev. 2.05 602 Freescale Semiconductor
Chapter 22 Module Mapping Control (MMCV4)
22.1 Introduction
This section describes the functionality of the module mapping control (MMC) sub-block of the S12 core platform. The block diagram of the MMC is shown in Figure 22-1.
MMC SECURE BDM_UNSECURE STOP, WAIT SECURITY MMC_SECURE
ADDRESS DECODE READ & WRITE ENABLES CLOCKS, RESET MODE INFORMATION INTERNAL MEMORY EXPANSION REGISTERS PORT K INTERFACE MEMORY SPACE SELECT(S) PERIPHERAL SELECT EBI ALTERNATE ADDRESS BUS EBI ALTERNATE WRITE DATA BUS EBI ALTERNATE READ DATA BUS ALTERNATE ADDRESS BUS (BDM) CPU ADDRESS BUS CPU READ DATA BUS CPU WRITE DATA BUS CPU CONTROL BUS CONTROL ALTERNATE WRITE DATA BUS (BDM) ALTERNATE READ DATA BUS (BDM) CORE SELECT (S)
Figure 22-1. MMC Block Diagram
The MMC is the sub-module which controls memory map assignment and selection of internal resources and external space. Internal buses between the core and memories and between the core and peripherals is controlled in this module. The memory expansion is generated in this module.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 603
Chapter 22 Module Mapping Control (MMCV4)
22.1.1
* * * * * * * * * * *
Features
Registers for mapping of address space for on-chip RAM, EEPROM, and FLASH (or ROM) memory blocks and associated registers Memory mapping control and selection based upon address decode and system operating mode Core address bus control Core data bus control and multiplexing Core security state decoding Emulation chip select signal generation (ECS) External chip select signal generation (XCS) Internal memory expansion External stretch and ROM mapping control functions via the MISC register Reserved registers for test purposes Configurable system memory options defined at integration of core into the system-on-a-chip (SoC).
22.1.2
Modes of Operation
Some of the registers operate differently depending on the mode of operation (i.e., normal expanded wide, special single chip, etc.). This is best understood from the register descriptions.
22.2
External Signal Description
All interfacing with the MMC sub-block is done within the core, it has no external signals.
22.3
Memory Map and Register Definition
A summary of the registers associated with the MMC sub-block is shown in Figure 22-2. Detailed descriptions of the registers and bits are given in the subsections that follow.
22.3.1
Module Memory Map
Table 22-1. MMC Memory Map
Address Offset Register Initialization of Internal RAM Position Register (INITRM) Initialization of Internal Registers Position Register (INITRG) Initialization of Internal EEPROM Position Register (INITEE) Miscellaneous System Control Register (MISC) Reserved . . . . Access R/W R/W R/W R/W -- --
MC9S12HZ256 Data Sheet, Rev. 2.05 604 Freescale Semiconductor
Chapter 22 Module Mapping Control (MMCV4)
Table 22-1. MMC Memory Map (continued)
Address Offset Reserved . . Memory Size Register 0 (MEMSIZ0) Memory Size Register 1 (MEMSIZ1) . . . . Program Page Index Register (PPAGE) Reserved R/W -- . . Register Access -- -- R R
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 605
Chapter 22 Module Mapping Control (MMCV4)
22.3.2
Name INITRM
Register Descriptions
Bit 7 R W RAM15 0 6 RAM14 5 RAM13 4 RAM12 3 RAM11 2 0 1 0 Bit 0 RAMHAL 0
INITRG
R W
REG14
REG13
REG12
REG11
0
0
INITEE
R W
EE15 0
EE14 0
EE13 0
EE12 0
EE11
0
0
EEON
MISC
R W
EXSTR1 3
EXSTR0 2
ROMHM 1
ROMON Bit 0
MTSTO
R W
Bit 7
6
5
4
MTST1
R W
Bit 7
6
5
4
3
2
1
Bit 0
MEMSIZ0
R REG_SW0 W
0
EEP_SW1 EEP_SW0
0
RAM_SW2 RAM_SW1 RAM_SW0
MEMSIZ1
R ROM_SW1 ROM_SW0 W
0
0
0
0
PAG_SW1 PAG_SW0
PPAGE
R W
0
0
PIX5 0
PIX4 0
PIX3 0
PIX2 0
PIX1 0
PIX0 0
Reserved
R W
0
0
= Unimplemented
Figure 22-2. MMC Register Summary
22.3.2.1
Initialization of Internal RAM Position Register (INITRM)
7 6 5 4 3 2 1 0
R RAM15 W Reset 0 0 0 0 1 RAM14 RAM13 RAM12 RAM11
0
0 RAMHAL
0
0
1
= Unimplemented or Reserved
Figure 22-3. Initialization of Internal RAM Position Register (INITRM)
Read: Anytime
MC9S12HZ256 Data Sheet, Rev. 2.05 606 Freescale Semiconductor
Chapter 22 Module Mapping Control (MMCV4)
Write: Once in normal and emulation modes, anytime in special modes NOTE Writes to this register take one cycle to go into effect. This register initializes the position of the internal RAM within the on-chip system memory map.
Table 22-2. INITRM Field Descriptions
Field Description
7:3 Internal RAM Map Position -- These bits determine the upper five bits of the base address for the system's RAM[15:11] internal RAM array. 0 RAMHAL RAM High-Align -- RAMHAL specifies the alignment of the internal RAM array. 0 Aligns the RAM to the lowest address (0x0000) of the mappable space 1 Aligns the RAM to the higher address (0xFFFF) of the mappable space
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 607
Chapter 22 Module Mapping Control (MMCV4)
22.3.2.2
Initialization of Internal Registers Position Register (INITRG)
7 6 5 4 3 2 1 0
R W Reset
0 REG14 0 0 REG13 0 REG12 0 REG11 0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 22-4. Initialization of Internal Registers Position Register (INITRG)
Read: Anytime Write: Once in normal and emulation modes and anytime in special modes This register initializes the position of the internal registers within the on-chip system memory map. The registers occupy either a 1K byte or 2K byte space and can be mapped to any 2K byte space within the first 32K bytes of the system's address space.
Table 22-3. INITRG Field Descriptions
Field Description
6:3 Internal Register Map Position -- These four bits in combination with the leading zero supplied by bit 7 of REG[14:11] INITRG determine the upper five bits of the base address for the system's internal registers (i.e., the minimum base address is 0x0000 and the maximum is 0x7FFF).
MC9S12HZ256 Data Sheet, Rev. 2.05 608 Freescale Semiconductor
Chapter 22 Module Mapping Control (MMCV4)
22.3.2.3
Initialization of Internal EEPROM Position Register (INITEE)
7 6 5 4 3 2 1 0
R EE15 W Reset1 -- -- -- -- -- EE14 EE13 EE12 EE11
0
0 EEON
--
--
--
1. The reset state of this register is controlled at chip integration. Please refer to the device overview section to determine the actual reset state of this register. = Unimplemented or Reserved
Figure 22-5. Initialization of Internal EEPROM Position Register (INITEE)
Read: Anytime Write: The EEON bit can be written to any time on all devices. Bits E[11:15] are "write anytime in all modes" on most devices. On some devices, bits E[11:15] are "write once in normal and emulation modes and write anytime in special modes". See device overview chapter to determine the actual write access rights. NOTE Writes to this register take one cycle to go into effect. This register initializes the position of the internal EEPROM within the on-chip system memory map.
Table 22-4. INITEE Field Descriptions
Field 7:3 EE[15:11] 0 EEON Description Internal EEPROM Map Position -- These bits determine the upper five bits of the base address for the system's internal EEPROM array. Enable EEPROM -- This bit is used to enable the EEPROM memory in the memory map. 0 Disables the EEPROM from the memory map. 1 Enables the EEPROM in the memory map at the address selected by EE[15:11].
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 609
Chapter 22 Module Mapping Control (MMCV4)
22.3.2.4
Miscellaneous System Control Register (MISC)
7 6 5 4 3 2 1 0
R W Reset: Expanded or Emulation Reset: Peripheral or Single Chip Reset: Special Test
0
0
0
0 EXSTR1 EXSTR0 ROMHM ROMON --1 1 0
0 0 0
0 0 0
0 0 0
0 0 0
1 1 1
1 1 1
0 0 0
1. The reset state of this bit is determined at the chip integration level. = Unimplemented or Reserved
Figure 22-6. Miscellaneous System Control Register (MISC)
Read: Anytime Write: As stated in each bit description NOTE Writes to this register take one cycle to go into effect. This register initializes miscellaneous control functions.
Table 22-5. INITEE Field Descriptions
Field Description
3:2 External Access Stretch Bits 1 and 0 EXSTR[1:0] Write: once in normal and emulation modes and anytime in special modes This two-bit field determines the amount of clock stretch on accesses to the external address space as shown in Table 22-6. In single chip and peripheral modes these bits have no meaning or effect. 1 ROMHM FLASH EEPROM or ROM Only in Second Half of Memory Map Write: once in normal and emulation modes and anytime in special modes 0 The fixed page(s) of FLASH EEPROM or ROM in the lower half of the memory map can be accessed. 1 Disables direct access to the FLASH EEPROM or ROM in the lower half of the memory map. These physical locations of the FLASH EEPROM or ROM remain accessible through the program page window. ROMON -- Enable FLASH EEPROM or ROM Write: once in normal and emulation modes and anytime in special modes This bit is used to enable the FLASH EEPROM or ROM memory in the memory map. 0 Disables the FLASH EEPROM or ROM from the memory map. 1 Enables the FLASH EEPROM or ROM in the memory map.
0 ROMON
Table 22-6. External Stretch Bit Definition
Stretch Bit EXSTR1 0 0 1 1 Stretch Bit EXSTR0 0 1 0 1 MC9S12HZ256 Data Sheet, Rev. 2.05 610 Freescale Semiconductor Number of E Clocks Stretched 0 1 2 3
Chapter 22 Module Mapping Control (MMCV4)
22.3.2.5
Reserved Test Register 0 (MTST0)
7 6 5 4 3 2 1 0
R W Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 22-7. Reserved Test Register 0 (MTST0)
Read: Anytime Write: No effect -- this register location is used for internal test purposes.
22.3.2.6
Reserved Test Register 1 (MTST1)
7 6 5 4 3 2 1 0
R W Reset
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
= Unimplemented or Reserved
Figure 22-8. Reserved Test Register 1 (MTST1)
Read: Anytime Write: No effect -- this register location is used for internal test purposes.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 611
Chapter 22 Module Mapping Control (MMCV4)
22.3.2.7
Memory Size Register 0 (MEMSIZ0)
7 6 5 4 3 2 1 0
R REG_SW0 W Reset --
0
EEP_SW1
EEP_SW0
0
RAM_SW2
RAM_SW1
RAM_SW0
--
--
--
--
--
--
--
= Unimplemented or Reserved
Figure 22-9. Memory Size Register 0 (MEMSIZ0)
Read: Anytime Write: Writes have no effect Reset: Defined at chip integration, see device overview section. The MEMSIZ0 register reflects the state of the register, EEPROM and RAM memory space configuration switches at the core boundary which are configured at system integration. This register allows read visibility to the state of these switches.
Table 22-7. MEMSIZ0 Field Descriptions
Field 7 REG_SW0 Description Allocated System Register Space 0 Allocated system register space size is 1K byte 1 Allocated system register space size is 2K byte
5:4 Allocated System EEPROM Memory Space -- The allocated system EEPROM memory space size is as EEP_SW[1:0] given in Table 22-8. 2 Allocated System RAM Memory Space -- The allocated system RAM memory space size is as given in RAM_SW[2:0] Table 22-9.
Table 22-8. Allocated EEPROM Memory Space
eep_sw1:eep_sw0 00 01 10 11 Allocated EEPROM Space 0K byte 2K bytes 4K bytes 8K bytes
Table 22-9. Allocated RAM Memory Space
ram_sw2:ram_sw0 000 001 010 011 100 Allocated RAM Space 2K bytes 4K bytes 6K bytes 8K bytes 10K bytes RAM Mappable Region 2K bytes 4K bytes 8K bytes
2
INITRM Bits Used RAM[15:11] RAM[15:12] RAM[15:13] RAM[15:13] RAM[15:14]
RAM Reset Base Address1 0x0800 0x0000 0x0800 0x0000 0x1800
8K bytes 16K bytes
2
MC9S12HZ256 Data Sheet, Rev. 2.05 612 Freescale Semiconductor
Chapter 22 Module Mapping Control (MMCV4)
Table 22-9. Allocated RAM Memory Space (continued)
ram_sw2:ram_sw0 101 110 111
1 2
Allocated RAM Space 12K bytes 14K bytes 16K bytes
RAM Mappable Region 16K bytes 2 16K bytes
2
INITRM Bits Used RAM[15:14] RAM[15:14] RAM[15:14]
RAM Reset Base Address1 0x1000 0x0800 0x0000
16K bytes
The RAM Reset BASE Address is based on the reset value of the INITRM register, 0x0009. Alignment of the Allocated RAM space within the RAM mappable region is dependent on the value of RAMHAL.
NOTE As stated, the bits in this register provide read visibility to the system physical memory space allocations defined at system integration. The actual array size for any given type of memory block may differ from the allocated size. Please refer to the device overview chapter for actual sizes.
22.3.2.8
Memory Size Register 1 (MEMSIZ1)
7 6 5 4 3 2 1 0
R ROM_SW1 W Reset --
ROM_SW0
0
0
0
0
PAG_SW1
PAG_SW0
--
--
--
--
--
--
--
= Unimplemented or Reserved
Figure 22-10. Memory Size Register 1 (MEMSIZ1)
Read: Anytime Write: Writes have no effect Reset: Defined at chip integration, see device overview section. The MEMSIZ1 register reflects the state of the FLASH or ROM physical memory space and paging switches at the core boundary which are configured at system integration. This register allows read visibility to the state of these switches.
Table 22-10. MEMSIZ0 Field Descriptions
Field Description
7:6 Allocated System FLASH or ROM Physical Memory Space -- The allocated system FLASH or ROM ROM_SW[1:0] physical memory space is as given in Table 22-11. 1:0 Allocated Off-Chip FLASH or ROM Memory Space -- The allocated off-chip FLASH or ROM memory space PAG_SW[1:0] size is as given in Table 22-12.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 613
Chapter 22 Module Mapping Control (MMCV4)
Table 22-11. Allocated FLASH/ROM Physical Memory Space
rom_sw1:rom_sw0 00 01 10 11 Allocated FLASH or ROM Space 0K byte 16K bytes 48K bytes(1) 64K bytes(1)
NOTES: 1. The ROMHM software bit in the MISC register determines the accessibility of the FLASH/ROM memory space. Please refer to Section 22.3.2.8, "Memory Size Register 1 (MEMSIZ1)," for a detailed functional description of the ROMHM bit.
Table 22-12. Allocated Off-Chip Memory Options
pag_sw1:pag_sw0 00 01 10 11 Off-Chip Space 876K bytes 768K bytes 512K bytes 0K byte On-Chip Space 128K bytes 256K bytes 512K bytes 1M byte
NOTE As stated, the bits in this register provide read visibility to the system memory space and on-chip/off-chip partitioning allocations defined at system integration. The actual array size for any given type of memory block may differ from the allocated size. Please refer to the device overview chapter for actual sizes.
22.3.2.9
Program Page Index Register (PPAGE)
7 6 5 4 3 2 1 0
R W Reset1
0
0 PIX5 PIX4 -- PIX3 -- PIX2 -- PIX1 -- PIX0 --
--
--
--
1. The reset state of this register is controlled at chip integration. Please refer to the device overview section to determine the actual reset state of this register. = Unimplemented or Reserved
Figure 22-11. Program Page Index Register (PPAGE)
Read: Anytime Write: Determined at chip integration. Generally it's: "write anytime in all modes;" on some devices it will be: "write only in special modes." Check specific device documentation to determine which applies. Reset: Defined at chip integration as either 0x00 (paired with write in any mode) or 0x3C (paired with write only in special modes), see device overview chapter.
MC9S12HZ256 Data Sheet, Rev. 2.05 614 Freescale Semiconductor
Chapter 22 Module Mapping Control (MMCV4)
The HCS12 core architecture limits the physical address space available to 64K bytes. The program page index register allows for integrating up to 1M byte of FLASH or ROM into the system by using the six page index bits to page 16K byte blocks into the program page window located from 0x8000 to 0xBFFF as defined in Table 22-14. CALL and RTC instructions have special access to read and write this register without using the address bus. NOTE Normal writes to this register take one cycle to go into effect. Writes to this register using the special access of the CALL and RTC instructions will be complete before the end of the associated instruction.
Table 22-13. MEMSIZ0 Field Descriptions
Field 5:0 PIX[5:0] Description Program Page Index Bits 5:0 -- These page index bits are used to select which of the 64 FLASH or ROM array pages is to be accessed in the program page window as shown in Table 22-14.
Table 22-14. Program Page Index Register Bits
PIX5 0 0 0 0 . . . . . 1 1 1 1 PIX4 0 0 0 0 . . . . . 1 1 1 1 PIX3 0 0 0 0 . . . . 1 1 1 1 PIX2 0 0 0 0 . . . . . 1 1 1 1 PIX1 0 0 1 1 . . . . . 0 0 1 1 PIX0 0 1 0 1 . . . . . 0 1 0 1 Program Space Selected 16K page 0 16K page 1 16K page 2 16K page 3 . . . . . 16K page 60 16K page 61 16K page 62 16K page 63
22.4
Functional Description
The MMC sub-block performs four basic functions of the core operation: bus control, address decoding and select signal generation, memory expansion, and security decoding for the system. Each aspect is described in the following subsections.
22.4.1
Bus Control
The MMC controls the address bus and data buses that interface the core with the rest of the system. This includes the multiplexing of the input data buses to the core onto the main CPU read data bus and control
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 615
Chapter 22 Module Mapping Control (MMCV4)
of data flow from the CPU to the output address and data buses of the core. In addition, the MMC manages all CPU read data bus swapping operations.
22.4.2
Address Decoding
As data flows on the core address bus, the MMC decodes the address information, determines whether the internal core register or firmware space, the peripheral space or a memory register or array space is being addressed and generates the correct select signal. This decoding operation also interprets the mode of operation of the system and the state of the mapping control registers in order to generate the proper select. The MMC also generates two external chip select signals, emulation chip select (ECS) and external chip select (XCS).
22.4.2.1
Select Priority and Mode Considerations
Although internal resources such as control registers and on-chip memory have default addresses, each can be relocated by changing the default values in control registers. Normally, I/O addresses, control registers, vector spaces, expansion windows, and on-chip memory are mapped so that their address ranges do not overlap. The MMC will make only one select signal active at any given time. This activation is based upon the priority outlined in Table 22-15. If two or more blocks share the same address space, only the select signal for the block with the highest priority will become active. An example of this is if the registers and the RAM are mapped to the same space, the registers will have priority over the RAM and the portion of RAM mapped in this shared space will not be accessible. The expansion windows have the lowest priority. This means that registers, vectors, and on-chip memory are always visible to a program regardless of the values in the page select registers.
Table 22-15. Select Signal Priority
Priority Highest ... ... ... ... Lowest Address Space BDM (internal to core) firmware or register space Internal register space RAM memory block EEPROM memory block On-chip FLASH or ROM Remaining external space
In expanded modes, all address space not used by internal resources is by default external memory space. The data registers and data direction registers for ports A and B are removed from the on-chip memory map and become external accesses. If the EME bit in the MODE register (see MEBI block description chapter) is set, the data and data direction registers for port E are also removed from the on-chip memory map and become external accesses. In special peripheral mode, the first 16 registers associated with bus expansion are removed from the on-chip memory map (PORTA, PORTB, DDRA, DDRB, PORTE, DDRE, PEAR, MODE, PUCR, RDRIV, and the EBI reserved registers).
MC9S12HZ256 Data Sheet, Rev. 2.05 616 Freescale Semiconductor
Chapter 22 Module Mapping Control (MMCV4)
In emulation modes, if the EMK bit in the MODE register (see MEBI block description chapter) is set, the data and data direction registers for port K are removed from the on-chip memory map and become external accesses.
22.4.2.2
Emulation Chip Select Signal
When the EMK bit in the MODE register (see MEBI block description chapter) is set, port K bit 7 is used as an active-low emulation chip select signal, ECS. This signal is active when the system is in emulation mode, the EMK bit is set and the FLASH or ROM space is being addressed subject to the conditions outlined in Section 22.4.3.2, "Extended Address (XAB19:14) and ECS Signal Functionality." When the EMK bit is clear, this pin is used for general purpose I/O.
22.4.2.3
External Chip Select Signal
When the EMK bit in the MODE register (see MEBI block description chapter) is set, port K bit 6 is used as an active-low external chip select signal, XCS. This signal is active only when the ECS signal described above is not active and when the system is addressing the external address space. Accesses to unimplemented locations within the register space or to locations that are removed from the map (i.e., ports A and B in expanded modes) will not cause this signal to become active. When the EMK bit is clear, this pin is used for general purpose I/O.
22.4.3
Memory Expansion
The HCS12 core architecture limits the physical address space available to 64K bytes. The program page index register allows for integrating up to 1M byte of FLASH or ROM into the system by using the six page index bits to page 16K byte blocks into the program page window located from 0x8000 to 0xBFFF in the physical memory space. The paged memory space can consist of solely on-chip memory or a combination of on-chip and off-chip memory. This partitioning is configured at system integration through the use of the paging configuration switches (pag_sw1:pag_sw0) at the core boundary. The options available to the integrator are as given in Table 22-16 (this table matches Table 22-12 but is repeated here for easy reference).
Table 22-16. Allocated Off-Chip Memory Options
pag_sw1:pag_sw0 00 01 10 11 Off-Chip Space 876K bytes 768K bytes 512K bytes 0K byte On-Chip Space 128K bytes 256K bytes 512K bytes 1M byte
Based upon the system configuration, the program page window will consider its access to be either internal or external as defined in Table 22-17.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 617
Chapter 22 Module Mapping Control (MMCV4)
Table 22-17. External/Internal Page Window Access
pag_sw1:pag_sw0 00 Partitioning 876K off-Chip, 128K on-Chip 768K off-chip, 256K on-chip 512K off-chip, 512K on-chip 0K off-chip, 1M on-chip PIX5:0 Value 0x0000-0x0037 0x0038-0x003F 0x0000-0x002F 0x0030-0x003F 0x0000-0x001F 0x0020-0x003F N/A 0x0000-0x003F Page Window Access External Internal External Internal External Internal External Internal
01
10
11
NOTE The partitioning as defined in Table 22-17 applies only to the allocated memory space and the actual on-chip memory sizes implemented in the system may differ. Please refer to the device overview chapter for actual sizes. The PPAGE register holds the page select value for the program page window. The value of the PPAGE register can be manipulated by normal read and write (some devices don't allow writes in some modes) instructions as well as the CALL and RTC instructions. Control registers, vector spaces, and a portion of on-chip memory are located in unpaged portions of the 64K byte physical address space. The stack and I/O addresses should also be in unpaged memory to make them accessible from any page. The starting address of a service routine must be located in unpaged memory because the 16-bit exception vectors cannot point to addresses in paged memory. However, a service routine can call other routines that are in paged memory. The upper 16K byte block of memory space (0xC000-0xFFFF) is unpaged. It is recommended that all reset and interrupt vectors point to locations in this area.
22.4.3.1
CALL and Return from Call Instructions
CALL and RTC are uninterruptable instructions that automate page switching in the program expansion window. CALL is similar to a JSR instruction, but the subroutine that is called can be located anywhere in the normal 64K byte address space or on any page of program expansion memory. CALL calculates and stacks a return address, stacks the current PPAGE value, and writes a new instruction-supplied value to PPAGE. The PPAGE value controls which of the 64 possible pages is visible through the 16K byte expansion window in the 64K byte memory map. Execution then begins at the address of the called subroutine. During the execution of a CALL instruction, the CPU: * Writes the old PPAGE value into an internal temporary register and writes the new instruction-supplied PPAGE value into the PPAGE register.
MC9S12HZ256 Data Sheet, Rev. 2.05 618 Freescale Semiconductor
Chapter 22 Module Mapping Control (MMCV4)
* * *
Calculates the address of the next instruction after the CALL instruction (the return address), and pushes this 16-bit value onto the stack. Pushes the old PPAGE value onto the stack. Calculates the effective address of the subroutine, refills the queue, and begins execution at the new address on the selected page of the expansion window.
This sequence is uninterruptable; there is no need to inhibit interrupts during CALL execution. A CALL can be performed from any address in memory to any other address. The PPAGE value supplied by the instruction is part of the effective address. For all addressing mode variations except indexed-indirect modes, the new page value is provided by an immediate operand in the instruction. In indexed-indirect variations of CALL, a pointer specifies memory locations where the new page value and the address of the called subroutine are stored. Using indirect addressing for both the new page value and the address within the page allows values calculated at run time rather than immediate values that must be known at the time of assembly. The RTC instruction terminates subroutines invoked by a CALL instruction. RTC unstacks the PPAGE value and the return address and refills the queue. Execution resumes with the next instruction after the CALL. During the execution of an RTC instruction, the CPU: * Pulls the old PPAGE value from the stack * Pulls the 16-bit return address from the stack and loads it into the PC * Writes the old PPAGE value into the PPAGE register * Refills the queue and resumes execution at the return address This sequence is uninterruptable; an RTC can be executed from anywhere in memory, even from a different page of extended memory in the expansion window. The CALL and RTC instructions behave like JSR and RTS, except they use more execution cycles. Therefore, routinely substituting CALL/RTC for JSR/RTS is not recommended. JSR and RTS can be used to access subroutines that are on the same page in expanded memory. However, a subroutine in expanded memory that can be called from other pages must be terminated with an RTC. And the RTC unstacks a PPAGE value. So any access to the subroutine, even from the same page, must use a CALL instruction so that the correct PPAGE value is in the stack.
22.4.3.2
Extended Address (XAB19:14) and ECS Signal Functionality
If the EMK bit in the MODE register is set (see MEBI block description chapter) the PIX5:0 values will be output on XAB19:14 respectively (port K bits 5:0) when the system is addressing within the physical program page window address space (0x8000-0xBFFF) and is in an expanded mode. When addressing anywhere else within the physical address space (outside of the paging space), the XAB19:14 signals will be assigned a constant value based upon the physical address space selected. In addition, the active-low emulation chip select signal, ECS, will likewise function based upon the assigned memory allocation. In the cases of 48K byte and 64K byte allocated physical FLASH/ROM space, the operation of the ECS signal will additionally depend upon the state of the ROMHM bit (see Section 22.3.2.4, "Miscellaneous System Control Register (MISC)") in the MISC register. Table 22-18, Table 22-19, Table 22-20, and
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 619
Chapter 22 Module Mapping Control (MMCV4)
Table 22-21 summarize the functionality of these signals based upon the allocated memory configuration. Again, this signal information is only available externally when the EMK bit is set and the system is in an expanded mode.
Table 22-18. 0K Byte Physical FLASH/ROM Allocated
Address Space 0x0000-0x3FFF 0x4000-0x7FFF 0x8000-0xBFFF 0xC000-0xFFFF Page Window Access N/A N/A N/A N/A ROMHM N/A N/A N/A N/A ECS 1 1 0 0 XAB19:14 0x3D 0x3E PIX[5:0] 0x3F
Table 22-19. 16K Byte Physical FLASH/ROM Allocated
Address Space 0x0000-0x3FFF 0x4000-0x7FFF 0x8000-0xBFFF 0xC000-0xFFFF Page Window Access N/A N/A N/A N/A ROMHM N/A N/A N/A N/A ECS 1 1 1 0 XAB19:14 0x3D 0x3E PIX[5:0] 0x3F
Table 22-20. 48K Byte Physical FLASH/ROM Allocated
Address Space 0x0000-0x3FFF 0x4000-0x7FFF 0x8000-0xBFFF 0xC000-0xFFFF Page Window Access N/A N/A N/A External Internal N/A ROMHM N/A 0 1 N/A N/A N/A ECS 1 0 1 1 0 0 0x3F PIX[5:0] XAB19:14 0x3D 0x3E
Table 22-21. 64K Byte Physical FLASH/ROM Allocated
Address Space 0x0000-0x3FFF 0x4000-0x7FFF 0x8000-0xBFFF 0xC000-0xFFFF Page Window Access N/A N/A N/A N/A External Internal N/A ROMHM 0 1 0 1 N/A N/A N/A ECS 0 1 0 1 1 0 0 0x3F PIX[5:0] 0x3E XAB19:14 0x3D
MC9S12HZ256 Data Sheet, Rev. 2.05 620 Freescale Semiconductor
Chapter 22 Module Mapping Control (MMCV4)
A graphical example of a memory paging for a system configured as 1M byte on-chip FLASH/ROM with 64K allocated physical space is given in Figure 22-12.
0x0000 61
16K FLASH (UNPAGED)
0x4000
62
16K FLASH (UNPAGED) ONE 16K FLASH/ROM PAGE ACCESSIBLE AT A TIME (SELECTED BY PPAGE = 0 TO 63) 0x8000 0 1 2 3 59 60 61 62 63
16K FLASH (PAGED)
0xC000 63 These 16K FLASH/ROM pages accessible from 0x0000 to 0x7FFF if selected by the ROMHM bit in the MISC register. 16K FLASH (UNPAGED)
0xFF00 0xFFFF VECTORS NORMAL SINGLE CHIP
Figure 22-12. Memory Paging Example: 1M Byte On-Chip FLASH/ROM, 64K Allocation
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 621
Chapter 22 Module Mapping Control (MMCV4)
MC9S12HZ256 Data Sheet, Rev. 2.05 622 Freescale Semiconductor
Appendix A Electrical Characteristics
A.1 General
This supplement contains the most accurate electrical information for the MC9S12HZ256 of microcontrollers available at the time of publication. This introduction is intended to give an overview on several common topics like power supply, current injection etc.
A.1.1
Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate. NOTE This classification is shown in the column labeled "C" in the parameter tables where appropriate. P: Those parameters are guaranteed during production testing on each individual device. C: Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. T: Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. D: Those parameters are derived mainly from simulations.
A.1.2
Power Supply
The MC9S12HZ256 utilizes several pins to supply power to the I/O ports, A/D converter, oscillator and PLL as well as the digital core. The VDDA, VSSA pair supplies the A/D converter and the resistor ladder of the internal voltage regulator. The VDDX1/VSSX1 and VDDX2/VSSX2 pairs supply the I/O pins except PH, PU, PV and PW. VDDR supplies the internal voltage regulator. VDDM1/VSSM1, VDDM2/VSSM2 and VDDM3/VSSM3 pairs supply the ports PH, PU, PV and PW.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 623
Appendix A Electrical Characteristics
VDD1, VSS1 and VSS2 are the supply pins for the digital logic, VDDPLL, VSSPLL supply the oscillator and the PLL. VSS1 and VSS2 are internally connected by metal. VDDA, VDDX1, VDDX2, VDDM as well as VSSA, VSSX1, VSSX2 and VSSM are connected by anti-parallel diodes for ESD protection. NOTE In the following context VDD5 is used for either VDDA, VDDM, VDDR and VDDX1/2; VSS5 is used for either VSSA, VSSR and VSSX unless otherwise noted. IDD5 denotes the sum of the currents flowing into the VDDA, VDDX1/2, VDDM and VDDR pins. VDD is used for VDD1 and VDDPLL, VSS is used for VSS1, VSS2 and VSSPLL. IDD is used for the sum of the currents flowing into VDD1 and VDDPLL.
A.1.3
Pins
There are four groups of functional pins.
A.1.3.1
5V I/O pins
Those I/O pins have a nominal level of 5V. This class of pins is comprised of all port I/O pins, the analog inputs, BKGD and the RESET pins.The internal structure of all those pins is identical, however some of the functionality may be disabled. E.g. for the analog inputs the output drivers, pull-up and pull-down resistors are disabled permanently.
A.1.3.2
Analog Reference
This group is made up by the VRH and VRL pins.
A.1.3.3
Oscillator
The pins XFC, EXTAL, XTAL dedicated to the oscillator have a nominal 2.5V level. They are supplied by VDDPLL.
A.1.3.4
TEST
This pin is used for production testing only.
MC9S12HZ256 Data Sheet, Rev. 2.05 624 Freescale Semiconductor
Appendix A Electrical Characteristics
A.1.4
Current Injection
Power supply must maintain regulation within operating VDD5 or VDD range during instantaneous and operating maximum current conditions. If positive injection current (Vin > VDD5) is greater than IDD5, the injection current may flow out of VDD5 and could result in external power supply going out of regulation. Ensure external VDD5 load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power; e.g. if no system clock is present, or if clock rate is very low which would reduce overall power consumption.
A.1.5
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the device. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either VSS5 or VDD5).
Table A-1. Absolute Maximum Ratings1
Num 1 2 3 4 5 6 7 8 9 10 Rating I/O, Regulator and Analog Supply Voltage Digital Logic Supply Voltage 2 PLL Supply Voltage 2 Voltage difference VDDX1 to VDDX2 to VDDM and VDDA Voltage difference VSSX to VSSR and VSSA Digital I/O Input Voltage Analog Reference XFC, EXTAL, XTAL inputs TEST input Instantaneous Maximum Current Single pin limit for all digital I/O pins except PU and PV
3
Symbol VDD5 VDD VDDPLL VDDX VSSX VIN VRH, VRL VILV VTEST ID
Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -25
Max 6.0 3.0 3.0 0.3 0.3 6.0 6.0 3.0 10.0 +25
Unit V V V V V V V V V mA
11 12 13 14
1
Instantaneous Maximum Current Single pin limit for Port PU and PV 4 Instantaneous Maximum Current Single pin limit for XFC, EXTAL, XTAL5 Instantaneous Maximum Current Single pin limit for TEST 6 Storage Temperature Range
ID IDL IDT T
stg
-55 -25 -0.25 - 65
+55 +25 0 155
mA mA mA C
Beyond absolute maximum ratings device might be damaged.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 625
Appendix A Electrical Characteristics
2 3 4 5 6
The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. The absolute maximum ratings apply when the device is powered from an external source. All digital I/O pins are internally clamped to VSSX1/2 and VDDX1/2, VSSM and VDDM or VSSA and VDDA. Ports PU and PV are internally clamped to VSSM and VDDM. Those pins are internally clamped to VSSPLL and VDDPLL. This pin is clamped low to VSSPLL, but not clamped high. This pin must be tied low in applications.
A.1.6
ESD Protection and Latch-up Immunity
All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body Model (HBM), the Machine Model (MM) and the Charge Device Model. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification.
Table A-2. ESD and Latch-up Test Conditions
Model Human Body Series Resistance Storage Capacitance Number of Pulse per pin positive negative Machine Series Resistance Storage Capacitance Number of Pulse per pin positive negative Latch-up Minimum input voltage limit Maximum input voltage limit Description Symbol R1 C - Value 1500 100 - 3 3 0 200 - 3 3 -2.5 7.5 V V W pF Unit W pF
R1 C -
Table A-3. ESD and Latch-Up Protection Characteristics
Num C 1 2 3 Rating Symbol VHBM VMM VCDM Min 2000 200 500 Max - - - Unit V V V
C Human Body Model (HBM) C Machine Model (MM) C Charge Device Model (CDM)
MC9S12HZ256 Data Sheet, Rev. 2.05 626 Freescale Semiconductor
Appendix A Electrical Characteristics
Table A-3. ESD and Latch-Up Protection Characteristics
4 C Latch-up Current at TA = 125C positive negative C Latch-up Current at TA = 27C positive negative ILAT +100 -100 ILAT +200 -200 - - mA mA
5
A.1.7
Operating Conditions
This chapter describes the operating conditions of the device. Unless otherwise noted those conditions apply to all the following data. NOTE Please refer to the temperature rating of the device (C, V, M) with regards to the ambient temperature TA and the junction temperature TJ. For power dissipation calculations refer to Section A.1.8, "Power Dissipation and Thermal Characteristics."
Table A-4. Operating Conditions
Rating I/O, Regulator and Analog Supply Voltage Digital Logic Supply Voltage 1 PLL Supply Voltage 2 Voltage Difference VDDX to VDDR and VDDA Voltage Difference VSSX to VSSR and VSSA Crystal oscillator (Colpitts) Crystal oscillator (Pierce) Bus Frequency Operating Junction Temperature Range C parts V parts M parts Operating Ambient Temperature Range2 C parts V parts M parts
1
Symbol VDD5 VDD VDDPLL VDDX VSSX fosc fosc fbus
Min 4.5 2.35 2.35 -0.1 -0.1 0.5 0.5 0.5
Typ 5 2.5 2.5 0 0 - - -
Max 5.5 2.75 2.75 0.1 0.1 16 40 25 100 120 140 85 105 125
Unit V V V V V MHz MHz MHz
T
J
-40
-
C
TA
-40
27
C
The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. The absolute maximum ratings apply when this regulator is disabled and the device is powered from an external source. 2 Please refer to Section A.1.8, "Power Dissipation and Thermal Characteristics," for more details about the relation between ambient temperature TA and device junction temperature TJ.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 627
Appendix A Electrical Characteristics
A.1.8
Power Dissipation and Thermal Characteristics
Power dissipation and thermal characteristics are closely related. The user must assure that the maximum operating junction temperature is not exceeded. The average chip-junction temperature (TJ) in C can be obtained from: T J = T A + ( P D * JA ) T J = Junction Temperature, [C ] T A = Ambient Temperature, [C ] P D = Total Chip Power Dissipation, [W] JA = Package Thermal Resistance, [C/W] The total power dissipation can be calculated from: P D = P INT + P IO P INT = Chip Internal Power Dissipation, [W] P INT = I DDR V DDR + I DDA V DDA P IO =
RDSON IIOi
i
2
PIO is the sum of all output currents on I/O ports associated with VDDX1,2 and VDDM1,2,3.
Table A-5. Thermal Package Characteristics1
Num C 1 2 3 4 5 6 7 8 9 10
1
Rating
Symbol JA JA JB JC JT JA JA JB JC JT
Min - - -- -- -- -- -- -- -- --
Typ - - -- -- -- -- -- -- -- --
Max 54 41 31 11 2 51 41 27 14 3
Unit
oC/W oC/W oC/W oC/W oC/W oC/W oC/W oC/W oC/W oC/W
T Thermal Resistance LQFP112, single sided PCB2 T Thermal Resistance LQFP112, double sided PCB with 2 internal planes3 T Junction to Board LQFP112 T Junction to Case LQFP112 T Junction to Package Top LQFP112 T Thermal Resistance QFP 80, single sided PCB T Thermal Resistance QFP 80, double sided PCB with 2 internal planes T Junction to Board QFP80 T Junction to Case QFP80 T Junction to Package Top QFP80
The values for thermal resistance are achieved by package simulations
MC9S12HZ256 Data Sheet, Rev. 2.05 628 Freescale Semiconductor
Appendix A Electrical Characteristics
2 3
PC Board according to EIA/JEDEC Standard 51-2 PC Board according to EIA/JEDEC Standard 51-7
A.1.9
I/O Characteristics
This section describes the characteristics of all 5V I/O pins. All parameters are not always applicable, e.g. not all pins feature pull up/down resistances.
Table A-6. 5V I/O Characteristics
Conditions are shown in Table A-4 unless otherwise noted Num C 1 2 3 4 P Input High Voltage P Input Low Voltage C Input Hysteresis P Input Leakage Current except PU, PV (pins in high impedance input mode)1 Vin = VDD5 or VSS5 P Input Leakage Current PU, PV (pins in high impedance input mode)2 Vin = VDD5 or VSS5 P Output High Voltage (pins in output mode, except PU and PV) Partial Drive IOH = -1.0mA Full Drive IOH = -10mA P Output Low Voltage (pins in output mode except PU and PV) Partial Drive IOL = +1.0mA Full Drive IOL = +10mA P Output High Voltage (pins PU and PV in output mode) IOH = -20mA (typical value at 25C) P Output Low Voltage (pins PU and PV in output mode) IOL = +20mA (typical value at 25C) C Output Rise Time (pins PU and PV in output mode with slew control enabled) VDD5=5V, Rload=1K, 10% to 90% of VOH C Output Fall Time (pins PU and PV in output mode with slew control enabled) VDD5=5V, Rload=1K, 10% to 90% of VOH P Internal Pull Up Device Current, tested at V Max.
IL
Rating
Symbol V
IH
Min 0.65*VDD5 VSS5 - 0.3
Typ - - 250
Max VDD5 + 0.3 0.35*VDD5
Unit V V mV
VIL VHYS Iin
-1.0
-
1.0
A
5
Iin
-2.5
-
2.5
A
6
V
OH
VDD5 - 0.8
-
-
V
7
V
OL
-
-
0.8
V
8 9 10
VOH V
OL
VDD5 - 0.32 VDD5 - 0.2 - 60 .2 100
- 0.32 130
V V ns
tr
11
tf
60
100
130
ns
12 13 14
IPUL IPUH IPDH
- -10 -
- - -
-130 - 130
A A A
P Internal Pull Up Device Current, tested at V Min.
IH
P Internal Pull Down Device Current, tested at V Min.
IH
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 629
Appendix A Electrical Characteristics
Table A-6. 5V I/O Characteristics
Conditions are shown in Table A-4 unless otherwise noted 15 16 17 P Internal Pull Down Device Current, tested at V Max.
IL
IPDL Cin IICS IICP tPULSE tPULSE
10
- 6 -
- - 2.5 25 3
A pF mA
D Input Capacitance T Injection current3 Single Pin limit Total Device Limit. Sum of all injected currents P Port AD Interrupt Input Pulse filtered4 P Port AD Interrupt Input Pulse passed4
-2.5 -25
18 19
1
s s
10
Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for each 8 C to 12 C in the temper ature range from 50 C to 125 C . 2 Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for each 8 C to 12 C in the temper ature range from 50 C to 125 C . 3 Refer to Section A.1.4, "Current Injection," for more details 4 Parameter only applies in STOP or Pseudo STOP mode.
A.1.10
Supply Currents
This section describes the current consumption characteristics of the device as well as the conditions for the measurements.
A.1.10.1
Measurement Conditions
All measurements are without output loads. Unless otherwise noted the currents are measured in single chip mode, internal voltage regulator enabled and at 16MHz bus frequency using a 4MHz oscillator in Colpitts mode. Production testing is performed using a square wave signal at the EXTAL input.
A.1.10.2
Additional Remarks
In expanded modes the currents flowing in the system are highly dependent on the load at the address, data and control signals as well as on the duty cycle of those signals. No generally applicable numbers can be given. A very good estimate is to take the single chip currents and add the currents due to the external loads.
MC9S12HZ256 Data Sheet, Rev. 2.05 630 Freescale Semiconductor
Appendix A Electrical Characteristics
Table A-7. Supply Current Characteristics
Conditions are shown in Table A-4 unless otherwise noted Num C 1 2 P P 3 C P C C P C P C P 4 C C C C C C C 5 C P C C P C P C P
1 2
Rating
Symbol IDD5 IDDW
Min
Typ
Max 65
Unit mA mA
P Run supply currents Single Chip, Internal regulator enabled Wait Supply current All modules enabled, PLL on only RTI enabled 1 Pseudo Stop Current (RTI and COP disabled) 1, 2 -40C 27C 70C 85C C Temp Option 100C 105C V Temp Option 120C 125C M Temp Option 140 C Pseudo Stop Current (RTI and COP enabled) 1, 2 -40C 27C 70C 85C 105C 125C 140C Stop Current 2 -40C 27C 70C 85C C Temp Option 100C 105C V Temp Option 120C 125C M Temp Option 140C
40 5 IDDPS 360 420 760 800 950 1000 1500 1700 2500 IDDPS 420 480 820 860 1050 1700 2500 IDDS 20 40 200 300 550 700 1200 1400 2200 100 A 520 A
2000 3300 4800 A
1500 2900 4500
PLL off At those low power dissipation levels TJ = TA can be assumed
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 631
Appendix A Electrical Characteristics
A.2
ATD
This section describes the characteristics of the analog to digital converter.
A.2.1
ATD Operating Characteristics
The Table A-8 shows conditions under which the ATD operates. The following constraints exist to obtain full-scale, full range results: VSSA VRL VIN VRH VDDA. This constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that it ties to. If the input level goes outside of this range it will effectively be clipped.
Table A-8. ATD Operating Characteristics
Conditions are shown in Table A-4 unless otherwise noted Num C 1 D Reference Potential Low High 2 3 4 C Differential Reference Voltage1 D ATD Clock Frequency D ATD 10-Bit Conversion Period Clock Cycles2 Conv, Time at 2.0MHz ATD Clock fATDCLK 5 D ATD 8-Bit Conversion Period Clock Cycles2 Conv, Time at 2.0MHz ATD Clock fATDCLK 6 7
1 2
Rating
Symbol VRL VRH VRH-VRL fATDCLK NCONV10 TCONV10 NCONV8 TCONV8 tSR IREF
Min VSSA VDDA/2 4.50 0.5 14 7
Typ
Max VDDA/2 VDDA
Unit V V V MHz Cycles s
5.00
5.25 2.0 28 14
12 6
26 13 20 0.375
Cycles s s mA
D Stop Recovery Time (VDDA=5.0 Volts) P Reference Supply current
Full accuracy is not guaranteed when differential voltage is less than 4.50V The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample period of 16 ATD clocks.
A.2.2
Factors influencing accuracy
Three factors - source resistance, source capacitance and current injection - have an influence on the accuracy of the ATD.
A.2.2.1
Source Resistance:
Due to the input pin leakage current as specified in Table A-6 in conjunction with the source resistance there will be a voltage drop from the signal source to the ATD input. The maximum source resistance RS specifies results in an error of less than 1/2 LSB (2.5mV) at the maximum leakage current. If device or operating conditions are less than worst case or leakage-induced error is acceptable, larger values of source resistance is allowed.
MC9S12HZ256 Data Sheet, Rev. 2.05 632 Freescale Semiconductor
Appendix A Electrical Characteristics
A.2.2.2
Source Capacitance
When sampling an additional internal capacitor is switched to the input. This can cause a voltage drop due to charge sharing with the external and the pin capacitance. For a maximum sampling error of the input voltage 1LSB, then the external filter capacitor, Cf 1024 * (CINS- CINN).
A.2.2.3
Current Injection
There are two cases to consider. 1. A current is injected into the channel being converted. The channel being stressed has conversion values of $3FF ($FF in 8-bit mode) for analog inputs greater than VRH and $000 for values less than VRL unless the current is higher than specified as disruptive condition. 2. Current is injected into pins in the neighborhood of the channel being converted. A portion of this current is picked up by the channel (coupling ratio K), This additional current impacts the accuracy of the conversion depending on the source resistance. The additional input voltage error on the converted channel can be calculated as VERR = K * RS * IINJ, with IINJ being the sum of the currents injected into the two pins adjacent to the converted channel.
Table A-9. ATD Electrical Characteristics
Conditions are shown in Table A-4 unless otherwise noted Num C 1 2 Rating Symbol RS CINN CINS INA Kp Kn -2.5 Min - Typ - Max 1 10 22 2.5 10-4 10-2 mA A/A A/A Unit K pF
C Max input Source Resistance T Total Input Capacitance Non Sampling Sampling C Disruptive Analog Input Current C Coupling Ratio positive current injection C Coupling Ratio negative current injection
3 4 5
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 633
Appendix A Electrical Characteristics
A.2.3
ATD accuracy
Table A-10 specifies the ATD conversion performance excluding any errors due to current injection, input capacitance and source resistance.
Table A-10. ATD Conversion Performance
Conditions are shown in Table A-4 unless otherwise noted VREF = VRH - VRL = 5.12V. Resulting to one 8 bit count = 20mV and one 10 bit count = 5mV fATDCLK = 2.0MHz Num C 1 2 3 4 5 6 7 8 9 10
1
Rating
Symbol LSB DNL INL
1
Min
Typ 5
Max
Unit mV
P 10-Bit Resolution P 10-Bit Differential Nonlinearity P 10-Bit Integral Nonlinearity P 10-Bit Absolute Error (Port AD) P 10-Bit Absolute Error (Port P 8-Bit Resolution P 8-Bit Differential Nonlinearity P 8-Bit Integral Nonlinearity P 8-Bit Absolute Error (Port AD) P 8-Bit Absolute Error (Port L)1
1
-1 -2.5 -3 -4 1.5 2.0 3.0 20 -0.5 -1.0 -1.5 -2.0 0.5 1.0 1.5
1 2.5 3 4
Counts Counts Counts Counts mV
AE AE LSB DNL INL AE AE
L)1
0.5 1.0 1.5 2.0
Counts Counts Counts Counts
These values include the quantization error which is inherently 1/2 count for any A/D converter.
For the following definitions see also Figure A-1. Differential Non-Linearity (DNL) is defined as the difference between two adjacent switching steps.
Vi - Vi - 1 DNL ( i ) = ------------------------ - 1 1LSB
The Integral Non-Linearity (INL) is defined as the sum of all DNLs: n Vn - V0
INL ( n ) =
DNL ( i ) =
i=1
------------------- - n 1LSB
MC9S12HZ256 Data Sheet, Rev. 2.05 634 Freescale Semiconductor
Appendix A Electrical Characteristics
DNL
LSB Vi-1
$3FF $3FE $3FD $3FC $3FB $3FA $3F9 $3F8 $3F7 $3F6 $3F5
10-Bit Absolute Error Boundary Vi 8-Bit Absolute Error Boundary
$FF
$FE
10-Bit Resolution
$3F4 $3F3
$FD
9 8 7 6 5 4 3 2 1 0 5 10 15 20 25 30 35 40 45
Ideal Transfer Curve
2
10-Bit Transfer Curve
1
8-Bit Transfer Curve
5055 5060 5065 5070 5075 5080 5085 5090 5095 5100 5105 5110 5115 5120
Vin mV
Figure A-1. ATD Accuracy Definitions
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 635
8-Bit Resolution
Appendix A Electrical Characteristics
A.3
NVM, Flash and EEPROM
NOTE Unless otherwise noted the abbreviation NVM (Non Volatile Memory) is used for both Flash and EEPROM.
A.3.1
NVM timing
The time base for all NVM program or erase operations is derived from the oscillator. A minimum oscillator frequency fNVMOSC is required for performing program or erase operations. The NVM modules do not have any means to monitor the frequency and will not prevent program or erase operation at frequencies above or below the specified minimum. Attempting to program or erase the NVM modules at a lower frequency a full program or erase transition is not assured. The Flash and EEPROM program and erase operations are timed using a clock derived from the oscillator using the FCLKDIV and ECLKDIV registers respectively. The frequency of this clock must be set within the limits specified as fNVMOP. The minimum program and erase times shown in Table A-11 are calculated for maximum fNVMOP and maximum fbus. The maximum times are calculated for minimum fNVMOP and a fbus of 2MHz.
A.3.1.1
Single Word Programming
The programming time for single word programming is dependant on the bus frequency as a well as on the frequency fNVMOP and can be calculated according to the following formula.
1 1 t swpgm = 9 --------------------- + 25 ---------f NVMOP f bus
Row Programming
A.3.1.2
Flash programming where up to 32 words in a row can be programmed consecutively by keeping the command pipeline filled. The time to program a consecutive word can be calculated as:
1 1 t bwpgm = 4 --------------------- + 9 ---------f NVMOP f bus
The time to program a whole row is:
t brpgm = t swpgm + 31 t bwpgm
Row programming is more than 2 times faster than single word programming.
A.3.1.3
Sector Erase
Erasing a 512 byte Flash sector or a 4 byte EEPROM sector takes:
1 t era 4000 --------------------f NVMOP
MC9S12HZ256 Data Sheet, Rev. 2.05 636 Freescale Semiconductor
Appendix A Electrical Characteristics
The setup time can be ignored for this operation.
A.3.1.4
Mass Erase
Erasing a NVM block takes:
The setup time can be ignored for this operation.
1 t mass 20000 --------------------f NVMOP
Blank Check
A.3.1.5
The time it takes to perform a blank check on the Flash or EEPROM is dependant on the location of the first non-blank word starting at relative address zero. It takes one bus cycle per word to verify plus a setup of the command.
t check location t cyc + 10 t cyc
Table A-11. NVM Timing Characteristics
Conditions are shown in Table A-4 unless otherwise noted Num C 1 2 3 4 5 6 7 8 9 10
1 2
Rating
Symbol fNVMOSC fNVMBUS fNVMOP tswpgm tbwpgm tbrpgm tera tmass tcheck tcheck
Min 0.5 1 150 46
2
Typ
Max 50 1
Unit MHz MHz
D External Oscillator Clock D Bus frequency for Programming or Erase Operations D Operating Frequency P Single Word Programming Time D Flash Burst Programming consecutive word 4 D Flash Burst Programming Time for 32 Words 4 P Sector Erase Time P Mass Erase Time D Blank Check Time Flash per block D Blank Check Time EEPROM per block
200 74.5
3
kHz s s s ms ms tcyc tcyc
20.4 2 678.4 2 20
5 5
31 3 1035.5 3 26.7 133
3 3
100
11 6 11 6
32778 7 20587
Restrictions for oscillator in crystal mode apply! Minimum Programming times are achieved under maximum NVM operating frequency fNVMOP and maximum bus frequency fbus. Maximum Erase and Programming times are achieved under particular combinations of fNVMOP and bus frequency fbus. Refer to formulae in Sections Section A.3.1.1, "Single Word Programming," through Section A.3.1.4, "Mass Erase," for guidance. urst Programming operations are not applicable to EEPROM Minimum Erase times are achieved under maximum NVM operating frequency fNVMOP. Minimum time, if first word in the array is not blank Maximum time to complete check on an erased block
3 4 5 6 7
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 637
Appendix A Electrical Characteristics
A.3.2
NVM Reliability
The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process monitors and burn-in to screen early life failures. The failure rates for data retention and program/erase cycling are specified at the operating conditions noted. The program/erase cycle count on the sector is incremented every time a sector or mass erase event is executed. NOTE All values shown in Table A-12 are target values and subject to further extensive characterization.
Table A-12. NVM Reliability Characteristics
Conditions are shown in Table A-4 unless otherwise noted Num C 1 2 3 4 Rating Symbol tNVMRET nFLPE nEEPE nEEPE Min 15 1000 10,000 100,000 10,000 Typ Max Unit Years Cycles Cycles Cycles
C Data Retention at an average junction temperature of TJavg = 70C C Flash number of Program/Erase cycles C EEPROM number of Program/Erase cycles (-40C TJ 0C) C EEPROM number of Program/Erase cycles (0C < TJ 140C)
MC9S12HZ256 Data Sheet, Rev. 2.05 638 Freescale Semiconductor
Appendix A Electrical Characteristics
A.4
A.4.1
Voltage Regulator
Operating Conditions
Table A-13. Voltage Regulator - Operating Conditions
Conditions are shown in Table A-4 unless otherwise noted Num 1 2 3 C P P P Characteristic Input Voltages Regulator Current Shutdown Mode Output Voltage Core Full Performance Mode Shutdown Mode Output Voltage PLL Full Performance Mode Shutdown Mode Low Voltage Interrupt3 Assert Level Deassert Level Low Voltage Reset4 Assert Level Power-on Reset5 Assert Level Deassert Level Symbol VVDDR,A IREG -- VDD 2.35 -- 2.35 -- 4.0 4.15 2.25 0.97 -- 12 2.5 --1 2.5 --2 4.37 4.52 -- -- -- 40 2.75 -- 2.75 -- 4.66 4.77 -- -- 2.05 Min 4.5 Typical -- Max 5.5 Unit V A V V V V V V V V V
4
P
VDDPLL
7
P
VLVIA VLVID VLVRA VPORA VPORD
8 9
P C
1 2
High Impedance Output High Impedance Output 3 Monitors V DDA, active only in Full Performance Mode. Indicates I/O & ADC performance degradation due to low supply voltage. 4 Monitors V , active only in Full Performance Mode. MCU is monitored by the POR in RPM (see Figure A-2) DD 5 Monitors V . Active in all modes. DD
A.4.2
Chip Power-up and Voltage Drops
The voltage regulator sub modules LVI (low voltage interrupt), POR (power-on reset) and LVR (low voltage reset) handle chip power-up or drops of the supply voltage. Their function is described in Figure A-2.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 639
Appendix A Electrical Characteristics
Figure A-2. Voltage Regulator - Chip Power-up and Voltage Drops (not scaled)
V
VLVID VLVIA
VDDA
VDD
VLVRD VLVRA VPORD
t
LVI
LVI enabled
POR
LVI disabled due to LVR
LVR
A.4.3
A.4.3.1
Output Loads
Resistive Loads
On-chip voltage regulator intended to supply the internal logic and oscillator circuits allows no external DC loads.
A.4.3.2
Capacitive Loads
The capacitive loads are specified in Table A-14. Ceramic capacitors with X7R dielectricum are required.
MC9S12HZ256 Data Sheet, Rev. 2.05 640 Freescale Semiconductor
Appendix A Electrical Characteristics
Table A-14. Voltage Regulator - Capacitive Loads
Num 1 3 Characteristic VDD external capacitive load VDDPLL external capacitive load Symbol CDDext CDDPLLext Min 200 90 Typical 440 220 Max 12000 5000 Unit nF nF
A.5
Reset, Oscillator and PLL
This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and Phase-Locked-Loop (PLL).
A.5.1
Startup
Table A-15 summarizes several startup characteristics explained in this section. Detailed description of the startup behavior can be found in the Clock and Reset Generator (CRG) Block User Guide.
Table A-15. Startup Characteristics
Conditions are shown in Table A-4 unless otherwise noted Num C 1 2 3 4 5 6 T POR release level T POR assert level D Reset input pulse width, minimum input time D Startup from Reset D Interrupt pulse width, IRQ edge-sensitive mode D Wait recovery startup time Rating Symbol VPORR VPORA PWRSTL nRST PWIRQ tWRS 0.97 2 192 20 14 196 Min Typ Max 2.07 Unit V V tosc nosc ns tcyc
A.5.1.1
POR
The release level VPORR and the assert level VPORA are derived from the VDD supply. They are also valid if the device is powered externally. After releasing the POR reset the oscillator and the clock quality check are started. If after a time tCQOUT no valid oscillation is detected, the MCU will start using the internal self clock. The fastest startup time possible is given by nuposc.
A.5.1.2
SRAM Data Retention
Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing code when VDD5 is out of specification limits, the SRAM contents integrity is guaranteed if after the reset the PORF bit in the CRG Flags Register has not been set.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 641
Appendix A Electrical Characteristics
A.5.1.3
External Reset
When external reset is asserted for a time greater than PWRSTL the CRG module generates an internal reset, and the CPU starts fetching the reset vector without doing a clock quality check, if there was an oscillation before reset.
A.5.1.4
Stop Recovery
Out of STOP the controller can be woken up by an external interrupt. A clock quality check as after POR is performed before releasing the clocks to the system.
A.5.1.5
Pseudo Stop and Wait Recovery
The recovery from Pseudo STOP and Wait are essentially the same since the oscillator was not stopped in both modes. The controller can be woken up by internal or external interrupts. After twrs the CPU starts fetching the interrupt vector.
MC9S12HZ256 Data Sheet, Rev. 2.05 642 Freescale Semiconductor
Appendix A Electrical Characteristics
A.5.2
Oscillator
The device features an internal Colpitts and Pierce oscillator. The selection of Colpitts oscillator or Pierce oscillator/external clock depends on the XCLKS signal which is sampled during reset. Pierce oscillator/external clock mode allows the input of a square wave. Before asserting the oscillator to the internal system clocks the quality of the oscillation is checked for each start from either power-on, STOP or oscillator fail. tCQOUT specifies the maximum time before switching to the internal self clock mode after POR or STOP if a proper oscillation is not detected. The quality check also determines the minimum oscillator start-up time tUPOSC. The device also features a clock monitor. A Clock Monitor Failure is asserted if the frequency of the incoming clock signal is below the Assert Frequency fCMFA.
Table A-16. Oscillator Characteristics
Conditions are shown in Table A-4 unless otherwise noted Num C 1a 1b 2 3 4 5 6 7 8 9 10 11 12 13 Rating Symbol fOSC fOSC iOSC tUPOSC tCQOUT fCMFA fEXT tEXTL tEXTH tEXTR tEXTF CIN VDCBIAS VIH,EXTAL VIH,EXTAL VIL,EXTAL VIL,EXTAL VHYS,EXTAL VSSPLL - 0.3 250 0.75*VDDPLL VDDPLL + 0.3 0.25*VDDPLL 7 1.1 0.45 50 0.5 9.5 9.5 1 1 100 Min 0.5 0.5 100 82 100
3
Typ
Max 16 40
Unit MHz MHz A ms s KHz MHz ns ns ns ns pF V V V V V mV
C Crystal oscillator range (Colpitts) C Crystal oscillator range (Pierce) 1 P Startup Current C Oscillator start-up time (Colpitts) D Clock Quality check time-out P Clock Monitor Failure Assert Frequency P External square wave input frequency 4 D External square wave pulse width low
4 4
2.5 200 50
D External square wave pulse width high D External square wave rise time4 D External square wave fall time4
D Input Capacitance (EXTAL, XTAL pins) C DC Operating Bias in Colpitts Configuration on EXTAL Pin P EXTAL Pin Input High Voltage4 T EXTAL Pin Input High Voltage4
14
P EXTAL Pin Input Low Voltage4 T EXTAL Pin Input Low Voltage
4
15
1 2
C EXTAL Pin Input Hysteresis
4
Depending on the crystal a damping series resistor might be necessary fosc = 4MHz, C = 22pF. 3 Maximum value is for extreme cases using high Q, low frequency crystals 4 Only valid if Pierce oscillator/external clock mode is selected
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 643
Appendix A Electrical Characteristics
A.5.3
Phase Locked Loop
The oscillator provides the reference clock for the PLL. The PLLs Voltage Controlled Oscillator (VCO) is also the system clock source in self clock mode.
A.5.3.1
XFC Component Selection
This section describes the selection of the XFC components to achieve a good filter characteristics.
VDDPLL Cs R Phase fosc 1 refdv+1 fref fcmp K Detector Loop Divider 1 synr+1 VCO KV fvco Cp
1 2
Figure A-3. Basic PLL Functional Diagram
The following procedure can be used to calculate the resistance and capacitance values using typical values for K1, f1 and ich from Table A-17. The VCO Gain at the desired VCO output frequency is approximated by: ( f 1 - f vco ) ---------------------K 1 1V KV = K1 e The phase detector relationship is given by:
K = i ch K V
ich is the current in tracking mode. The loop bandwidth fC should be chosen to fulfill the Gardner's stability criteria by at least a factor of 10, typical values are 50. = 0.9 ensures a good transient response.
MC9S12HZ256 Data Sheet, Rev. 2.05 644 Freescale Semiconductor
And finally the frequency relationship is defined as
2 f ref f ref 1 f C < ------------------------------------------ ----- f C < ------------ ;( = 0.9 ) 4 50 50 2 + 1 + f VCO n = ------------ = 2 ( synr + 1 ) f ref
Appendix A Electrical Characteristics
With the above inputs the resistance can be calculated as:
2 n fC R = ---------------------------K
The capacitance Cs can now be calculated as:
0.516 2 C s = --------------------- -------------- ;( = 0.9 ) fC R fC R
The capacitance Cp should be chosen in the range of:
2
C s 20 C p C s 10
The stabilization delays shown in Table A-17 are dependant on PLL operational settings and external component selection (e.g. crystal, XFC filter).
A.5.3.2
Jitter Information
The basic functionality of the PLL is shown in Figure A-3. With each transition of the clock fcmp, the deviation from the reference clock fref is measured and input voltage to the VCO is adjusted accordingly.The adjustment is done continuously with no abrupt changes in the clock output frequency. Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock jitter. This jitter affects the real minimum and maximum clock periods as illustrated in Figure A-4.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 645
Appendix A Electrical Characteristics
0
1
2
3
N-1
N
tmin1 tnom tmax1 tminN tmaxN
Figure A-4. Jitter Definitions
The relative deviation of tnom is at its maximum for one clock period, and decreases towards zero for larger number of clock periods (N). Defining the jitter as:
t max ( N ) t min ( N ) J ( N ) = max 1 - -------------------- , 1 - -------------------- N t nom N t nom
For N < 100, the following equation is a good fit for the maximum jitter:
j1 J ( N ) = ------- + j 2 N
J(N)
1
5
10
20
N
Figure A-5. Maximum bus clock jitter approximation
This is very important to notice with respect to timers, serial modules where a pre-scaler will eliminate the effect of the jitter to a large extent.
MC9S12HZ256 Data Sheet, Rev. 2.05 646 Freescale Semiconductor
Appendix A Electrical Characteristics
Table A-17. PLL Characteristics
Conditions are shown in Table A-4 unless otherwise noted Num C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1 2
Rating
Symbol fSCM fVCO |trk| |Lock| |unl| |unt| tstab tacq tal K1 f1 | ich | | ich | j1 j2
Min 1 8 3 0 0.5 6
Typ
Max 5.5 50 4 1.5 2.5 8
Unit MHz MHz %1 %1 %1 %1 ms ms ms MHz/V MHz A A
P Self Clock Mode frequency D VCO locking range D Lock Detector transition from Acquisition to Tracking mode D Lock Detection D Un-Lock Detection D Lock Detector transition from Tracking to Acquisition mode C PLLON Total Stabilization delay (Auto Mode) 2 D PLLON Acquisition mode stabilization delay 2 D PLLON Tracking mode stabilization delay D Fitting parameter VCO loop gain D Fitting parameter VCO loop frequency D Charge pump current acquisition mode D Charge pump current tracking mode C Jitter fit parameter 1
2 2
0.5 0.3 0.2 -100 60 38.5 3.5 1.1 0.13
% %
C Jitter fit parameter 2 2
% deviation from target frequency fREF = 4MHz, fBUS = 25MHz equivalent fVCO = 50MHz: REFDV = #$03, SYNR = #$18, Cs = 4.7nF, Cp = 470pF, Rs = 10K.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 647
Appendix A Electrical Characteristics
A.6
MSCAN
Table A-18. MSCAN Wake-up Pulse Characteristics
Conditions are shown in Table A-4 unless otherwise noted Num C 1 2 Rating Symbol tWUP tWUP 5 Min Typ Max 2 Unit s s
P MSCAN Wake-up dominant pulse filtered P MSCAN Wake-up dominant pulse pass
A.7
A.7.1
SPI
Master Mode
Figure A-6 and Figure A-7 illustrate the master mode timing. Timing values are shown in Table A-19.
SS1 (OUTPUT) 2 SCK (CPOL = 0) (OUTPUT) SCK (CPOL = 1) (OUTPUT) 5 MISO (INPUT) 9 MOSI (OUTPUT)
1. If configured as output. 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
1 4 4
11
3
12
6 MSB IN2 BIT 6 . . . 1 9 MSB OUT2 BIT 6 . . . 1 LSB OUT LSB IN 10
Figure A-6. SPI Master Timing (CPHA = 0)
MC9S12HZ256 Data Sheet, Rev. 2.05 648 Freescale Semiconductor
Appendix A Electrical Characteristics
SS1 (OUTPUT) 1 2 SCK (CPOL = 0) (OUTPUT) 4 SCK (CPOL = 1) (OUTPUT) 5 MISO (INPUT) 9 MOSI (OUTPUT)PORT DATA
1. If configured as output 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
12
11
3
4
11
12
6 MSB IN2 BIT 6 . . . 1 10 LSB IN
MASTER MSB OUT2
BIT 6 . . . 1
MASTER LSB OUT
PORT DATA
Figure A-7. SPI Master Timing (CPHA =1) Table A-19. SPI Master Mode Timing Characteristics1
Conditions are shown in Table A-4 unless otherwise noted, CLOAD = 200pF on all outputs Num C 1 1 2 3 4 5 6 9 10 11 12
1
Rating
Symbol fop tsck tlead tlag twsck tsu thi tv tho tr tf
Min DC 4 1/2 1/2 tbus - 30 25 0
Typ
Max 1/4 2048 --
Unit fbus tbus tsck tsck
P Operating Frequency P SCK Period tsck = 1./fop D Enable Lead Time D Enable Lag Time D Clock (SCK) High or Low Time D Data Setup Time (Inputs) D Data Hold Time (Inputs) D Data Valid (after SCK Edge) D Data Hold Time (Outputs) D Rise Time Inputs and Outputs D Fall Time Inputs and Outputs
1024 tbus
ns ns ns
25 0 25 25
ns ns ns ns
The numbers 7, 8 in the column labeled "Num" are missing. This has been done on purpose to be consistent between the Master and the Slave timing shown in Table A-20.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 649
Appendix A Electrical Characteristics
A.7.2
Slave Mode
Figure A-8 and Figure A-9 illustrate the slave mode timing. Timing values are shown in Figure A-20.
SS (INPUT) 1 SCK (CPOL = 0) (INPUT) 2 SCK (CPOL = 1) (INPUT) 7 MISO (OUTPUT) SLAVE MSB OUT 5 MOSI (INPUT) 6 MSB IN BIT 6 . . . 1 LSB IN 9 BIT 6 . . . 1 4 4 11 12 8 10 10 12 11 3
SLAVE LSB OUT
Figure A-8. SPI Slave Timing (CPHA = 0)
SS (INPUT) 1 2 SCK (CPOL = 0) (INPUT) 4 SCK (CPOL = 1) (INPUT) 9 MISO (OUTPUT) 7 MOSI (INPUT) SLAVE MSB OUT 5 MSB IN 6 BIT 6 . . . 1 LSB IN 4 11 12 12 11 3
10 BIT 6 . . . 1 SLAVE LSB OUT
8
Figure A-9. SPI Slave Timing (CPHA =1)
MC9S12HZ256 Data Sheet, Rev. 2.05 650 Freescale Semiconductor
Appendix A Electrical Characteristics
Table A-20. SPI Slave Mode Timing Characteristics
Conditions are shown in Table A-4 unless otherwise noted, CLOAD = 200pF on all outputs Num C 1 1 2 3 4 5 6 7 8 9 10 11 12 P Operating Frequency P SCK Period tsck = 1./fop D Enable Lead Time D Enable Lag Time D Clock (SCK) High or Low Time D Data Setup Time (Inputs) D Data Hold Time (Inputs) D Slave Access Time D Slave MISO Disable Time D Data Valid (after SCK Edge) D Data Hold Time (Outputs) D Rise Time Inputs and Outputs D Fall Time Inputs and Outputs Rating Symbol fop tsck tlead tlag twsck tsu thi ta tdis tv tho tr tf 0 25 25 Min DC 4 1 1 tcyc - 30 25 25 1 1 25 Typ Max 1/4 2048 Unit fbus tbus tcyc tcyc ns ns ns tcyc tcyc ns ns ns ns
A.8
LCD_32F4B
Table A-21. LCD_32F4B Driver Electrical Characteristics
Characteristic Symbol VLCD ZBP/FP Min. -0.25 Typ. Max. VDDX + 0.25 5.0 Unit V k
LCD Supply Voltage LCD Output Impedance(BP[3:0],FP[31:0]) for outputs to charge to higher voltage level or to GND 1 LCD Output Current (BP[3:0],FP[31:0]) for outputs to discharge to lower voltage level except GND 2
1 2
IBP/FP
50
-
-
uA
Outputs measured one at a time, low impedance voltage source connected to the VLCD pin. Outputs measured one at a time, low impedance voltage source connected to the VLCD pin.
A.9
External Bus Timing
A timing diagram of the external multiplexed-bus is illustrated in Figure A-10 with the actual timing values shown on table Table A-22. All major bus signals are included in the diagram. While both a data write and data read cycle are shown, only one or the other would occur on a particular bus cycle. The expanded bus timings are highly dependent on the load conditions. The timing parameters shown assume a balanced load across all outputs.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 651
Appendix A Electrical Characteristics
1, 2 3 ECLK PE4 5 9 Addr/Data (read) PA, PB data 6 15 addr 7 12 Addr/Data (write) PA, PB data addr 8 14 data 13 16 10 data 11 4
17 Non-Multiplexed Addresses PK5:0 20 ECS PK7
18
19
21
22
23
24 R/W PE2
25
26
27 LSTRB PE3
28
29
30 NOACC PE7
31
32
33 IPIPO0 IPIPO1, PE6,5
34
35
36
Figure A-10. General External Bus Timing
MC9S12HZ256 Data Sheet, Rev. 2.05 652 Freescale Semiconductor
Appendix A Electrical Characteristics
Table A-22. Expanded Bus Timing Characteristics (5V Range)
Conditions are 4.75V < VDDX < 5.25V, Junction Temperature -40C to +140C, CLOAD = 50pF Num 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 C P P D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D Rating Frequency of operation (E-clock) Cycle time Pulse width, E low Pulse width, E high Address delay time Address valid time to E rise (PWEL-tAD) Muxed address hold time Address hold to data valid Data hold to address Read data setup time Read data hold time Write data delay time Write data hold time Write data setup time1 (PWEH-tDDW) Address access time E high access
1 (t cyc-tAD-tDSR) 1
Symbol fo tcyc PWEL PWEH tAD tAV tMAH tAHDS tDHA tDSR tDHR tDDW tDHW tDSW tACCA tACCE tNAD tNAV tNAH tCSD tACCS tCSH tCSN tRWD tRWV tRWH tLSD tLSV tLSH tNOD tNOV tNOH tP0D tP0V
Min 0 40 19 19
Typ
Max 25.0
Unit MHz ns ns ns
8 11 2 7 2 13 0 7 2 12 19 6 6 14 2 16 11 2 8 7 14 2 7 14 2 7 14 2 2 11 7
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
time1 (PWEH-tDSR)
Non-multiplexed address delay time Non-muxed address valid to E rise (PWEL-tNAD) Non-multiplexed address hold time Chip select delay time Chip select access time1 (tcyc-tCSD-tDSR) Chip select hold time Chip select negated time Read/write delay time Read/write valid time to E rise (PWEL-tRWD) Read/write hold time Low strobe delay time Low strobe valid time to E rise (PWEL-tLSD) Low strobe hold time NOACC strobe delay time NOACC valid time to E rise (PWEL-tNOD) NOACC hold time IPIPO[1:0] delay time IPIPO[1:0] valid time to E rise (PWEL-tP0D)
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 653
Appendix A Electrical Characteristics
Table A-22. Expanded Bus Timing Characteristics (5V Range)
Conditions are 4.75V < VDDX < 5.25V, Junction Temperature -40C to +140C, CLOAD = 50pF 35 36
1
D D
IPIPO[1:0] delay time1 (PWEH-tP1V) IPIPO[1:0] valid time to E fall
tP1D tP1V
2 11
25
ns ns
Affected by clock stretch: add N x tcyc where N=0,1,2 or 3, depending on the number of clock stretches.
MC9S12HZ256 Data Sheet, Rev. 2.05 654 Freescale Semiconductor
Appendix B PCB Layout Guidelines
Appendix B PCB Layout Guidelines
The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as of the MCU itself. The following rules must be observed: * Every supply pair must be decoupled by a ceramic/tantalum capacitor connected as near as possible to the corresponding pins (C1-C9). * Central point of the ground star should be the VSS1 pin. * Use low ohmic low inductance connections between VSS1, VSS2, VSSA, VSSX1,2 and VSSM1,2,3. * VSSPLL must be directly connected to VSS1. * Keep traces of VSSPLL, EXTAL and XTAL as short as possible and occupied board area for C10, C11, C14 and Q1 as small as possible. * Do not place other signals or supplies underneath area occupied by C10, C11, C14 and Q1 and the connection area to the MCU. * Central power input should be fed in at the VDDA/VSSA pins.
Table B-1. Recommended Components
Component C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 R1 Q1 Purpose VDD1 filter cap VDDA filter cap VDDX2 filter cap VDDR filter cap VDDM3 filter cap VDDM2 filter cap VDDM1 filter cap VDDX1 filter cap VDDPLL filter cap OSC load cap OSC load cap PLL loop filter cap PLL loop filter cap DC cutoff cap PLL loop filter res Quartz/Resonator Type ceramic X7R X7R/tantalum X7R/tantalum X7R/tantalum X7R/tantalum X7R/tantalum X7R/tantalum X7R/tantalum ceramic X7R Value 100 .. 220 nF >=100 nF >=100 nF >=100 nF >=100 nF >=100 nF >=100 nF >=100 nF 100 nF .. 220 nF
See CRG block description chapter
Example layouts are illustrated on Figure B-1 and Figure B-2.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 655
Appendix B PCB Layout Guidelines
C8
VSSX1
VDDX1
VDDM1 C7 VSSM1 VSS1 C1 VDDM2 C6 VSSM2 VDD1
VDDA
VDDM3 C2 C5 VSSM3 VSSA
C3
C4
VDDR/
C14
C9
C10
C11
VDDX2
Q1 C12 R1 C13 VSSPLL VDDPLL
Figure B-1. Recommended PCB Layout for 112-pin LQFP
MC9S12HZ256 Data Sheet, Rev. 2.05 656 Freescale Semiconductor
Appendix B PCB Layout Guidelines
C8
VSSX1
VDDX1
VSS1 VDDM2 C6 VSSM2 C1 VDD1
VDDA C2 VSSA
C3
C4
VDDR/
C14
C9
C10
C11
VDDX2
Q1 C12 R1 C13 VSSPLL VDDPLL
Figure B-2. Recommended PCB Layout for 80-pin QFP
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 657
Appendix C Package Information
Appendix C Package Information
This section provides the physical dimensions of the MC9S12HZ256 packages.
MC9S12HZ256 Data Sheet, Rev. 2.05 658 Freescale Semiconductor
Appendix C Package Information
C.1
112-Pin LQFP Package
4X
0.20 T L-M N
112
4X 28 TIPS 85 84
0.20 T L-M N
J1 J1 C L
4X
P
PIN 1 IDENT 1
VIEW Y
108X
G
X X=L, M OR N
VIEW Y B L M B1 V1 V
J
AA
28
57
F D 0.13
M
BASE METAL
29
56
T L-M N
N A1 S1 A S
SECTION J1-J1 ROTATED 90 COUNTERCLOCKWISE
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DATUMS L, M AND N TO BE DETERMINED AT SEATING PLANE, DATUM T. 4. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE, DATUM T. 5. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE. DIMENSIONS A AND B INCLUDE MOLD MISMATCH. 6. DIMENSION D DOES NOT INCLUDE DAMBAR MILLIMETERS MIN MAX 20.000 BSC 10.000 BSC 20.000 BSC 10.000 BSC --1.600 0.050 0.150 1.350 1.450 0.270 0.370 0.450 0.750 0.270 0.330 0.650 BSC 0.090 0.170 0.500 REF 0.325 BSC 0.100 0.200 0.100 0.200 22.000 BSC 11.000 BSC 22.000 BSC 11.000 BSC 0.250 REF 1.000 REF 0.090 0.160 8 0 7 3 11 13 11 13
C2 C 0.050 2
VIEW AB 0.10 T
112X
SEATING PLANE
3 T
R
R2 0.25
GAGE PLANE
R
R1
C1 (Y) (Z) VIEW AB
(K) E
1
DIM A A1 B B1 C C1 C2 D E F G J K P R1 R2 S S1 V V1 Y Z AA 1 2 3
Figure C-1. 112-Pin LQFP Mechanical Dimensions (case no. 987)
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 659
Appendix C Package Information
C.2
80-Pin QFP Package
L
60 61 41 40
S
S
B B P
D
S
-AL
-BB
0.20 M H A-B
V 0.05 D
0.20 M C A-B
S
D
-A-,-B-,-DDETAIL A
DETAIL A
80 1 20
21
-DA 0.20 M H A-B 0.05 A-B S 0.20 M C A-B
S S
F
D
S
J D
S
N
E C -CSEATING PLANE
M DETAIL C -HH G
DATUM PLANE
D 0.20
M
C A-B
S
D
S
SECTION B-B
VIEW ROTATED 90
0.10 M
U T
DATUM -HPLANE
R
K W X DETAIL C
Q
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -A-, -B- AND -D- TO BE DETERMINED AT DATUM PLANE -H-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -C-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT.
DIM A B C D E F G H J K L M N P Q R S T U V W X
MILLIMETERS MIN MAX 13.90 14.10 13.90 14.10 2.15 2.45 0.22 0.38 2.00 2.40 0.22 0.33 0.65 BSC --0.25 0.13 0.23 0.65 0.95 12.35 REF 5 10 0.13 0.17 0.325 BSC 0 7 0.13 0.30 16.95 17.45 0.13 --0 --16.95 17.45 0.35 0.45 1.6 REF
Figure C-2. 80-Pin QFP Mechanical Dimensions (case no. 841B)
MC9S12HZ256 Data Sheet, Rev. 2.05 660 Freescale Semiconductor
Appendix D Derivative Differences
Appendix D Derivative Differences
Table D-1 shows the different options for the MC9S12HZ256 members.
Table D-1. Package, Memory and Peripheral Options for MC9S12HZ256 members
Device Package Flash ROM RAM EEPROM CAN SCI SPI IIC SSD LCD Motor A/D PWM TIM I/O 0 0 0 0 12K 6K 4K 4K 2K 2K 1K 1K 0 0 0 0 0 0 2 2 1 1 0 0 2 1 1 1 0 0 1 0 2 2 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 0 1 0 1 1 1 0 1 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 4 4 4 4 4 4 4 4 4 4 4 4 4 4 32x4 32x4 24x4 20x4 24x4 20x4 32x4 32x4 24x4 20x4 24x4 20x4 20x4 20x4 16/4 16/4 16/4 16/4 16/4 16/4 16/4 16/4 16/4 16/4 16/4 16/4 16/4 16/4 1/16 6-ch 8-ch 85 1/16 6-ch 8-ch 85 1/8 1/7 1/8 1/7 4-ch 8-ch 69 4-ch 4-ch 59 4-ch 8-ch 69 4-ch 4-ch 59
MC9S12HZ256 112 LQFP 256K MC9S12HZ128 112 LQFP 128K MC9S12HZ64 MC9S12HN64 112 LQFP 80 QFP 112 LQFP 80 QFP 64K 64K 0 0 0 0 0 0
MC3S12HZ256 112 LQFP MC3S12HZ128 112 LQFP MC3S12HZ64 MC3S12HN64 MC3S12HZ32 MC3S12HN32 112 LQFP 80 QFP 112 LQFP 80 QFP 80 QFP 80 QFP
256K 12K 128K 64K 64K 32K 32K 6K 4K 4K 2K 2K
1/16 6-ch 8-ch 85 1/16 6-ch 8-ch 85 1/8 1/7 1/8 1/7 1/7 1/7 4-ch 8-ch 69 4-ch 4-ch 59 4-ch 8-ch 69 4-ch 4-ch 59 4-ch 4-ch 59 4-ch 4-ch 59
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 661
Appendix E ROM Description
Appendix E ROM Description
E.1 Memory Map and Register Definition
ROM control registers are located in the same place as the 16-byte memory space for Flash control registers 0x0100-0x010F. There are no EEPROM control registers in a ROM device and register locations 0x0110-0x011F are reserved.
Table E-1. ROM Memory Map Address
0x0100 0x0101 0x0102 0x0103 0x01040x010B 0x010C 0x010D 0x010E 0x010F
Use
Reserved ROM Options Register (ROPT) Reserved ROM Configuration Register (RCNFG) Reserved Device SC number byte0 (DSC0) Device SC number byte1 (DSC1) Device SC number byte2 (DSC2) Reserved
Access
Read Read Read Read/Write Read Read Read Read Read
E.1.1
ROM Options Register (ROPT)
Upon reset the contents of the non-volatile location NVOPT are copied from ROM into ROPT. This register may be read at any time, but writes have no meaning or effect.
7 6 5 4 3 2 1 0
R W Reset
KEYEN1
KEYEN0
NV5
NV4
NV3
NV2
SEC1
SEC0
R
R
R
R
R
R
R
R
= Unimplemented or Reserved
R = Read from ROM
Figure E-1. ROM Options Register (ROPT)
MC9S12HZ256 Data Sheet, Rev. 2.05 662 Freescale Semiconductor
Appendix E ROM Description
Table E-2. ROPT Field Descriptions
Field Description
7:6 Backdoor Key Mechanism Enable -- Determines the state of the ROM backdoor key access. If the backdoor KEYEN[1:0] key mechanism is enabled, user firmware can write a 4-words value that matches the non-volatile backdoor key (NVBACKKEY through NVBACKKEY+7 in that order) to temporarily disengage security until the next reset. The backdoor key mechanism is accessible only from user (secured) firmware. BDM commands cannot be used to write key comparison values that would unlock the backdoor key. If disabled, no backdoor key access is allowed. The backdoor keywords 0x0000 and 0xFFFF are invalid and will effectively disable the backdoor key access when used. 00 Disabled 01 Disabled (preferred KEYEN state to disable backdoor key access) 10 Enabled 11 Enabled 5:2 NV[5:2] 1:0 SEC[1:0] Non-volatile flag bits -- This bits are available to the user. Security State Code -- Determines the security state of the MCU. 00 Secured 01 Secured 10 Unsecured 11 Secured
E.1.2
ROM Configuration Register (RCNFG)
7 6 5 4 3 2 1 0
R W Reset
0
0 KEYACC
0
0
0
0
0
R
R
R
R
R
R
R
R
= Unimplemented or Reserved
Figure E-2. ROM Configuration Register (RCNFG) Table E-3. RCNFG Field Descriptions
Field 5 KEYACC Description Security Access Key Write Enable -- Enables writes to the backdoor comparison key to disable security. This bit can not be set unless the KEYEN1:KEYEN0 bits are 10. This bit can not be written through BDM. 0 Backdoor key access enabled 1 Backdoor key access disabled
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 663
Appendix E ROM Description
E.1.3
Device SC Number Registers
This register contains a copy of the Device SC number which is stored in the non-volatile registers at addresses 0xFF0C, 0xFF0D and 0xFF0E.
7 6 5 4 3 2 1 0
R W Reset R R R R
DSCn
R
R
R
R
= Unimplemented or Reserved
Figure E-3. Device SC Number (DSCn) Table E-4. DSCn Field Descriptions
Field 7:0 DSCn Description Device SC Number byte n (n= 0,1 or 2) -- Reads Device SC number
E.1.4
Non-volatile Registers
A range of addresses in the ROM is reserved for the security bits and backdoor key. In addition, some locations are reserved for the ROM device SC number and for the 32 bit CRC value used by the BIST control.
Table E-5. Non-volatile Register Summary Address Register Name
0xFF00 - NVBACKKEY 0xFF07 0xFF08 0xFF09 0xFF0A 0xFF0B 0xFF0C 0xFF0D 0xFF0E 0xFF0F NVCRC0 NVCRC1 NVCRC2 NVCRC3 NVSC0 NVSC1 NVSC2 NVOPT KEYEN1 KEYEN0 NV5
7
6
5
4
3
2
1
0
8-Byte Comparison Key CRC value byte0 CRC value byte1 CRC value byte2 CRC value byte3 Device SC number byte0 Device SC number byte1 Device SC number byte2 NV4 NV3 NV2 SEC1 SEC0
NOTE Please note that backdoor keywords 0x0000 or 0xFFFF are invalid and will effectively disable backdoor key access when used.
MC9S12HZ256 Data Sheet, Rev. 2.05 664 Freescale Semiconductor
Appendix E ROM Description
E.2
ROM Security
The ROM module provides the necessary security information to the rest of the chip. After each reset, the ROM module determines the security state of the microcontroller as defined in section Section E.1.1, "ROM Options Register (ROPT)". If the NVM Options byte at 0xFF0F in the NVM Options Field is in secure state, any reset will cause the microcontroller to return to the secure operating mode
E.2.1
Security and Backdoor Key Access definition
Security is engaged or disengaged based on the state of two non-volatile register bits (SEC1:SEC0) in the ROPT register. During reset, the contents of the non-volatile location NVOPT are copied from ROM into the working ROPT register in high-page register space. A user engages security by defining the security bits in the NVOPT location to select security enabled. This data is included along with the ROM program and data file which is delivered when ordering a ROM device. The SEC1=1:SEC0=0 state disengages security while the other three combinations engage security. In a similar manner the user can choose to allow or disallow a security unlocking mechanism through an 8-byte backdoor security key. There is no way to disable security unless the non-volatile KEYEN1:KEYEN0 bits in NVOPT/ROPT are set to 1:0. NOTE The backdoor key is also used to protect access to internal product analysis features. No product analysis will be possible on a secured ROM if backdoor key access is disabled or keywords are invalid.
E.2.2
Unsecuring the MCU using the Backdoor Key Access
Provided that the key access is permitted, security can be disabled by the backdoor access sequence described below: 1. Writing 1 to KEYACC in the RCNFG register. This causes the ROM control logic to interpret writes to the backdoor comparison key locations (NVBACKKEY through NVBACKKEY+7) as values to be compared against the key rather than as writes to ROM locations. 2. Writing the correct four 16-bit key values to addresses NVBACKKEY through NVBACKKEY+7 locations. These writes must be done in order starting with the value for NVBACKKEY and ending with NVBACKKEY+7. User software normally would get the key codes from outside the MCU system through a communication interface such as a serial I/O. 3. Writing 0 to KEYACC in the RCNFG register. If the 8-byte key that was just written matches the key stored in the backdoor comparison key locations, SEC1:SEC0 in the ROPT register are automatically changed to 10 and security will be disengaged until the next POR. The security key can be written only from a secure memory, so it cannot be entered through background commands without the cooperation of a secure user program.
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 665
Appendix F Ordering Information
Appendix F Ordering Information
Figure F-1 provides an ordering example for the MC9S12HZ256. Package Options AL = 112LQFP AA = 80QFP Package Option Temperature Option Maskset Revision Fab Code Device Title Controller Family Main Memory Type Order Marking Temperature Options C = -40C to 85C V = -40C to 105C M = -40C to 125C Fab Code J = TSMC3 Main Memory Type 9 = Flash 3 = ROM Order Marking MC = Generic S = Mask Specific
S 9 S12 HZ256 J 3 C AL
Figure F-1. Order Part Number Coding
Customers who place orders using the generic MC part numbers which are constructed using the above rules will automatically receive the preferred maskset. If the product is updated in the future and a newer maskset is put into production, then the newer maskset may automatically ship against these generic MC part numbers. If required, a customer can specify a particular maskset when ordering product. Orders placed against a "S" part number will only receive one specific maskset. If a new maskset is made available, customers will be notified by PCN (Process Change Notification) but will have to order against a different "S" part number in order to receive the new maskset.
MC9S12HZ256 Data Sheet, Rev. 2.05 666 Freescale Semiconductor
Appendix G Detailed Register Map
Appendix G Detailed Register Map
The following tables show the detailed register map of the MC9S12HZ256.
0x0000-0x000F MEBI Map 1 of 3 (HCS12 Multiplexed External Bus Interface)
Address Name 7 6 5 4 3 2 1 0
0x0000 0x0001 0x0002 0x0003 0x0004- 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C 0x000D 0x000E 0x000F
PORTA PORTB DDRA DDRB Reserved PORTE DDRE PEAR MODE PUCR RDRIV EBICTL Reserved
R Bit 7 W R Bit 7 W R Bit 7 W R Bit 7 W R 0 W R Bit 7 W R Bit 7 W R NOACCE W R MODC W R PUPKE W R RDPK W R 0 W R 0 W
6 6 6 6 0
5 5 5 5 0
4 4 4 4 0
3 3 3 3 0
2 2 2 2 0
1 1 1 1 0 Bit 1 0 0
Bit 0 Bit 0 Bit 0 Bit 0 0 Bit 0 0 0
6 6 0
5 5 PIPOE MODA 0 0 0 0
4 4 NECLK 0
3 3 LSTRE IVIS 0 0 0 0
2 Bit 2 RDWE 0 0 0 0 0
MODB 0 0 0 0
EMK PUPBE RDPB 0 0
EME PUPAE RDPA ESTR 0
PUPEE RDPE 0 0
0x0010-0x0014
Address Name
MMC Map 1 of 4 (HCS12 Module Mapping Control)
7 6 5 4 3 2 1 0
0x0010 0x0011 0x0012 0x0013 0x0014
INITRM INITRG INITEE MISC MTST0 Test Only
R W R W R W R W R W
RAM15 0
RAM14 REG14 EE14 0 6
RAM13 REG13 EE13 0 5
RAM12 REG12 EE12 0 4
RAM11 REG11 EE11 EXSTR1 3
0 0 0
0 0 0
RAMHAL 0
EE15 0 Bit 7
EEON ROMON Bit 0
EXSTR0 2
ROMHM 1
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 667
Appendix G Detailed Register Map
0x0015-0x0016
Address Name
INT Map 1 of 2 (HCS12 Interrupt)
7 6 5 4 3 2 1 0
0x0015 0x0016
ITCR ITEST
R W R W
0
0
0
WRINT INT8
ADR3 INT6
ADR2 INT4
ADR1 INT2
ADR0 INT0
INTE
INTC
INTA
0x0017-0x0017
Address Name
MMC Map 2 of 4 (HCS12 Module Mapping Control)
7 6 5 4 3 2 1 0
0x0017
MTST1 Test Only
R W
Bit 7
6
5
4
3
2
1
Bit 0
0x0018-0x0018
Address Name
Miscellaneous Peripherals
7 6 5 4 3 2 1 0
0x0018
Reserved
R W
0
0
0
0
0
0
0
0
0x0019-0x0019
Address Name
VREG3V3 (Voltage Regulator)
7 6 5 4 3 2 1 0
0x0019
VREGCTRL
R W
0
0
0
0
0
LVDS
LVIE
LVIF
0x001A-0x001B Miscellaneous Peripherals
Address Name 7 6 5 4 3 2 1 0
0x001A 0x001B
PARTIDH PARTIDL
R W R W
ID15 ID7
ID14 ID6
ID13 ID5
ID12 ID4
ID11 ID3
ID10 ID2
ID9 ID1
ID8 ID0
0x001C-0x001D MMC Map 3 of 4 (HCS12 Module Mapping Control)
Address Name 7 6 5 4 3 2 1 0
0x001C 0x001D
MEMSIZ0 MEMSIZ1
R reg_sw0 W R rom_sw1 W
0 rom_sw0
eep_sw1 0
eep_sw0 0
0 0
ram_sw2 0
ram_sw1 pag_sw1
ram_sw0 pag_sw0
0x001E-0x001E MEBI map 2 of 3 (HCS12 Multiplexed External Bus Interface)
Address Name 7 6 5 4 3 2 1 0
0x001E
INTCR
R W
IRQE
IRQEN
0
0
0
0
0
0
MC9S12HZ256 Data Sheet, Rev. 2.05 668 Freescale Semiconductor
Appendix G Detailed Register Map
0x001F-0x001F INT map 2 of 2 (HCS12 Interrupt)
Address Name 7 6 5 4 3 2 1 0
0x001F
HPRIO
R W
PSEL7
PSEL6
PSEL5
PSEL4
PSEL3
PSEL2
PSEL1
0
0x0020-0x002F DBG (including BKP) map 1of 1 (HCS12 Debug)
Address Name 7 6 5 4 3 2 1 0
0x0020 0x0021 0x0022 0x0023 0x0024 0x0025 0x0026 0x0027 0x0028 0x0029 0x002A 0x002B 0x002C 0x002D 0x002E 0x002F
DBGC1 DBGSC DBGTBH DBGTBL DBGCNT DBGCCX DBGCCH DBGCCL DBGC2 BKPCT0 DBGC3 BKPCT1 DBGCAX BKP0X DBGCAH BKP0H DBGCAL BKP0L DBGCBX BKP1X DBGCBH BKP1H DBGCBL BKP1L
R DBGEN ARM W R AF BF W R Bit 15 Bit 14 W R Bit 7 Bit 6 W R TBF 0 W R PAGSEL W R Bit 15 14 W R Bit 7 6 W R BKABEN FULL W R BKAMBH BKAMBL W R PAGSEL W R Bit 15 14 W R Bit 7 6 W R PAGSEL W R Bit 15 14 W R Bit 7 6 W
TRGSEL CF Bit 13 Bit 5
BEGIN 0 Bit 12 Bit 4
DBGBRK
0
CAPMOD TRG
Bit 11 Bit 3 CNT
Bit 10 Bit 2
Bit 9 Bit 1
Bit 8 Bit 0
EXTCMP 13 5 BDM BKBMBH 12 4 TAGAB BKBMBL 11 3 BKCEN RWAEN 10 2 TAGC RWA 9 1 RWCEN RWBEN Bit 8 Bit 0 RWC RWB
EXTCMP 13 5 12 4 11 3 EXTCMP 13 5 12 4 11 3 10 2 9 1 Bit 8 Bit 0 10 2 9 1 Bit 8 Bit 0
0x0030-0x0031
Address Name
MMC map 4 of 4 (HCS12 Module Mapping Control)
7 6 5 4 3 2 1 0
0x0030 0x0031
PPAGE Reserved
R W R W
0 0
0 0
PIX5 0
PIX4 0
PIX3 0
PIX2 0
PIX1 0
PIX0 0
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 669
Appendix G Detailed Register Map
0x0032-0x0033
Address Name
MEBI map 3 of 3 (HCS12 Multiplexed External Bus Interface)
7 6 5 4 3 2 1 0
0x0032 0x0033
PORTK DDRK
R W R W
Bit 7 Bit 7
6 6
5 5
4 4
3 3
2 2
1 1
Bit 0 Bit 0
0x0034-0x003F CRG (Clock and Reset Generator)
Address Name 7 6 5 4 3 2 1 0
0x0034 0x0035 0x0036 0x0037 0x0038 0x0039 0x003A 0x003B 0x003C 0x003D 0x003E 0x003F
SYNR REFDV CTFLG TEST ONLY CRGFLG CRGINT CLKSEL PLLCTL RTICTL COPCTL FORBYP TEST ONLY CTCTL TEST ONLY ARMCOP
R W R W R W R W R W R W R W R W R W R W R W R W
0 0 0
0 0 0
SYN5 0 0
SYN4 0 0
SYN3 REFDV3 0 LOCK 0
SYN2 REFDV2 0 TRACK 0
SYN1 REFDV1 0
SYN0 REFDV0 0 SCM 0
RTIF RTIE PLLSEL CME 0
PORF 0
LVRF 0
LOCKIF LOCKIE ROAWAI ACQ RTR4 0 0 0 0 4
SCMIF SCMIE RTIWAI PCE RTR1 CR1 0 0 0 1
PSTP PLLON RTR6 RSBCK 0 0 0 6
SYSWAI AUTO RTR5 0 0 0 0 5
PLLWAI 0
CWAI PRE RTR2 CR2 0 0 0 2
COPWAI SCME RTR0 CR0 0 0 0 Bit 0
RTR3 0 0 0 0 3
WCOP 0 0 0 Bit 7
0x0040-0x006F TIM (Timer 16 Bit 8 Channels) (Sheet 1 of 3)
Address Name 7 6 5 4 3 2 1 0
0x0040 0x0041 0x0042 0x0043 0x0044
TIOS CFORC OC7M OC7D TCNT (hi)
R W R W R W R W R W
IOS7 0 FOC7 OC7M7 OC7D7 Bit 15
IOS6 0 FOC6 OC7M6 OC7D6 14
IOS5 0 FOC5 OC7M5 OC7D5 13
IOS4 0 FOC4 OC7M4 OC7D4 12
IOS3 0 FOC3 OC7M3 OC7D3 11
IOS2 0 FOC2 OC7M2 OC7D2 10
IOS1 0 FOC1 OC7M1 OC7D1 9
IOS0 0 FOC0 OC7M0 OC7D0 Bit 8
MC9S12HZ256 Data Sheet, Rev. 2.05 670 Freescale Semiconductor
Appendix G Detailed Register Map
0x0040-0x006F TIM (Timer 16 Bit 8 Channels) (Sheet 2 of 3)
Address Name 7 6 5 4 3 2 1 0
0x0045 0x0046 0x0047 0x0048 0x0049 0x004A 0x004B 0x004C 0x004D 0x004E 0x004F 0x0050 0x0051 0x0052 0x0053 0x0054 0x0055 0x0056 0x0057 0x0058 0x0059 0x005A 0x005B
TCNT (lo) TSCR1 TTOV TCTL1 TCTL2 TCTL3 TCTL4 TIE TSCR2 TFLG1 TFLG2 TC0 (hi) TC0 (lo) TC1 (hi) TC1 (lo) TC2 (hi) TC2 (lo) TC3 (hi) TC3 (lo) TC4 (hi) TC4 (lo) TC5 (hi) TC5 (lo)
R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W
Bit 7
6
5
4
3 0
2 0
1 0
Bit 0 0
TEN TOV7 OM7 OM3 EDG7B EDG3B C7I TOI C7F TOF Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7
TSWAI TOV6 OL7 OL3 EDG7A EDG3A C6I 0
TSFRZ TOV5 OM6 OM2 EDG6B EDG2B C5I 0
TFFCA TOV4 OL6 OL2 EDG6A EDG2A C4I 0
TOV3 OM5 OM1 EDG5B EDG1B C3I TCRE C3F 0
TOV2 OL5 OL1 EDG5A EDG1A C2I PR2 C2F 0
TOV1 OM4 OM0 EDG4B EDG0B C1I PR1 C1F 0
TOV0 OL4 OL0 EDG4A EDG0A C0I PR0 C0F 0
C6F 0
C5F 0
C4F 0
14 6 14 6 14 6 14 6 14 6 14 6
13 5 13 5 13 5 13 5 13 5 13 5
12 4 12 4 12 4 12 4 12 4 12 4
11 3 11 3 11 3 11 3 11 3 11 3
10 2 10 2 10 2 10 2 10 2 10 2
9 1 9 1 9 1 9 1 9 1 9 1
Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 671
Appendix G Detailed Register Map
0x0040-0x006F TIM (Timer 16 Bit 8 Channels) (Sheet 3 of 3)
Address Name 7 6 5 4 3 2 1 0
0x005C 0x005D 0x005E 0x005F 0x0060 0x0061 0x0062 0x0063 0x0064- 0x006C 0x006D 0x006E- 0x006F
TC6 (hi) TC6 (lo) TC7 (hi) TC7 (lo) PACTL PAFLG PACNT (hi) PACNT (lo) Reserved TIMTST Test Only Reserved
R W R W R W R W R W R W R W R W R W R W R W
Bit 15 Bit 7 Bit 15 Bit 7 0 0
14 6 14 6 PAEN 0
13 5 13 5 PAMOD 0
12 4 12 4 PEDGE 0
11 3 11 3 CLK1 0
10 2 10 2 CLK0 0
9 1 9 1 PAOVI PAOVF 1 1
Bit 8 Bit 0 Bit 8 Bit 0 PAI PAIF Bit 0 Bit 0
Bit 7 Bit 7
6 6
5 5
4 4
3 3
2 2
0
0
0
0
0
0
TCBYP
PCBYP
0x0070-0x007F Reserved
Address Name 7 6 5 4 3 2 1 0
0x0070- 0x007F
Reserved
R W
0
0
0
0
0
0
0
0
0x0080-0x00AF ATD (Analog-to-Digital Converter 10 Bit 16 Channel) (Sheet 1 of 3)
Address Name 7 6 5 4 3 2 1 0
0x0080 0x0081 0x0082 0x0083 0x0084 0x0085 0x0086
ATDCTL0 ATDCTL1 ATDCTL2 ATDCTL3 ATDCTL4 ATDCTL5 ATDSTAT0
R W R W R W R W R W R W R W
0 0
0 0
0 0
0 0
WRAP3
WRAP2
WRAP1
WRAP0
ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0 ETRIGP S1C PRS3 CD CC3 ETRIG FIFO PRS2 CC CC2 ASCIE FRZ1 PRS1 CB CC1 ASCIF
ADPU 0
AFFC S8C SMP1 DSGN 0
AWAI S4C SMP0 SCAN ETORF
ETRIGLE S2C PRS4 MULT FIFOR
FRZ0 PRS0 CA CC0
SRES8 DJM SCF
MC9S12HZ256 Data Sheet, Rev. 2.05 672 Freescale Semiconductor
Appendix G Detailed Register Map
0x0080-0x00AF ATD (Analog-to-Digital Converter 10 Bit 16 Channel) (Sheet 2 of 3)
Address Name 7 6 5 4 3 2 1 0
0x0087 0x0088 0x0089 0x008A 0x008B 0x008C 0x008D 0x008E 0x008F 0x0090 0x0091 0x0092 0x0093 0x0094 0x0095 0x0096 0x0097 0x0098 0x0099 0x009A 0x009B 0x009C 0x009D
Reserved ATDTEST0 ATDTEST1 ATDSTAT2 ATDSTAT1 ATDDIEN0 ATDDIEN1 PORTAD0 PORTAD1 ATDDR0H ATDDR0L ATDDR1H ATDDR1L ATDDR2H ATDDR2L ATDDR3H ATDDR3L ATDDR4H ATDDR4L ATDDR5H ATDDR5L ATDDR6H ATDDR6L
R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W
0 SAR9 SAR1 CCF15 CCF7
0 SAR8 SAR0 CCF14 CCF6
0 SAR7 0 CCF13 CCF5
0 SAR6 0 CCF12 CCF4
0 SAR5 0 CCF11 CCF3
0 SAR4
0 SAR3 ATDCLK CCF9 CCF1
0 SAR2
RST CCF10 CCF2
SC CCF8 CCF0
Bit 15 Bit 7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7
14 6 14 6 14 6 14 6 14 6 14 6 14 6 14 6 14 6
13 5 13 5 13 5 13 5 13 5 13 5 13 5 13 5 13 5
12 4 12 4 12 4 12 4 12 4 12 4 12 4 12 4 12 4
11 3 11 3 11 3 11 3 11 3 11 3 11 3 11 3 11 3
10 2 10 2 10 2 10 2 10 2 10 2 10 2 10 2 10 2
9 1 9 1 9 1 9 1 9 1 9 1 9 1 9 1 9 1
Bit 8 Bit 0 Bit8 BIT 0 Bit8 Bit0 Bit8 Bit0 Bit8 Bit0 Bit8 Bit0 Bit8 Bit0 Bit8 Bit0 Bit8 Bit0
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 673
Appendix G Detailed Register Map
0x0080-0x00AF ATD (Analog-to-Digital Converter 10 Bit 16 Channel) (Sheet 3 of 3)
Address Name 7 6 5 4 3 2 1 0
0x009E 0x009F 0x00A0 0x00A1 0x00A2 0x00A3 0x00A4 0x00A5 0x00A6 0x00A7 0x00A8 0x00A9 0x00AA 0x00AB 0x00AC 0x00AD 0X00AE 0x00AF
ATDDR7H ATDDR7L ATDDR8H ATDDR8L ATDDR9H ATDDR9L ATDDR10H ATDDR10L ATDDR11H ATDDR11L ATDDR12H ATDDR12L ATDDR13H ATDDR13L ATDDR14H ATDDR14L ATDDR15H ATDDR15L
R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W
Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7
14 6 14 6 14 6 14 6 14 6 14 6 14 6 14 6 14 6
13 5 13 5 13 5 13 5 13 5 13 5 13 5 13 5 13 5
12 4 12 4 12 4 12 4 12 4 12 4 12 4 12 4 12 4
11 3 11 3 11 3 11 3 11 3 11 3 11 3 11 3 11 3
10 2 10 2 10 2 10 2 10 2 10 2 10 2 10 2 10 2
9 1 9 1 9 1 9 1 9 1 9 1 9 1 9 1 9 1
Bit8 Bit0 Bit8 Bit0 Bit8 Bit0 Bit8 Bit0 Bit8 Bit0 Bit8 Bit0 Bit8 Bit0 Bit8 Bit0 Bit8 Bit0
0x00B0-0x00BF Reserved
Address Name 7 6 5 4 3 2 1 0
0x00B0- 0x00BF
Reserved
R W
0
0
0
0
0
0
0
0
MC9S12HZ256 Data Sheet, Rev. 2.05 674 Freescale Semiconductor
Appendix G Detailed Register Map
0x00C0-0x00C7 IIC (Inter IC Bus)
Address Name 7 6 5 4 3 2 1 0
0x00C0 0x00C1 0x00C2 0x00C3 0x00C4 0x00C5- 0x00C7
IBAD IBFD IBCR IBSR IBDR Reserved
R W R W R W R W R W R W
ADR7 IBC7 IBEN TCF
ADR6 IBC6 IBIE IAAS
ADR5 IBC5 MS/SL IBB
ADR4 IBC4 Tx/Rx IBAL D4 0
ADR3 IBC3 TXAK 0
ADR2 IBC2 0 RSTA SRW
ADR1 IBC1 0
0 IBC0 IBSWAI RXAK
IBIF D1 0
D7 0
D6 0
D5 0
D3 0
D2 0
D0 0
0x00C8-0x00CF SCI0 (Asynchronous Serial Interface)
Address Name 7 6 5 4 3 2 1 0
0x00C8 0x00C9 0x00CA 0x00CB 0x00CC 0x00CD 0x00CE 0x00CF
SCI0BDH SCI0BDL SCI0CR1 SCI0CR2 SCI0SR1 SCI0SR2 SCI0DRH SCI0DRL
R W R W R W R W R W R W R W R W
IREN SBR7 LOOPS TIE TDRE 0 R8 R7 T7
TNP1 SBR6 SCISWAI TCIE TC 0
TNP0 SBR5 RSRC RIE RDRF 0 0 R5 T5
SBR12 SBR4 M ILIE IDLE
SBR11 SBR3 WAKE TE OR
SBR10 SBR2 ILT RE NF
SBR9 SBR1 PE RWU FE
SBR8 SBR0 PT SBK PF RAF 0 R0 T0
TXPOL 0 R4 T4
RXPOL 0 R3 T3
BRK13 0 R2 T2
TXDIR 0 R1 T1
T8 R6 T6
0x00D0-0x00D7 SCI1 (Asynchronous Serial Interface)
Address Name 7 6 5 4 3 2 1 0
0x00D0 0x00D1 0x00D2 0x00D3 0x00D4
SCI1BDH SCI1BDL SCI1CR1 SCI1CR2 SCI1SR1
R W R W R W R W R W
IREN SBR7 LOOPS TIE TDRE
TNP1 SBR6 SCISWAI TCIE TC
TNP0 SBR5 RSRC RIE RDRF
SBR12 SBR4 M ILIE IDLE
SBR11 SBR3 WAKE TE OR
SBR10 SBR2 ILT RE NF
SBR9 SBR1 PE RWU FE
SBR8 SBR0 PT SBK PF
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 675
Appendix G Detailed Register Map
0x00D0-0x00D7 SCI1 (Asynchronous Serial Interface) (continued)
Address Name 7 6 5 4 3 2 1 0
0x00D5 0x00D6 0x00D7
SCI1SR2 SCI1DRH SCI1DRL
R W R W R W
0 R8 R7 T7
0
0 0 R5 T5
TXPOL 0 R4 T4
RXPOL 0 R3 T3
BRK13 0 R2 T2
TXDIR 0 R1 T1
RAF 0 R0 T0
T8 R6 T6
0x00D8-0x00DF SPI (Serial Peripheral Interface)
Address Name 7 6 5 4 3 2 1 0
0x00D8 0x00D9 0x00DA 0x00DB 0x00DC 0x00DD 0x00DE- 0x00DF
SPICR1 SPICR2 SPIBR SPISR Reserved SPIDR Reserved
R W R W R W R W R W R W R W
SPIE 0 0 SPIF 0
SPE 0
SPTIE 0
MSTR MODFEN SPPR0 MODF 0
CPOL BIDIROE 0 0 0
CPHA 0
SSOE SPISWAI SPR1 0 0
LSBFE SPC0 SPR0 0 0
SPPR2 0 0
SPPR1 SPTEF 0
SPR2 0 0
Bit7 0
6 0
5 0
4 0
3 0
2 0
1 0
Bit0 0
0x00E0-0x00FF PWM (Pulse Width Modulator 8 Bit 6 Channel) (Sheet 1 of 2)
Address Name 7 6 5 4 3 2 1 0
0x00E0 0x00E1 0x00E2 0x00E3 0x00E4 0x00E5 0x00E6 0x00E7 0x00E8
PWME PWMPOL PWMCLK PWMPRCLK PWMCAE PWMCTL PWMTST Test Only PWMPRSC Test Only PWMSCLA
R W R W R W R W R W R W R W R W R W
0 0 0 0 0 0 0 0
0 0 0
PWME5 PPOL5 PCLK5 PCKB1 CAE5 CON23 0 0
PWME4 PPOL4 PCLK4 PCKB0 CAE4 CON01 0 0
PWME3 PPOL3 PCLK3 0
PWME2 PPOL2 PCLK2 PCKA2 CAE2 PFRZ 0 0
PWME1 PPOL1 PCLK1 PCKA1 CAE1 0 0 0
PWME0 PPOL0 PCLK0 PCKA0 CAE0 0 0 0
PCKB2 0
CAE3 PSWAI 0 0
CON45 0 0
Bit 7
6
5
4
3
2
1
Bit 0
MC9S12HZ256 Data Sheet, Rev. 2.05 676 Freescale Semiconductor
Appendix G Detailed Register Map
0x00E0-0x00FF PWM (Pulse Width Modulator 8 Bit 6 Channel) (Sheet 2 of 2)
Address Name 7 6 5 4 3 2 1 0
0x00E9 0x00EA 0x00EB 0x00EC 0x00ED 0x00EE 0x00EF 0x00F0 0x00F1 0x00F2 0x00F3 0x00F4 0x00F5 0x00F6 0x00F7 0x00F8 0x00F9 0x00FA 0x00FB 0x00FC 0x00FD 0x00FE 0x00FF
PWMSCLB PWMSCNTA Test Only PWMSCNTB Test Only PWMCNT0 PWMCNT1 PWMCNT2 PWMCNT3 PWMCNT4 PWMCNT5 PWMPER0 PWMPER1 PWMPER2 PWMPER3 PWMPER4 PWMPER5 PWMDTY0 PWMDTY1 PWMDTY2 PWMDTY3 PWMDTY4 PWMDTY5 PWMSDN Reserved
R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W
Bit 7 0 0 Bit 7 0 Bit 7 0 Bit 7 0 Bit 7 0 Bit 7 0 Bit 7 0 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 PWMIF 0
6 0 0 6 0 6 0 6 0 6 0 6 0 6 0 6 6 6 6 6 6 6 6 6 6 6 6 PWMIE 0
5 0 0 5 0 5 0 5 0 5 0 5 0 5 0 5 5 5 5 5 5 5 5 5 5 5 5 PWMRSTRT 0
4 0 0 4 0 4 0 4 0 4 0 4 0 4 0 4 4 4 4 4 4 4 4 4 4 4 4 PWMLVL 0
3 0 0 3 0 3 0 3 0 3 0 3 0 3 0 3 3 3 3 3 3 3 3 3 3 3 3 0 0
2 0 0 2 0 2 0 2 0 2 0 2 0 2 0 2 2 2 2 2 2 2 2 2 2 2 2 PWM5IN 0
1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 PWM5INL 0
Bit 0 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 PWM5ENA 0
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 677
Appendix G Detailed Register Map
0x0100-0x010F Flash Control Register (fts256k2)
Address Name 7 6 5 4 3 2 1 0
0x0100 0x0101 0x0102 0x0103 0x0104 0x0105 0x0106 0x0107 0x0108 0x0109 0x010A 0x010B 0x010C- 0x010F
FCLKDIV FSEC Reserved FCNFG FPROT FSTAT FCMD FCTL FADDRHI FADDRLO FDATAHI FDATALO Reserved
R FDIVLD PRDIV8 W R KEYEN W R 0 0 W R CBEIE CCIE W R RNV6 FPOPEN W R CCIF CBEIF W R 0 W R NV7 NV6 W R W R W R W R W R 0 0 W
FDIV5 RNV5 0
FDIV4 RNV4
FDIV3 RNV3 0 0
FDIV2 RNV2 0 0
FDIV1 SEC 0 0
FDIV0
WRALL 0
0
KEYACC FPHDIS PVIOL
BKSEL FPLS
FPHS ACCERR 0
FPLDIS BLANK 0
0
CMDB NV5 NV4 NV3 NV2 NV1 NV0
FADDRHI FADDRLO FDATAHI FDATALO 0 0 0 0 0 0
0x0110-0x011B EEPROM Control Register (eets2k)
Address Name 7 6 5 4 3 2 1 0
0x0110 0x0111- 0x0112 0x0113 0x0114 0x0115 0x0116 0x0117 0x0118
ECLKDIV Reserved ECNFG EPROT ESTAT ECMD Reserved EADDRHI
R EDIVLD W R 0 W R CBEIE W R EPOPEN W R CBEIF W R 0 W R 0 W R 0 W
PRDIV8 0
EDIV5 0 0 NV5
EDIV4 0 0 NV4
EDIV3 0 0
EDIV2 0 0
EDIV1 0 0
EDIV0 0 0
CCIE NV6 CCIF
EPDIS 0 0 0 0
EP2 BLANK
EP1 0 0 0
EP0 0
PVIOL CMDB5 0 0
ACCERR 0 0 0
CMDB6 0 0
CMDB2 0 0
CMDB0 0
EABHI
MC9S12HZ256 Data Sheet, Rev. 2.05 678 Freescale Semiconductor
Appendix G Detailed Register Map
0x0110-0x011B EEPROM Control Register (eets2k) (continued)
Address Name 7 6 5 4 3 2 1 0
0x0119 0x011A 0x011B
EADDRLO EDATAHI EDATALO
R W R W R W
EABLO EDHI EDLO
0x011C-0x011F Reserved Space
Address Name 7 6 5 4 3 2 1 0
0x011C- 0x011F
Reserved
R W
0
0
0
0
0
0
0
0
0x0120-0x0137
Address Name
LCD (Liquid Crystal Display 32 frontplanes, 4 backplanes)
7 6 5 4 3 2 1 0
0x0120 0x0121 0x0122 0x0123 0x0124 0x0125 0x0126- 0x0127 0x0128 0x0129 0x012A 0x012B 0x012C 0x012D 0x012E 0x012F
LCDCR0 LCDCR1 FPENR0 FPENR1 FPENR2 FPENR3 Reserved LCDRAM0 LCDRAM1 LCDRAM2 LCDRAM3 LCDRAM4 LCDRAM5 LCDRAM6 LCDRAM7
R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W
LCDEN 0
0 0
LCLK2 0
LCLK1 0
LCLK0 0
BIAS 0
DUTY1 LCDSWAI FPEN1 FPEN9 FPEN17 FPEN25 0
DUTY0 LCDRPST P FPEN0 FPEN8 FPEN16 FPEN24 0
FPEN7 FPEN15 FPEN23 FPEN31 0
FPEN6 FPEN14 FPEN22 FPEN30 0
FPEN5 FPEN13 FPEN21 FPEN29 0
FPEN4 FPEN12 FPEN20 FPEN28 0
FPEN3 FPEN11 FPEN19 FPEN27 0
FPEN2 FPEN10 FPEN18 FPEN26 0
FP1BP3 FP3BP3 FP5BP3 FP7BP3 FP9BP3 FP11BP3 FP13BP3 FP15BP3
FP1BP2 FP3BP2 FP5BP2 FP7BP2 FP9BP2 FP11BP2 FP13BP2 FP15BP2
FP1BP1 FP3BP1 FP5BP1 FP7BP1 FP9BP1 FP11BP1 FP13BP1 FP15BP1
FP1BP0 FP3BP0 FP5BP0 FP7BP0 FP9BP0 FP11BP0 FP13BP0 FP15BP0
FP0BP3 FP2BP3 FP4BP3 FP6BP3 FP8BP3 FP10BP3 FP12BP3 FP14BP3
FP0BP2 FP2BP2 FP4BP2 FP6BP2 FP8BP2 FP10BP2 FP12BP2 FP14BP2
FP0BP1 FP2BP1 FP4BP1 FP6BP1 FP8BP1 FP10BP1 FP12BP1 FP14BP1
FP0BP0 FP2BP0 FP4BP0 FP6BP0 FP8BP0 FP10BP0 FP12BP0 FP14BP0
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 679
Appendix G Detailed Register Map
0x0120-0x0137
Address Name
LCD (Liquid Crystal Display 32 frontplanes, 4 backplanes) (continued)
7 6 5 4 3 2 1 0
0x0130 0x0131 0x0132 0x0133 0x0134 0x0135 0x0136 0x0137
LCDRAM8 LCDRAM9 LCDRAM10 LCDRAM11 LCDRAM12 LCDRAM13 LCDRAM14 LCDRAM15
R W R W R W R W R W R W R W R W
FP17BP3 FP19BP3 FP21BP3 FP23BP3 FP25BP3 FP27BP3 FP29BP3 FP31BP3
FP17BP2 FP19BP2 FP21BP2 FP23BP2 FP25BP2 FP27BP2 FP29BP2 FP31BP2
FP17BP1 FP19BP1 FP21BP1 FP23BP1 FP25BP1 FP27BP1 FP29BP1 FP31BP1
FP17BP0 FP19BP0 FP21BP0 FP23BP0 FP25BP0 FP27BP0 FP29BP0 FP31BP0
FP16BP3 FP18BP3 FP20BP3 FP22BP3 FP24BP3 FP26BP3 FP28BP3 FP30BP3
FP16BP2 FP18BP2 FP20BP2 FP22BP2 FP24BP2 FP26BP2 FP28BP2 FP30BP2
FP16BP1 FP18BP1 FP20BP1 FP22BP1 FP24BP1 FP26BP1 FP28BP1 FP30BP1
FP16BP0 FP18BP0 FP20BP0 FP22BP0 FP24BP0 FP26BP0 FP28BP0 FP30BP0
0x0140-0x017F CAN0 (Scalable CAN-MSCAN)
Address Name 7 6 5 4 3 2 1 0
0x0140 0x0141 0x0142 0x0143 0x0144 0x0145 0x0146 0x0147 0x0148 0x0149 0x014A 0x014B 0x014C- 0x014D
CAN0CTL0 CAN0CTL1 CAN0BTR0 CAN0BTR1 CAN0RFLG CAN0RIER CAN0TFLG CAN0TIER CAN0TARQ CAN0TAAK CAN0TBSEL CAN0IDAC Reserved
R W R W R W R W R W R W R W R W R W R W R W R W R W
RXFRM CANE SJW1 SAMP WUPIF WUPIE 0 0 0 0 0 0 0
RXACT
CSWAI LOOPB BRP5 TSEG21 RSTAT1
SYNCH
TIME 0
WUPE WUPM BRP2 TSEG12 TSTAT0
SLPRQ SLPAK
INITRQ INITAK
CLKSRC SJW0 TSEG22 CSCIF CSCIE 0 0 0 0 0 0 0
LISTEN BRP4 TSEG20 RSTAT0
BRP3 TSEG13 TSTAT1
BRP1 TSEG11 OVRIF OVRIE TXE1 TXEIE1 ABTRQ1 ABTAK1
BRP0 TSEG10 RXF RXFIE TXE0 TXEIE0 ABTRQ0 ABTAK0
RSTATE1 0 0 0 0 0
RSTATE0 0 0 0 0 0
TSTATE1 0 0 0 0 0 0 0
TSTATE0 TXE2 TXEIE2 ABTRQ2 ABTAK2
TX2 IDHIT2 0
TX1 IDHIT1 0
TX0 IDHIT0 0
IDAM1 0
IDAM0 0
MC9S12HZ256 Data Sheet, Rev. 2.05 680 Freescale Semiconductor
Appendix G Detailed Register Map
0x0140-0x017F CAN0 (Scalable CAN-MSCAN) (continued)
Address Name 7 6 5 4 3 2 1 0
0x014E 0x014F 0x0150- 0x0153
CAN0RXERR CAN0TXERR CAN0IDAR0- CAN0IDAR3
0x0154- CAN0IDMR0- 0x0157 CAN0IDMR3 0x0158- 0x015B CAN0IDAR4- CAN0IDAR7
0x015C- CAN0IDMR4- 0x015F CAN0IDMR7 0x0160- 0x016F 0x0170- 0x017F CAN0RXFG CAN0TXFG
R RXERR7 W R TXERR7 W R AC7 W R AM7 W R AC7 W R AM7 W R W R W
RXERR6 TXERR6
RXERR5 TXERR5
RXERR4 TXERR4
RXERR3 TXERR3
RXERR2 TXERR2
RXERR1 TXERR1
RXERR0 TXERR0
AC6 AM6 AC6 AM6
AC5 AM5 AC5 AM5
AC4 AM4 AC4 AM4
AC3 AM3 AC3 AM3
AC2 AM2 AC2 AM2
AC1 AM1 AC1 AM1
AC0 AM0 AC0 AM0
FOREGROUND RECEIVE BUFFER see Table 22-22
FOREGROUND TRANSMIT BUFFER see Table 22-22
Table 22-22. Detailed MSCAN Foreground Receive and Transmit Buffer Layout
Address Name 7 6 5 4 3 2 1 0
R 0x0160 R W R 0x0161 R W R 0x0162 R W R 0x0163 R W 0x0164- CAN0RDSR0- R 0x016B CAN0RDSR7 W R 0x016C CAN0RDLR W R 0x016D Reserved W R 0x016E CAN0RTSRH W R 0x016F CAN0RTSRL W Extended ID R CAN0TIDR0 W 0x0170 R Standard ID W
Extended ID Standard ID CAN0RIDR0 Extended ID Standard ID CAN0RIDR1 Extended ID Standard ID CAN0RIDR2 Extended ID Standard ID CAN0RIDR3
ID28 ID10 ID20 ID2 ID14
ID27 ID9 ID19 ID1 ID13
ID26 ID8 ID18 ID0 ID12
ID25 ID7 SRR=1 RTR ID11
ID24 ID6 IDE=1 IDE=0 ID10
ID23 ID5 ID17
ID22 ID4 ID16
ID21 ID3 ID15
ID9
ID8
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
RTR
DB7
DB6
DB5
DB4
DB3 DLC3
DB2 DLC2
DB1 DLC1
DB0 DLC0
TSR15 TSR7
TSR14 TSR6
TSR13 TSR5
TSR12 TSR4
TSR11 TSR3
TSR10 TSR2
TSR9 TSR1
TSR8 TSR0
ID28 ID10
ID27 ID9
ID26 ID8
ID25 ID7
ID24 ID6
ID23 ID5
ID22 ID4
ID21 ID3
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 681
Appendix G Detailed Register Map
Table 22-22. Detailed MSCAN Foreground Receive and Transmit Buffer Layout (continued)
Address Name 7 6 5 4 3 2 1 0
R W 0x0171 R Standard ID W Extended ID R CAN0TIDR2 W 0x0172 R Standard ID W Extended ID R CAN0TIDR3 W 0x0173 R Standard ID W 0x0174- CAN0TDSR0- R 0x017B CAN0TDSR7 W R 0x017C CAN0TDLR W R 0x017D CON0TTBPR W R 0x017E CAN0TTSRH W R 0x017F CAN0TTSRL W
Extended ID CAN0TIDR1
ID20 ID2 ID14
ID19 ID1 ID13
ID18 ID0 ID12
SRR=1 RTR ID11
IDE=1 IDE=0 ID10
ID17
ID16
ID15
ID9
ID8
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
RTR
DB7
DB6
DB5
DB4
DB3 DLC3
DB2 DLC2 PRIO2 TSR10 TSR2
DB1 DLC1 PRIO1 TSR9 TSR1
DB0 DLC0 PRIO0 TSR8 TSR0
PRIO7 TSR15 TSR7
PRIO6 TSR14 TSR6
PRIO5 TSR13 TSR5
PRIO4 TSR12 TSR4
PRIO3 TSR11 TSR3
0x0180-0x01BF CAN1 (Freescale's Scalable CAN-MSCAN)
Address Name 7 6 5 4 3 2 1 0
0x0180 0x0181 0x0182 0x0183 0x0184 0x0185 0x0186 0x0187 0x0188 0x0189
CAN1CTL0 CAN1CTL1 CAN1BTR0 CAN1BTR1 CAN1RFLG CAN1RIER CAN1TFLG CAN1TIER CAN1TARQ CAN1TAAK
R W R W R W R W R W R W R W R W R W R W
RXFRM CANE SJW1 SAMP WUPIF WUPIE 0 0 0 0
RXACT
CSWAI LOOPB BRP5 TSEG21 RSTAT1
SYNCH
TIME 0
WUPE WUPM BRP2 TSEG12 TSTAT0
SLPRQ SLPAK
INITRQ INITAK
CLKSRC SJW0 TSEG22 CSCIF CSCIE 0 0 0 0
LISTEN BRP4 TSEG20 RSTAT0
BRP3 TSEG13 TSTAT1
BRP1 TSEG11 OVRIF OVRIE TXE1 TXEIE1 ABTRQ1 ABTAK1
BRP0 TSEG10 RXF RXFIE TXE0 TXEIE0 ABTRQ0 ABTAK0
RSTATE1 0 0 0 0
RSTATE0 0 0 0 0
TSTATE1 0 0 0 0
TSTATE0 TXE2 TXEIE2 ABTRQ2 ABTAK2
MC9S12HZ256 Data Sheet, Rev. 2.05 682 Freescale Semiconductor
Appendix G Detailed Register Map
0x0180-0x01BF CAN1 (Freescale's Scalable CAN-MSCAN) (continued)
Address Name 7 6 5 4 3 2 1 0
0x018A 0x018B 0x018C- 0x018D 0x018E 0x018F 0x0190- 0x0193
CAN1TBSEL CAN1IDAC Reserved CAN1RXERR CAN1TXERR CAN1IDAR0- CAN1IDAR3
0x0194- CAN1IDMR0- 0x0197 CAN1IDMR3 0x0198- 0x019B CAN1IDAR4- CAN1IDAR7
0x019C- CAN1IDMR4- 0x019F CAN1IDMR7 0x01A0- 0x01AF 0x01B0- 0x01BF CAN1RXFG CAN1TXFG
R 0 W R 0 W R 0 W R RXERR7 W R TXERR7 W R AC7 W R AM7 W R AC7 W R AM7 W R W R W
0 0 0 RXERR6 TXERR6
0
0
0 0 0 RXERR3 TXERR3
TX2 IDHIT2 0 RXERR2 TXERR2
TX1 IDHIT1 0 RXERR1 TXERR1
TX0 IDHIT0 0 RXERR0 TXERR0
IDAM1 0 RXERR5 TXERR5
IDAM0 0 RXERR4 TXERR4
AC6 AM6 AC6 AM6
AC5 AM5 AC5 AM5
AC4 AM4 AC4 AM4
AC3 AM3 AC3 AM3
AC2 AM2 AC2 AM2
AC1 AM1 AC1 AM1
AC0 AM0 AC0 AM0
FOREGROUND RECEIVE BUFFER see Table 22-22
FOREGROUND TRANSMIT BUFFER see Table 22-22
Table 22-23. Detailed MSCAN Foreground Receive and Transmit Buffer Layout (Sheet 1 of 2)
Address Name 7 6 5 4 3 2 1 0
R 0x01A0 R W R 0x01A1 R W R 0x01A2 R W R 0x01A3 R W 0x01A4- CAN1RDSR0- R 0x01AB CAN1RDSR7 W R 0x01AC CAN1RDLR W R 0x01AD Reserved W R 0x01AE CAN1RTSRH W
Extended ID Standard ID CAN1RIDR0 Extended ID Standard ID CAN1RIDR1 Extended ID Standard ID CAN1RIDR2 Extended ID Standard ID CAN1RIDR3
ID28 ID10 ID20 ID2 ID14
ID27 ID9 ID19 ID1 ID13
ID26 ID8 ID18 ID0 ID12
ID25 ID7 SRR=1 RTR ID11
ID24 ID6 IDE=1 IDE=0 ID10
ID23 ID5 ID17
ID22 ID4 ID16
ID21 ID3 ID15
ID9
ID8
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
RTR
DB7
DB6
DB5
DB4
DB3 DLC3
DB2 DLC2
DB1 DLC1
DB0 DLC0
TSR15
TSR14
TSR13
TSR12
TSR11
TSR10
TSR9
TSR8
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 683
Appendix G Detailed Register Map
Table 22-23. Detailed MSCAN Foreground Receive and Transmit Buffer Layout (Sheet 2 of 2)
Address Name 7 6 5 4 3 2 1 0
R 0x01AF CAN1RTSRL W Extended ID R CAN1TIDR0 W 0x01B0 R Standard ID W Extended ID R CAN1TIDR1 W 0x01B1 R Standard ID W Extended ID R CAN1TIDR2 W 0x01B2 R Standard ID W Extended ID R CAN1TIDR3 W 0x01B3 R Standard ID W 0x01B4- CAN1TDSR0- R 0x01BB CAN1TDSR7 W R 0x01BC CAN1TDLR W R 0x01BD CON1TTBPR W R 0x01BE CAN1TTSRH W R 0x01BF CAN1TTSRL W
TSR7
TSR6
TSR5
TSR4
TSR3
TSR2
TSR1
TSR0
ID28 ID10 ID20 ID2 ID14
ID27 ID9 ID19 ID1 ID13
ID26 ID8 ID18 ID0 ID12
ID25 ID7 SRR=1 RTR ID11
ID24 ID6 IDE=1 IDE=0 ID10
ID23 ID5 ID17
ID22 ID4 ID16
ID21 ID3 ID15
ID9
ID8
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
RTR
DB7
DB6
DB5
DB4
DB3 DLC3
DB2 DLC2 PRIO2 TSR10 TSR2
DB1 DLC1 PRIO1 TSR9 TSR1
DB0 DLC0 PRIO0 TSR8 TSR0
PRIO7 TSR15 TSR7
PRIO6 TSR14 TSR6
PRIO5 TSR13 TSR5
PRIO4 TSR12 TSR4
PRIO3 TSR11 TSR3
0x01C0-0x01FF MC (Motor Controller 10bit 8 channels)
Address Name 7 6 5 4 3 2 1 0
0x01C0 0x01C1 0x01C2 0x01C3 0x01C4- 0x01CF 0x01D0- 0x01D7 0x01D8- 0x01DF
MCCTL0 MCCTL1 MCPER (hi) MCPER (lo) Reserved MCCC0- MCCC7 Reserved
R 0 W R RECIRC W R 0 W R P7 W R 0 W R OM1 W R 0 W
MCPRE1 0 0
MCPRE0 0 0
MCSWAI 0 0
FAST 0 0
DITH 0
0 0
MCTOIF MCTOIE P8 P0 0
P10 P2 0 0 0
P9 P1 0
P6 0
P5 0
P4 0
P3 0 0 0
OM0 0
AM1 0
AM0 0
CD1 0
CD0 0
MC9S12HZ256 Data Sheet, Rev. 2.05 684 Freescale Semiconductor
Appendix G Detailed Register Map
0x01C0-0x01FF MC (Motor Controller 10bit 8 channels) (continued)
Address Name 7 6 5 4 3 2 1 0
0x01E0 0x01E1 0x01E2 0x01E3 0x01E4 0x01E5 0x01E6 0x01E7 0x01E8 0x01E9 0x01EA 0x01EB 0x01EC 0x01ED 0x01EE 0x01EF 0x01F0- 0x01FF
MCDC0 (hi) MCDC0 (lo) MCDC1 (hi) MCDC1 (lo) MCDC2 (hi) MCDC2 (lo) MCDC3 (hi) MCDC3 (lo) MCDC4 (hi) MCDC4 (lo) MCDC5 (hi) MCDC5 (lo) MCDC6 (hi) MCDC6 (lo) MCDC7 (hi) MCDC7 (lo) Reserved
R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W
S D7 S D7 S D7 S D7 S D7 S D7 S D7 S D7 0
S
S
S
S
D10 D2 D10 D2 D10 D2 D10 D2 D10 D2 D10 D2 D10 D2 D10 D2 0
D9 D1 D9 D1 D9 D1 D9 D1 D9 D1 D9 D1 D9 D1 D9 D1 0
D8 D0 D8 D0 D8 D0 D8 D0 D8 D0 D8 D0 D8 D0 D8 D0 0
D6 S
D5 S
D4 S
D3 S
D6 S
D5 S
D4 S
D3 S
D6 S
D5 S
D4 S
D3 S
D6 S
D5 S
D4 S
D3 S
D6 S
D5 S
D4 S
D3 S
D6 S
D5 S
D4 S
D3 S
D6 S
D5 S
D4 S
D3 S
D6 0
D5 0
D4 0
D3 0
0x0200-0x027F PIM (Port Integration Module) (Sheet 1 of 4)
Address Name 7 6 5 4 3 2 1 0
0x0200 0x0201 0x0202 0x0203
PTT PTIT DDRT RDRT
R W R W R W R W
PTT7 PTIT7
PTT6 PTIT6
PTT5 PTIT5
PTT4 PTIT4
PTT3 PTIT3
PTT2 PTIT2
PTT1 PTIT1
PTT0 PTIT0
DDRT7 RDRT7
DDRT7 RDRT6
DDRT5 RDRT5
DDRT4 RDRT4
DDRT3 RDRT3
DDRT2 RDRT2
DDRT1 RDRT1
DDRT0 RDRT0
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 685
Appendix G Detailed Register Map
0x0200-0x027F PIM (Port Integration Module) (Sheet 2 of 4)
Address Name 7 6 5 4 3 2 1 0
0x0204 0x0205 0x0206- 0x0207 0x0208 0x0209 0x020A 0x020B 0x020C 0x020D 0x020E 0x020F 0x0210 0x0211 0x0212 0x0213 0x0214 0x0215 0x0216 0x0217 0x0218 0x0219 0x021A 0x021B
PERT PPST Reserved PTS PTIS DDRS RDRS PERS PPSS WOMS Reserved PTM PTIM DDRM RDRM PERM PPSM WOMM Reserved PTP PTIP DDRP RDRP
R PERT7 W R PPST7 W R 0 W R PTS7 W R PTIS7 W R DDRS7 W R RDRS7 W R PERS7 W R PPSS7 W R WOMS7 W R 0 W R 0 W R 0 W R 0 W R 0 W R 0 W R 0 W R 0 W R 0 W R 0 W R 0 W R 0 W R 0 W
PERT6 PPST6 0
PERT5 PPST5 0
PERT4 PPST4 0
PERT3 PPST3 0 0 0 0 0 0 0 0 0
PERT2 PPST2 0 0 0 0 0 0 0 0 0
PERT1 PPST1 0
PERT0 PPST0 0
PTS6 PTIS6
PTS5 PTIS5
PTS4 PTIS4
PTS1 PTIS1
PTS0 PTIS0
DDRS6 RDRS6 PERS6 PPSS6 WOMS6 0 0 0 0 0 0 0 0 0 0 0 0 0
DDRS5 RDRS5 PERS5 PPSS5 WOMS5 0
DDRS4 RDRS4 PERS4 PPSS4 WOMS4 0
DDRS1 RDRS1 PERS1 PPSS1 WOMS1 0 0 0 0 0 0 0 0 0
DDRS0 RDRS0 PERS0 PPSS0 WOMS0 0 0 0 0 0 0 0 0 0
PTM5 PTIM5
PTM4 PTIM4
PTM3 PTIM3
PTM2 PTIM2
DDRM5 RDRM5 PERM5 PPSM5 WOMM5 0
DDRM4 RDRM4 PERM4 PPSM4 WOMM4 0
DDRM3 RDRM3 PERM3 PPSM3 WOMM3 0
DDRM2 RDRM2 PERM2 PPSM2 WOMM2 0
PTP5 PTIP5
PTP4 PTIP4
PTP3 PTIP3
PTP2 PTIP2
PTP1 PTIP1
PTP0 PTIP0
DDRP5 RDRP5
DDRP4 RDRP4
DDRP3 RDRP3
DDRP2 RDRP2
DDRP1 RDRP1
DDRP0 RDRP0
MC9S12HZ256 Data Sheet, Rev. 2.05 686 Freescale Semiconductor
Appendix G Detailed Register Map
0x0200-0x027F PIM (Port Integration Module) (Sheet 3 of 4)
Address Name 7 6 5 4 3 2 1 0
0x021C 0x021D 0x021E 0x021F 0x0220- 0x022F 0x0230 0x0231 0x0232 0x0233 0x0234 0x0235 0x0236- 0x0237 0x0238 0x0239 0x023A 0x023B 0x023C 0x023D 0x023E- 0x023F 0x0240 0x0241 0x0242 0x0243
PERP PPSP WOMP Reserved Reserved PTL PTIL DDRL RDRL PERL PPSL Reserved PTU PTIU DDRU SRRU PERU PPSU Reserved PTV PTIV DDRV SRRV
R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W
0 0 0 0 0
0 0 0 0 0
PERP5 PPSP5 WOMP5 0 0
PERP4 PPSP4 WOMP4 0 0
PERP3 PPSP3 0 0 0
PERP2 PPSP2 WOMP2 0 0
PERP1 PPSP1 0 0 0
PERP0 PPSS0 WOMP0 0 0
PTL7 PTIL7
PTL6 PTIL6
PTL5 PTIL5
PTL4 PTIL4
PTL3 PTIL3
PTL2 PTIL2
PTL1 PTIL1
PTL0 PTIL0
DDRL7 RDRL7 PERL7 PPSL7 0
DDRL7 RDRL6 PERL6 PPSL6 0
DDRL5 RDRL5 PERL5 PPSL5 0
DDRL4 RDRL4 PERL4 PPSL4 0
DDRL3 RDRL3 PERL3 PPSL3 0
DDRL2 RDRL2 PERL2 PPSL2 0
DDRL1 RDRL1 PERL1 PPSL1 0
DDRL0 RDRL0 PERL0 PPSL0 0
PTU7 PTIU7
PTU6 PTIU6
PTU5 PTIU5
PTU4 PTIU4
PTU3 PTIU3
PTU2 PTIU2
PTU1 PTIU1
PTU0 PTIU0
DDRU7 SRRU7 PERU7 PPSU7 0
DDRU7 SRRU6 PERU6 PPSU6 0
DDRU5 SRRU5 PERU5 PPSU5 0
DDRU4 SRRU4 PERU4 PPSU4 0
DDRU3 SRRU3 PERU3 PPSU3 0
DDRU2 SRRU2 PERU2 PPSU2 0
DDRU1 SRRU1 PERU1 PPSU1 0
DDRU0 SRRU0 PERU0 PPSU0 0
PTV7 PTIV7
PTV6 PTIV6
PTV5 PTIV5
PTV4 PTIV4
PTV3 PTIV3
PTV2 PTIV2
PTV1 PTIV1
PTV0 PTIV0
DDRV7 SRRV7
DDRV7 SRRV6
DDRV5 SRRV5
DDRV4 SRRV4
DDRV3 SRRV3
DDRV2 SRRV2
DDRV1 SRRV1
DDRV0 SRRV0
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 687
Appendix G Detailed Register Map
0x0200-0x027F PIM (Port Integration Module) (Sheet 4 of 4)
Address Name 7 6 5 4 3 2 1 0
0x0244 0x0245 0x0246- 0x024F 0x0250 0x0251 0x0252 0x0253 0x0254 0x0255 0x0256 0x0257 0x0258 0x0259 0x025A 0x025B 0x025C 0x025D 0x025E 0x025F
PERV PPSV Reserved Reserved PTAD Reserved PTIAD Reserved DDRAD Reserved RDRAD Reserved PERAD Reserved PPSAD Reserved PIEAD Reserved PIFAD
R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W
PERV7 PPSV7 0 0
PERV6 PPSV6 0 0
PERV5 PPSV5 0 0
PERV4 PPSV4 0 0
PERV3 PPSV3 0 0
PERV2 PPSV2 0 0
PERV1 PPSV1 0 0
PERV0 PPSV0 0 0
PTAD7 0
PTAD6 0
PTAD5 0
PTAD4 0
PTAD3 0
PTAD2 0
PTAD1 0
PTAD0 0
PTIAD7 0
PTIAD6 0
PTIAD5 0
PTIAD4 0
PTIAD3 0
PTIAD2 0
PTIAD1 0
PTIAD0 0
DDRAD7 0
DDRAD6 0
DDRAD5 0
DDRAD4 0
DDRAD3 0
DDRAD2 0
DDRAD1 0
DDRAD0 0
RDRAD7 0
RDRAD6 0
RDRAD5 0
RDRAD4 0
RDRAD3 0
RDRAD2 0
RDRAD1 0
RDRAD0 0
PERAD7 0
PERAD6 0
PERAD5 0
PERAD4 0
PERAD3 0
PERAD2 0
PERAD1 0
PERAD0 0
PPSAD7 0
PPSAD6 0
PPSAD5 0
PPSAD4 0
PPSAD3 0
PPSAD2 0
PPSAD1 0
PPSAD0 0
PIEAD7 0
PIEAD6 0
PIEAD5 0
PIEAD4 0
PIEAD3 0
PIEAD2 0
PIEAD1 0
PIEAD0 0
PIFAD7
PIFAD6
PIFAD5
PIFAD4
PIFAD3
PIFAD2
PIFAD1
PIFAD0
0x0260-0x0287
Address Name
Reserved
7 6 5 4 3 2 1 0
0x0260- 0x0287
Reserved
R W
0
0
0
0
0
0
0
0
MC9S12HZ256 Data Sheet, Rev. 2.05 688 Freescale Semiconductor
Appendix G Detailed Register Map
0x0288-0x028F SSD0 (Stepper Stall Detector)
Address Name 7 6 5 4 3 2 1 0
0x0288 0x0289 0x028A 0x028B 0x028C 0x028D 0x028E 0x028F
R RTZ0CTL W R MDC0CTL W R SSD0CTL W R SSD0FLG W R MDC0CNT(hi) W R MDC0CNT(lo) W R ITG0ACC(hi) W R ITG0ACC(lo) W
ITG MCZIE RTZE MCZIF
DCOIL MODMC SDCPU 0
RCIR RDMCL SSDWAI 0
POL PRE FTST 0
0 0 FLMC 0 0
0 0
STEP AOVIE ACLKS 0 AOVIF
MCEN 0 0
MDCCNT[15:8] MDCCNT[7:0] ITGACC[15:8] ITGACC[7:0]
0x0290-0x0297
Address Name
SSD1 (Stepper Stall Detector)
7 6 5 4 3 2 1 0
0x0290 0x0291 0x0292 0x0293 0x0294 0x0295 0x0296 0x0297
R RTZ1CTL W R MDC1CTL W R SSD1CTL W R SSD1FLG W R MDC1CNT(hi) W R MDC1CNT(lo) W R ITG1ACC(hi) W R ITG1ACC(lo) W
ITG MCZIE RTZE MCZIF
DCOIL MODMC SDCPU 0
RCIR RDMCL SSDWAI 0
POL PRE FTST 0
0 0 FLMC 0 0
0 0
STEP AOVIE ACLKS 0 AOVIF
MCEN 0 0
MDCCNT[15:8] MDCCNT[7:0] ITGACC[15:8] ITGACC[7:0]
0x0298-0x029F SSD2 (Stepper Stall Detector)
Address Name 7 6 5 4 3 2 1 0
0x0298 0x0299 0x029A
RTZ2CTL MDC2CTL SSD2CTL
R W R W R W
ITG MCZIE RTZE
DCOIL MODMC SDCPU
RCIR RDMCL SSDWAI
POL PRE FTST
0 0 FLMC 0
0 0
STEP AOVIE ACLKS
MCEN 0
MC9S12HZ256 Data Sheet, Rev. 2.05 Freescale Semiconductor 689
Appendix G Detailed Register Map
0x0298-0x029F SSD2 (Stepper Stall Detector) (continued)
Address Name 7 6 5 4 3 2 1 0
0x029B 0x029C 0x029D 0x029E 0x029F
R SSD2FLG W R MDC2CNT(hi) W R MDC2CNT(lo) W R ITG2ACC(hi) W R ITG2ACC(lo) W
MCZIF
0
0
0
0
0
0
AOVIF
MDCCNT[15:8] MDCCNT[7:0] ITGACC[15:8] ITGACC[7:0]
0x02A0-0x02A7 SSD3 (Stepper Stall Detector)
Address Name 7 6 5 4 3 2 1 0
0x02A0 0x02A1 0x02A2 0x02A3 0x02A4 0x02A5 0x02A6 0x02A7
R RTZ3CTL W R MDC3CTL W R SSD3CTL W R SSD3FLG W R MDC3CNT(hi) W R MDC3CNT(lo) W R ITG3ACC(hi) W R ITG3ACC(lo) W
ITG MCZIE RTZE MCZIF
DCOIL MODMC SDCPU 0
RCIR RDMCL SSDWAI 0
POL PRE FTST 0
0 0 FLMC 0 0
0 0
STEP AOVIE ACLKS 0 AOVIF
MCEN 0 0
MDCCNT[15:8] MDCCNT[7:0] ITGACC[15:8] ITGACC[7:0]
0x02A8-0x03FF Reserved
Address Name 7 6 5 4 3 2 1 0
0x02A8- 0x03FF
Reserved
R W
0
0
0
0
0
0
0
0
MC9S12HZ256 Data Sheet, Rev. 2.05 690 Freescale Semiconductor
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